drivers/dma/tegra20-apb-dma.c

   1 /*
   2  * DMA driver for Nvidia's Tegra20 APB DMA controller.
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/bitops.h>
  20 #include <linux/clk.h>
  21 #include <linux/delay.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/slab.h>
  34
  35 #include <mach/clk.h>
  36 #include "dmaengine.h"
  37
  38 #define TEGRA_APBDMA_GENERAL                    0x0
  39 #define TEGRA_APBDMA_GENERAL_ENABLE             BIT(31)
  40
  41 #define TEGRA_APBDMA_CONTROL                    0x010
  42 #define TEGRA_APBDMA_IRQ_MASK                   0x01c
  43 #define TEGRA_APBDMA_IRQ_MASK_SET               0x020
  44
  45 /* CSR register */
  46 #define TEGRA_APBDMA_CHAN_CSR                   0x00
  47 #define TEGRA_APBDMA_CSR_ENB                    BIT(31)
  48 #define TEGRA_APBDMA_CSR_IE_EOC                 BIT(30)
  49 #define TEGRA_APBDMA_CSR_HOLD                   BIT(29)
  50 #define TEGRA_APBDMA_CSR_DIR                    BIT(28)
  51 #define TEGRA_APBDMA_CSR_ONCE                   BIT(27)
  52 #define TEGRA_APBDMA_CSR_FLOW                   BIT(21)
  53 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT          16
  54 #define TEGRA_APBDMA_CSR_WCOUNT_MASK            0xFFFC
  55
  56 /* STATUS register */
  57 #define TEGRA_APBDMA_CHAN_STATUS                0x004
  58 #define TEGRA_APBDMA_STATUS_BUSY                BIT(31)
  59 #define TEGRA_APBDMA_STATUS_ISE_EOC             BIT(30)
  60 #define TEGRA_APBDMA_STATUS_HALT                BIT(29)
  61 #define TEGRA_APBDMA_STATUS_PING_PONG           BIT(28)
  62 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT         2
  63 #define TEGRA_APBDMA_STATUS_COUNT_MASK          0xFFFC
  64
  65 /* AHB memory address */
  66 #define TEGRA_APBDMA_CHAN_AHBPTR                0x010
  67
  68 /* AHB sequence register */
  69 #define TEGRA_APBDMA_CHAN_AHBSEQ                0x14
  70 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB            BIT(31)
  71 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8         (0 << 28)
  72 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16        (1 << 28)
  73 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32        (2 << 28)
  74 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64        (3 << 28)
  75 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128       (4 << 28)
  76 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP           BIT(27)
  77 #define TEGRA_APBDMA_AHBSEQ_BURST_1             (4 << 24)
  78 #define TEGRA_APBDMA_AHBSEQ_BURST_4             (5 << 24)
  79 #define TEGRA_APBDMA_AHBSEQ_BURST_8             (6 << 24)
  80 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF             BIT(19)
  81 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT          16
  82 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE           0
  83
  84 /* APB address */
  85 #define TEGRA_APBDMA_CHAN_APBPTR                0x018
  86
  87 /* APB sequence register */
  88 #define TEGRA_APBDMA_CHAN_APBSEQ                0x01c
  89 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8         (0 << 28)
  90 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16        (1 << 28)
  91 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32        (2 << 28)
  92 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64        (3 << 28)
  93 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128       (4 << 28)
  94 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP           BIT(27)
  95 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1         (1 << 16)
  96
  97 /*
  98  * If any burst is in flight and DMA paused then this is the time to complete
  99  * on-flight burst and update DMA status register.
 100  */
 101 #define TEGRA_APBDMA_BURST_COMPLETE_TIME        20
 102
 103 /* Channel base address offset from APBDMA base address */
 104 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET    0x1000
 105
 106 /* DMA channel register space size */
 107 #define TEGRA_APBDMA_CHANNEL_REGISTER_SIZE      0x20
 108
 109 struct tegra_dma;
 110
 111 /*
 112  * tegra_dma_chip_data Tegra chip specific DMA data
 113  * @nr_channels: Number of channels available in the controller.
 114  * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
 115  */
 116 struct tegra_dma_chip_data {
 117         int nr_channels;
 118         int max_dma_count;
 119 };
 120
 121 /* DMA channel registers */
 122 struct tegra_dma_channel_regs {
 123         unsigned long   csr;
 124         unsigned long   ahb_ptr;
 125         unsigned long   apb_ptr;
 126         unsigned long   ahb_seq;
 127         unsigned long   apb_seq;
 128 };
 129
 130 /*
 131  * tegra_dma_sg_req: Dma request details to configure hardware. This
 132  * contains the details for one transfer to configure DMA hw.
 133  * The client's request for data transfer can be broken into multiple
 134  * sub-transfer as per requester details and hw support.
 135  * This sub transfer get added in the list of transfer and point to Tegra
 136  * DMA descriptor which manages the transfer details.
 137  */
 138 struct tegra_dma_sg_req {
 139         struct tegra_dma_channel_regs   ch_regs;
 140         int                             req_len;
 141         bool                            configured;
 142         bool                            last_sg;
 143         bool                            half_done;
 144         struct list_head                node;
 145         struct tegra_dma_desc           *dma_desc;
 146 };
 147
 148 /*
 149  * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
 150  * This descriptor keep track of transfer status, callbacks and request
 151  * counts etc.
 152  */
 153 struct tegra_dma_desc {
 154         struct dma_async_tx_descriptor  txd;
 155         int                             bytes_requested;
 156         int                             bytes_transferred;
 157         enum dma_status                 dma_status;
 158         struct list_head                node;
 159         struct list_head                tx_list;
 160         struct list_head                cb_node;
 161         int                             cb_count;
 162 };
 163
 164 struct tegra_dma_channel;
 165
 166 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
 167                                 bool to_terminate);
 168
 169 /* tegra_dma_channel: Channel specific information */
 170 struct tegra_dma_channel {
 171         struct dma_chan         dma_chan;
 172         char                    name[30];
 173         bool                    config_init;
 174         int                     id;
 175         int                     irq;
 176         unsigned long           chan_base_offset;
 177         spinlock_t              lock;
 178         bool                    busy;
 179         struct tegra_dma        *tdma;
 180         bool                    cyclic;
 181
 182         /* Different lists for managing the requests */
 183         struct list_head        free_sg_req;
 184         struct list_head        pending_sg_req;
 185         struct list_head        free_dma_desc;
 186         struct list_head        cb_desc;
 187
 188         /* ISR handler and tasklet for bottom half of isr handling */
 189         dma_isr_handler         isr_handler;
 190         struct tasklet_struct   tasklet;
 191         dma_async_tx_callback   callback;
 192         void                    *callback_param;
 193
 194         /* Channel-slave specific configuration */
 195         struct dma_slave_config dma_sconfig;
 196 };
 197
 198 /* tegra_dma: Tegra DMA specific information */
 199 struct tegra_dma {
 200         struct dma_device               dma_dev;
 201         struct device                   *dev;
 202         struct clk                      *dma_clk;
 203         spinlock_t                      global_lock;
 204         void __iomem                    *base_addr;
 205         const struct tegra_dma_chip_data *chip_data;
 206
 207         /* Some register need to be cache before suspend */
 208         u32                             reg_gen;
 209
 210         /* Last member of the structure */
 211         struct tegra_dma_channel channels[0];
 212 };
 213
 214 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
 215 {
 216         writel(val, tdma->base_addr + reg);
 217 }
 218
 219 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
 220 {
 221         return readl(tdma->base_addr + reg);
 222 }
 223
 224 static inline void tdc_write(struct tegra_dma_channel *tdc,
 225                 u32 reg, u32 val)
 226 {
 227         writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 228 }
 229
 230 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
 231 {
 232         return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
 233 }
 234
 235 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
 236 {
 237         return container_of(dc, struct tegra_dma_channel, dma_chan);
 238 }
 239
 240 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
 241                 struct dma_async_tx_descriptor *td)
 242 {
 243         return container_of(td, struct tegra_dma_desc, txd);
 244 }
 245
 246 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
 247 {
 248         return &tdc->dma_chan.dev->device;
 249 }
 250
 251 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
 252 static int tegra_dma_runtime_suspend(struct device *dev);
 253 static int tegra_dma_runtime_resume(struct device *dev);
 254
 255 /* Get DMA desc from free list, if not there then allocate it.  */
 256 static struct tegra_dma_desc *tegra_dma_desc_get(
 257                 struct tegra_dma_channel *tdc)
 258 {
 259         struct tegra_dma_desc *dma_desc;
 260         unsigned long flags;
 261
 262         spin_lock_irqsave(&tdc->lock, flags);
 263
 264         /* Do not allocate if desc are waiting for ack */
 265         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 266                 if (async_tx_test_ack(&dma_desc->txd)) {
 267                         list_del(&dma_desc->node);
 268                         spin_unlock_irqrestore(&tdc->lock, flags);
 269                         dma_desc->txd.flags = 0;
 270                         return dma_desc;
 271                 }
 272         }
 273
 274         spin_unlock_irqrestore(&tdc->lock, flags);
 275
 276         /* Allocate DMA desc */
 277         dma_desc = kzalloc(sizeof(*dma_desc), GFP_ATOMIC);
 278         if (!dma_desc) {
 279                 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
 280                 return NULL;
 281         }
 282
 283         dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
 284         dma_desc->txd.tx_submit = tegra_dma_tx_submit;
 285         dma_desc->txd.flags = 0;
 286         return dma_desc;
 287 }
 288
 289 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
 290                 struct tegra_dma_desc *dma_desc)
 291 {
 292         unsigned long flags;
 293
 294         spin_lock_irqsave(&tdc->lock, flags);
 295         if (!list_empty(&dma_desc->tx_list))
 296                 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
 297         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 298         spin_unlock_irqrestore(&tdc->lock, flags);
 299 }
 300
 301 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
 302                 struct tegra_dma_channel *tdc)
 303 {
 304         struct tegra_dma_sg_req *sg_req = NULL;
 305         unsigned long flags;
 306
 307         spin_lock_irqsave(&tdc->lock, flags);
 308         if (!list_empty(&tdc->free_sg_req)) {
 309                 sg_req = list_first_entry(&tdc->free_sg_req,
 310                                         typeof(*sg_req), node);
 311                 list_del(&sg_req->node);
 312                 spin_unlock_irqrestore(&tdc->lock, flags);
 313                 return sg_req;
 314         }
 315         spin_unlock_irqrestore(&tdc->lock, flags);
 316
 317         sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_ATOMIC);
 318         if (!sg_req)
 319                 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
 320         return sg_req;
 321 }
 322
 323 static int tegra_dma_slave_config(struct dma_chan *dc,
 324                 struct dma_slave_config *sconfig)
 325 {
 326         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 327
 328         if (!list_empty(&tdc->pending_sg_req)) {
 329                 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
 330                 return -EBUSY;
 331         }
 332
 333         memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
 334         tdc->config_init = true;
 335         return 0;
 336 }
 337
 338 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
 339         bool wait_for_burst_complete)
 340 {
 341         struct tegra_dma *tdma = tdc->tdma;
 342
 343         spin_lock(&tdma->global_lock);
 344         tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
 345         if (wait_for_burst_complete)
 346                 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 347 }
 348
 349 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
 350 {
 351         struct tegra_dma *tdma = tdc->tdma;
 352
 353         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
 354         spin_unlock(&tdma->global_lock);
 355 }
 356
 357 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
 358 {
 359         u32 csr;
 360         u32 status;
 361
 362         /* Disable interrupts */
 363         csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
 364         csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
 365         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 366
 367         /* Disable DMA */
 368         csr &= ~TEGRA_APBDMA_CSR_ENB;
 369         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
 370
 371         /* Clear interrupt status if it is there */
 372         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 373         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 374                 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
 375                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 376         }
 377         tdc->busy = false;
 378 }
 379
 380 static void tegra_dma_start(struct tegra_dma_channel *tdc,
 381                 struct tegra_dma_sg_req *sg_req)
 382 {
 383         struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
 384
 385         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
 386         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
 387         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
 388         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
 389         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
 390
 391         /* Start DMA */
 392         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 393                                 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
 394 }
 395
 396 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
 397                 struct tegra_dma_sg_req *nsg_req)
 398 {
 399         unsigned long status;
 400
 401         /*
 402          * The DMA controller reloads the new configuration for next transfer
 403          * after last burst of current transfer completes.
 404          * If there is no IEC status then this makes sure that last burst
 405          * has not be completed. There may be case that last burst is on
 406          * flight and so it can complete but because DMA is paused, it
 407          * will not generates interrupt as well as not reload the new
 408          * configuration.
 409          * If there is already IEC status then interrupt handler need to
 410          * load new configuration.
 411          */
 412         tegra_dma_global_pause(tdc, false);
 413         status  = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 414
 415         /*
 416          * If interrupt is pending then do nothing as the ISR will handle
 417          * the programing for new request.
 418          */
 419         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 420                 dev_err(tdc2dev(tdc),
 421                         "Skipping new configuration as interrupt is pending\n");
 422                 tegra_dma_global_resume(tdc);
 423                 return;
 424         }
 425
 426         /* Safe to program new configuration */
 427         tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
 428         tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
 429         tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
 430                                 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
 431         nsg_req->configured = true;
 432
 433         tegra_dma_global_resume(tdc);
 434 }
 435
 436 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
 437 {
 438         struct tegra_dma_sg_req *sg_req;
 439
 440         if (list_empty(&tdc->pending_sg_req))
 441                 return;
 442
 443         sg_req = list_first_entry(&tdc->pending_sg_req,
 444                                         typeof(*sg_req), node);
 445         tegra_dma_start(tdc, sg_req);
 446         sg_req->configured = true;
 447         tdc->busy = true;
 448 }
 449
 450 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
 451 {
 452         struct tegra_dma_sg_req *hsgreq;
 453         struct tegra_dma_sg_req *hnsgreq;
 454
 455         if (list_empty(&tdc->pending_sg_req))
 456                 return;
 457
 458         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 459         if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
 460                 hnsgreq = list_first_entry(&hsgreq->node,
 461                                         typeof(*hnsgreq), node);
 462                 tegra_dma_configure_for_next(tdc, hnsgreq);
 463         }
 464 }
 465
 466 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
 467         struct tegra_dma_sg_req *sg_req, unsigned long status)
 468 {
 469         return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
 470 }
 471
 472 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
 473 {
 474         struct tegra_dma_sg_req *sgreq;
 475         struct tegra_dma_desc *dma_desc;
 476
 477         while (!list_empty(&tdc->pending_sg_req)) {
 478                 sgreq = list_first_entry(&tdc->pending_sg_req,
 479                                                 typeof(*sgreq), node);
 480                 list_move_tail(&sgreq->node, &tdc->free_sg_req);
 481                 if (sgreq->last_sg) {
 482                         dma_desc = sgreq->dma_desc;
 483                         dma_desc->dma_status = DMA_ERROR;
 484                         list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 485
 486                         /* Add in cb list if it is not there. */
 487                         if (!dma_desc->cb_count)
 488                                 list_add_tail(&dma_desc->cb_node,
 489                                                         &tdc->cb_desc);
 490                         dma_desc->cb_count++;
 491                 }
 492         }
 493         tdc->isr_handler = NULL;
 494 }
 495
 496 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
 497                 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
 498 {
 499         struct tegra_dma_sg_req *hsgreq = NULL;
 500
 501         if (list_empty(&tdc->pending_sg_req)) {
 502                 dev_err(tdc2dev(tdc), "Dma is running without req\n");
 503                 tegra_dma_stop(tdc);
 504                 return false;
 505         }
 506
 507         /*
 508          * Check that head req on list should be in flight.
 509          * If it is not in flight then abort transfer as
 510          * looping of transfer can not continue.
 511          */
 512         hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
 513         if (!hsgreq->configured) {
 514                 tegra_dma_stop(tdc);
 515                 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
 516                 tegra_dma_abort_all(tdc);
 517                 return false;
 518         }
 519
 520         /* Configure next request */
 521         if (!to_terminate)
 522                 tdc_configure_next_head_desc(tdc);
 523         return true;
 524 }
 525
 526 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
 527         bool to_terminate)
 528 {
 529         struct tegra_dma_sg_req *sgreq;
 530         struct tegra_dma_desc *dma_desc;
 531
 532         tdc->busy = false;
 533         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 534         dma_desc = sgreq->dma_desc;
 535         dma_desc->bytes_transferred += sgreq->req_len;
 536
 537         list_del(&sgreq->node);
 538         if (sgreq->last_sg) {
 539                 dma_desc->dma_status = DMA_SUCCESS;
 540                 dma_cookie_complete(&dma_desc->txd);
 541                 if (!dma_desc->cb_count)
 542                         list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 543                 dma_desc->cb_count++;
 544                 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
 545         }
 546         list_add_tail(&sgreq->node, &tdc->free_sg_req);
 547
 548         /* Do not start DMA if it is going to be terminate */
 549         if (to_terminate || list_empty(&tdc->pending_sg_req))
 550                 return;
 551
 552         tdc_start_head_req(tdc);
 553         return;
 554 }
 555
 556 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
 557                 bool to_terminate)
 558 {
 559         struct tegra_dma_sg_req *sgreq;
 560         struct tegra_dma_desc *dma_desc;
 561         bool st;
 562
 563         sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
 564         dma_desc = sgreq->dma_desc;
 565         dma_desc->bytes_transferred += sgreq->req_len;
 566
 567         /* Callback need to be call */
 568         if (!dma_desc->cb_count)
 569                 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
 570         dma_desc->cb_count++;
 571
 572         /* If not last req then put at end of pending list */
 573         if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
 574                 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
 575                 sgreq->configured = false;
 576                 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
 577                 if (!st)
 578                         dma_desc->dma_status = DMA_ERROR;
 579         }
 580         return;
 581 }
 582
 583 static void tegra_dma_tasklet(unsigned long data)
 584 {
 585         struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
 586         dma_async_tx_callback callback = NULL;
 587         void *callback_param = NULL;
 588         struct tegra_dma_desc *dma_desc;
 589         unsigned long flags;
 590         int cb_count;
 591
 592         spin_lock_irqsave(&tdc->lock, flags);
 593         while (!list_empty(&tdc->cb_desc)) {
 594                 dma_desc  = list_first_entry(&tdc->cb_desc,
 595                                         typeof(*dma_desc), cb_node);
 596                 list_del(&dma_desc->cb_node);
 597                 callback = dma_desc->txd.callback;
 598                 callback_param = dma_desc->txd.callback_param;
 599                 cb_count = dma_desc->cb_count;
 600                 dma_desc->cb_count = 0;
 601                 spin_unlock_irqrestore(&tdc->lock, flags);
 602                 while (cb_count-- && callback)
 603                         callback(callback_param);
 604                 spin_lock_irqsave(&tdc->lock, flags);
 605         }
 606         spin_unlock_irqrestore(&tdc->lock, flags);
 607 }
 608
 609 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
 610 {
 611         struct tegra_dma_channel *tdc = dev_id;
 612         unsigned long status;
 613         unsigned long flags;
 614
 615         spin_lock_irqsave(&tdc->lock, flags);
 616
 617         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 618         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 619                 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
 620                 tdc->isr_handler(tdc, false);
 621                 tasklet_schedule(&tdc->tasklet);
 622                 spin_unlock_irqrestore(&tdc->lock, flags);
 623                 return IRQ_HANDLED;
 624         }
 625
 626         spin_unlock_irqrestore(&tdc->lock, flags);
 627         dev_info(tdc2dev(tdc),
 628                 "Interrupt already served status 0x%08lx\n", status);
 629         return IRQ_NONE;
 630 }
 631
 632 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
 633 {
 634         struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
 635         struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
 636         unsigned long flags;
 637         dma_cookie_t cookie;
 638
 639         spin_lock_irqsave(&tdc->lock, flags);
 640         dma_desc->dma_status = DMA_IN_PROGRESS;
 641         cookie = dma_cookie_assign(&dma_desc->txd);
 642         list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
 643         spin_unlock_irqrestore(&tdc->lock, flags);
 644         return cookie;
 645 }
 646
 647 static void tegra_dma_issue_pending(struct dma_chan *dc)
 648 {
 649         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 650         unsigned long flags;
 651
 652         spin_lock_irqsave(&tdc->lock, flags);
 653         if (list_empty(&tdc->pending_sg_req)) {
 654                 dev_err(tdc2dev(tdc), "No DMA request\n");
 655                 goto end;
 656         }
 657         if (!tdc->busy) {
 658                 tdc_start_head_req(tdc);
 659
 660                 /* Continuous single mode: Configure next req */
 661                 if (tdc->cyclic) {
 662                         /*
 663                          * Wait for 1 burst time for configure DMA for
 664                          * next transfer.
 665                          */
 666                         udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
 667                         tdc_configure_next_head_desc(tdc);
 668                 }
 669         }
 670 end:
 671         spin_unlock_irqrestore(&tdc->lock, flags);
 672         return;
 673 }
 674
 675 static void tegra_dma_terminate_all(struct dma_chan *dc)
 676 {
 677         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 678         struct tegra_dma_sg_req *sgreq;
 679         struct tegra_dma_desc *dma_desc;
 680         unsigned long flags;
 681         unsigned long status;
 682         bool was_busy;
 683
 684         spin_lock_irqsave(&tdc->lock, flags);
 685         if (list_empty(&tdc->pending_sg_req)) {
 686                 spin_unlock_irqrestore(&tdc->lock, flags);
 687                 return;
 688         }
 689
 690         if (!tdc->busy)
 691                 goto skip_dma_stop;
 692
 693         /* Pause DMA before checking the queue status */
 694         tegra_dma_global_pause(tdc, true);
 695
 696         status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 697         if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
 698                 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
 699                 tdc->isr_handler(tdc, true);
 700                 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
 701         }
 702
 703         was_busy = tdc->busy;
 704         tegra_dma_stop(tdc);
 705
 706         if (!list_empty(&tdc->pending_sg_req) && was_busy) {
 707                 sgreq = list_first_entry(&tdc->pending_sg_req,
 708                                         typeof(*sgreq), node);
 709                 sgreq->dma_desc->bytes_transferred +=
 710                                 get_current_xferred_count(tdc, sgreq, status);
 711         }
 712         tegra_dma_global_resume(tdc);
 713
 714 skip_dma_stop:
 715         tegra_dma_abort_all(tdc);
 716
 717         while (!list_empty(&tdc->cb_desc)) {
 718                 dma_desc  = list_first_entry(&tdc->cb_desc,
 719                                         typeof(*dma_desc), cb_node);
 720                 list_del(&dma_desc->cb_node);
 721                 dma_desc->cb_count = 0;
 722         }
 723         spin_unlock_irqrestore(&tdc->lock, flags);
 724 }
 725
 726 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
 727         dma_cookie_t cookie, struct dma_tx_state *txstate)
 728 {
 729         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 730         struct tegra_dma_desc *dma_desc;
 731         struct tegra_dma_sg_req *sg_req;
 732         enum dma_status ret;
 733         unsigned long flags;
 734         unsigned int residual;
 735
 736         spin_lock_irqsave(&tdc->lock, flags);
 737
 738         ret = dma_cookie_status(dc, cookie, txstate);
 739         if (ret == DMA_SUCCESS) {
 740                 dma_set_residue(txstate, 0);
 741                 spin_unlock_irqrestore(&tdc->lock, flags);
 742                 return ret;
 743         }
 744
 745         /* Check on wait_ack desc status */
 746         list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
 747                 if (dma_desc->txd.cookie == cookie) {
 748                         residual =  dma_desc->bytes_requested -
 749                                         (dma_desc->bytes_transferred %
 750                                                 dma_desc->bytes_requested);
 751                         dma_set_residue(txstate, residual);
 752                         ret = dma_desc->dma_status;
 753                         spin_unlock_irqrestore(&tdc->lock, flags);
 754                         return ret;
 755                 }
 756         }
 757
 758         /* Check in pending list */
 759         list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
 760                 dma_desc = sg_req->dma_desc;
 761                 if (dma_desc->txd.cookie == cookie) {
 762                         residual =  dma_desc->bytes_requested -
 763                                         (dma_desc->bytes_transferred %
 764                                                 dma_desc->bytes_requested);
 765                         dma_set_residue(txstate, residual);
 766                         ret = dma_desc->dma_status;
 767                         spin_unlock_irqrestore(&tdc->lock, flags);
 768                         return ret;
 769                 }
 770         }
 771
 772         dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
 773         spin_unlock_irqrestore(&tdc->lock, flags);
 774         return ret;
 775 }
 776
 777 static int tegra_dma_device_control(struct dma_chan *dc, enum dma_ctrl_cmd cmd,
 778                         unsigned long arg)
 779 {
 780         switch (cmd) {
 781         case DMA_SLAVE_CONFIG:
 782                 return tegra_dma_slave_config(dc,
 783                                 (struct dma_slave_config *)arg);
 784
 785         case DMA_TERMINATE_ALL:
 786                 tegra_dma_terminate_all(dc);
 787                 return 0;
 788
 789         default:
 790                 break;
 791         }
 792
 793         return -ENXIO;
 794 }
 795
 796 static inline int get_bus_width(struct tegra_dma_channel *tdc,
 797                 enum dma_slave_buswidth slave_bw)
 798 {
 799         switch (slave_bw) {
 800         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 801                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
 802         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 803                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
 804         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 805                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 806         case DMA_SLAVE_BUSWIDTH_8_BYTES:
 807                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
 808         default:
 809                 dev_warn(tdc2dev(tdc),
 810                         "slave bw is not supported, using 32bits\n");
 811                 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
 812         }
 813 }
 814
 815 static inline int get_burst_size(struct tegra_dma_channel *tdc,
 816         u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
 817 {
 818         int burst_byte;
 819         int burst_ahb_width;
 820
 821         /*
 822          * burst_size from client is in terms of the bus_width.
 823          * convert them into AHB memory width which is 4 byte.
 824          */
 825         burst_byte = burst_size * slave_bw;
 826         burst_ahb_width = burst_byte / 4;
 827
 828         /* If burst size is 0 then calculate the burst size based on length */
 829         if (!burst_ahb_width) {
 830                 if (len & 0xF)
 831                         return TEGRA_APBDMA_AHBSEQ_BURST_1;
 832                 else if ((len >> 4) & 0x1)
 833                         return TEGRA_APBDMA_AHBSEQ_BURST_4;
 834                 else
 835                         return TEGRA_APBDMA_AHBSEQ_BURST_8;
 836         }
 837         if (burst_ahb_width < 4)
 838                 return TEGRA_APBDMA_AHBSEQ_BURST_1;
 839         else if (burst_ahb_width < 8)
 840                 return TEGRA_APBDMA_AHBSEQ_BURST_4;
 841         else
 842                 return TEGRA_APBDMA_AHBSEQ_BURST_8;
 843 }
 844
 845 static int get_transfer_param(struct tegra_dma_channel *tdc,
 846         enum dma_transfer_direction direction, unsigned long *apb_addr,
 847         unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
 848         enum dma_slave_buswidth *slave_bw)
 849 {
 850
 851         switch (direction) {
 852         case DMA_MEM_TO_DEV:
 853                 *apb_addr = tdc->dma_sconfig.dst_addr;
 854                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
 855                 *burst_size = tdc->dma_sconfig.dst_maxburst;
 856                 *slave_bw = tdc->dma_sconfig.dst_addr_width;
 857                 *csr = TEGRA_APBDMA_CSR_DIR;
 858                 return 0;
 859
 860         case DMA_DEV_TO_MEM:
 861                 *apb_addr = tdc->dma_sconfig.src_addr;
 862                 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
 863                 *burst_size = tdc->dma_sconfig.src_maxburst;
 864                 *slave_bw = tdc->dma_sconfig.src_addr_width;
 865                 *csr = 0;
 866                 return 0;
 867
 868         default:
 869                 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
 870                 return -EINVAL;
 871         }
 872         return -EINVAL;
 873 }
 874
 875 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
 876         struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
 877         enum dma_transfer_direction direction, unsigned long flags,
 878         void *context)
 879 {
 880         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 881         struct tegra_dma_desc *dma_desc;
 882         unsigned int        i;
 883         struct scatterlist      *sg;
 884         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
 885         struct list_head req_list;
 886         struct tegra_dma_sg_req  *sg_req = NULL;
 887         u32 burst_size;
 888         enum dma_slave_buswidth slave_bw;
 889         int ret;
 890
 891         if (!tdc->config_init) {
 892                 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
 893                 return NULL;
 894         }
 895         if (sg_len < 1) {
 896                 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
 897                 return NULL;
 898         }
 899
 900         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
 901                                 &burst_size, &slave_bw);
 902         if (ret < 0)
 903                 return NULL;
 904
 905         INIT_LIST_HEAD(&req_list);
 906
 907         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
 908         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
 909                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
 910         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
 911
 912         csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
 913         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
 914         if (flags & DMA_PREP_INTERRUPT)
 915                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
 916
 917         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
 918
 919         dma_desc = tegra_dma_desc_get(tdc);
 920         if (!dma_desc) {
 921                 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
 922                 return NULL;
 923         }
 924         INIT_LIST_HEAD(&dma_desc->tx_list);
 925         INIT_LIST_HEAD(&dma_desc->cb_node);
 926         dma_desc->cb_count = 0;
 927         dma_desc->bytes_requested = 0;
 928         dma_desc->bytes_transferred = 0;
 929         dma_desc->dma_status = DMA_IN_PROGRESS;
 930
 931         /* Make transfer requests */
 932         for_each_sg(sgl, sg, sg_len, i) {
 933                 u32 len, mem;
 934
 935                 mem = sg_dma_address(sg);
 936                 len = sg_dma_len(sg);
 937
 938                 if ((len & 3) || (mem & 3) ||
 939                                 (len > tdc->tdma->chip_data->max_dma_count)) {
 940                         dev_err(tdc2dev(tdc),
 941                                 "Dma length/memory address is not supported\n");
 942                         tegra_dma_desc_put(tdc, dma_desc);
 943                         return NULL;
 944                 }
 945
 946                 sg_req = tegra_dma_sg_req_get(tdc);
 947                 if (!sg_req) {
 948                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
 949                         tegra_dma_desc_put(tdc, dma_desc);
 950                         return NULL;
 951                 }
 952
 953                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
 954                 dma_desc->bytes_requested += len;
 955
 956                 sg_req->ch_regs.apb_ptr = apb_ptr;
 957                 sg_req->ch_regs.ahb_ptr = mem;
 958                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
 959                 sg_req->ch_regs.apb_seq = apb_seq;
 960                 sg_req->ch_regs.ahb_seq = ahb_seq;
 961                 sg_req->configured = false;
 962                 sg_req->last_sg = false;
 963                 sg_req->dma_desc = dma_desc;
 964                 sg_req->req_len = len;
 965
 966                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
 967         }
 968         sg_req->last_sg = true;
 969         if (flags & DMA_CTRL_ACK)
 970                 dma_desc->txd.flags = DMA_CTRL_ACK;
 971
 972         /*
 973          * Make sure that mode should not be conflicting with currently
 974          * configured mode.
 975          */
 976         if (!tdc->isr_handler) {
 977                 tdc->isr_handler = handle_once_dma_done;
 978                 tdc->cyclic = false;
 979         } else {
 980                 if (tdc->cyclic) {
 981                         dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
 982                         tegra_dma_desc_put(tdc, dma_desc);
 983                         return NULL;
 984                 }
 985         }
 986
 987         return &dma_desc->txd;
 988 }
 989
 990 struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
 991         struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
 992         size_t period_len, enum dma_transfer_direction direction,
 993         unsigned long flags, void *context)
 994 {
 995         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
 996         struct tegra_dma_desc *dma_desc = NULL;
 997         struct tegra_dma_sg_req  *sg_req = NULL;
 998         unsigned long csr, ahb_seq, apb_ptr, apb_seq;
 999         int len;
1000         size_t remain_len;
1001         dma_addr_t mem = buf_addr;
1002         u32 burst_size;
1003         enum dma_slave_buswidth slave_bw;
1004         int ret;
1005
1006         if (!buf_len || !period_len) {
1007                 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1008                 return NULL;
1009         }
1010
1011         if (!tdc->config_init) {
1012                 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1013                 return NULL;
1014         }
1015
1016         /*
1017          * We allow to take more number of requests till DMA is
1018          * not started. The driver will loop over all requests.
1019          * Once DMA is started then new requests can be queued only after
1020          * terminating the DMA.
1021          */
1022         if (tdc->busy) {
1023                 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1024                 return NULL;
1025         }
1026
1027         /*
1028          * We only support cycle transfer when buf_len is multiple of
1029          * period_len.
1030          */
1031         if (buf_len % period_len) {
1032                 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1033                 return NULL;
1034         }
1035
1036         len = period_len;
1037         if ((len & 3) || (buf_addr & 3) ||
1038                         (len > tdc->tdma->chip_data->max_dma_count)) {
1039                 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1040                 return NULL;
1041         }
1042
1043         ret = get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1044                                 &burst_size, &slave_bw);
1045         if (ret < 0)
1046                 return NULL;
1047
1048
1049         ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1050         ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1051                                         TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1052         ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1053
1054         csr |= TEGRA_APBDMA_CSR_FLOW;
1055         if (flags & DMA_PREP_INTERRUPT)
1056                 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1057         csr |= tdc->dma_sconfig.slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1058
1059         apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1060
1061         dma_desc = tegra_dma_desc_get(tdc);
1062         if (!dma_desc) {
1063                 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1064                 return NULL;
1065         }
1066
1067         INIT_LIST_HEAD(&dma_desc->tx_list);
1068         INIT_LIST_HEAD(&dma_desc->cb_node);
1069         dma_desc->cb_count = 0;
1070
1071         dma_desc->bytes_transferred = 0;
1072         dma_desc->bytes_requested = buf_len;
1073         remain_len = buf_len;
1074
1075         /* Split transfer equal to period size */
1076         while (remain_len) {
1077                 sg_req = tegra_dma_sg_req_get(tdc);
1078                 if (!sg_req) {
1079                         dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1080                         tegra_dma_desc_put(tdc, dma_desc);
1081                         return NULL;
1082                 }
1083
1084                 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1085                 sg_req->ch_regs.apb_ptr = apb_ptr;
1086                 sg_req->ch_regs.ahb_ptr = mem;
1087                 sg_req->ch_regs.csr = csr | ((len - 4) & 0xFFFC);
1088                 sg_req->ch_regs.apb_seq = apb_seq;
1089                 sg_req->ch_regs.ahb_seq = ahb_seq;
1090                 sg_req->configured = false;
1091                 sg_req->half_done = false;
1092                 sg_req->last_sg = false;
1093                 sg_req->dma_desc = dma_desc;
1094                 sg_req->req_len = len;
1095
1096                 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1097                 remain_len -= len;
1098                 mem += len;
1099         }
1100         sg_req->last_sg = true;
1101         if (flags & DMA_CTRL_ACK)
1102                 dma_desc->txd.flags = DMA_CTRL_ACK;
1103
1104         /*
1105          * Make sure that mode should not be conflicting with currently
1106          * configured mode.
1107          */
1108         if (!tdc->isr_handler) {
1109                 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1110                 tdc->cyclic = true;
1111         } else {
1112                 if (!tdc->cyclic) {
1113                         dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1114                         tegra_dma_desc_put(tdc, dma_desc);
1115                         return NULL;
1116                 }
1117         }
1118
1119         return &dma_desc->txd;
1120 }
1121
1122 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1123 {
1124         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1125         struct tegra_dma *tdma = tdc->tdma;
1126         int ret;
1127
1128         dma_cookie_init(&tdc->dma_chan);
1129         tdc->config_init = false;
1130         ret = clk_prepare_enable(tdma->dma_clk);
1131         if (ret < 0)
1132                 dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
1133         return ret;
1134 }
1135
1136 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1137 {
1138         struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1139         struct tegra_dma *tdma = tdc->tdma;
1140
1141         struct tegra_dma_desc *dma_desc;
1142         struct tegra_dma_sg_req *sg_req;
1143         struct list_head dma_desc_list;
1144         struct list_head sg_req_list;
1145         unsigned long flags;
1146
1147         INIT_LIST_HEAD(&dma_desc_list);
1148         INIT_LIST_HEAD(&sg_req_list);
1149
1150         dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1151
1152         if (tdc->busy)
1153                 tegra_dma_terminate_all(dc);
1154
1155         spin_lock_irqsave(&tdc->lock, flags);
1156         list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1157         list_splice_init(&tdc->free_sg_req, &sg_req_list);
1158         list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1159         INIT_LIST_HEAD(&tdc->cb_desc);
1160         tdc->config_init = false;
1161         spin_unlock_irqrestore(&tdc->lock, flags);
1162
1163         while (!list_empty(&dma_desc_list)) {
1164                 dma_desc = list_first_entry(&dma_desc_list,
1165                                         typeof(*dma_desc), node);
1166                 list_del(&dma_desc->node);
1167                 kfree(dma_desc);
1168         }
1169
1170         while (!list_empty(&sg_req_list)) {
1171                 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1172                 list_del(&sg_req->node);
1173                 kfree(sg_req);
1174         }
1175         clk_disable_unprepare(tdma->dma_clk);
1176 }
1177
1178 /* Tegra20 specific DMA controller information */
1179 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1180         .nr_channels            = 16,
1181         .max_dma_count          = 1024UL * 64,
1182 };
1183
1184 #if defined(CONFIG_OF)
1185 /* Tegra30 specific DMA controller information */
1186 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1187         .nr_channels            = 32,
1188         .max_dma_count          = 1024UL * 64,
1189 };
1190
1191 static const struct of_device_id tegra_dma_of_match[] = {
1192         {
1193                 .compatible = "nvidia,tegra30-apbdma",
1194                 .data = &tegra30_dma_chip_data,
1195         }, {
1196                 .compatible = "nvidia,tegra20-apbdma",
1197                 .data = &tegra20_dma_chip_data,
1198         }, {
1199         },
1200 };
1201 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1202 #endif
1203
1204 static int tegra_dma_probe(struct platform_device *pdev)
1205 {
1206         struct resource *res;
1207         struct tegra_dma *tdma;
1208         int ret;
1209         int i;
1210         const struct tegra_dma_chip_data *cdata = NULL;
1211
1212         if (pdev->dev.of_node) {
1213                 const struct of_device_id *match;
1214                 match = of_match_device(of_match_ptr(tegra_dma_of_match),
1215                                         &pdev->dev);
1216                 if (!match) {
1217                         dev_err(&pdev->dev, "Error: No device match found\n");
1218                         return -ENODEV;
1219                 }
1220                 cdata = match->data;
1221         } else {
1222                 /* If no device tree then fallback to tegra20 */
1223                 cdata = &tegra20_dma_chip_data;
1224         }
1225
1226         tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1227                         sizeof(struct tegra_dma_channel), GFP_KERNEL);
1228         if (!tdma) {
1229                 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1230                 return -ENOMEM;
1231         }
1232
1233         tdma->dev = &pdev->dev;
1234         tdma->chip_data = cdata;
1235         platform_set_drvdata(pdev, tdma);
1236
1237         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1238         if (!res) {
1239                 dev_err(&pdev->dev, "No mem resource for DMA\n");
1240                 return -EINVAL;
1241         }
1242
1243         tdma->base_addr = devm_request_and_ioremap(&pdev->dev, res);
1244         if (!tdma->base_addr) {
1245                 dev_err(&pdev->dev,
1246                         "Cannot request memregion/iomap dma address\n");
1247                 return -EADDRNOTAVAIL;
1248         }
1249
1250         tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1251         if (IS_ERR(tdma->dma_clk)) {
1252                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1253                 return PTR_ERR(tdma->dma_clk);
1254         }
1255
1256         spin_lock_init(&tdma->global_lock);
1257
1258         pm_runtime_enable(&pdev->dev);
1259         if (!pm_runtime_enabled(&pdev->dev)) {
1260                 ret = tegra_dma_runtime_resume(&pdev->dev);
1261                 if (ret) {
1262                         dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
1263                                 ret);
1264                         goto err_pm_disable;
1265                 }
1266         }
1267
1268         /* Enable clock before accessing registers */
1269         ret = clk_prepare_enable(tdma->dma_clk);
1270         if (ret < 0) {
1271                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1272                 goto err_pm_disable;
1273         }
1274
1275         /* Reset DMA controller */
1276         tegra_periph_reset_assert(tdma->dma_clk);
1277         udelay(2);
1278         tegra_periph_reset_deassert(tdma->dma_clk);
1279
1280         /* Enable global DMA registers */
1281         tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1282         tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1283         tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1284
1285         clk_disable_unprepare(tdma->dma_clk);
1286
1287         INIT_LIST_HEAD(&tdma->dma_dev.channels);
1288         for (i = 0; i < cdata->nr_channels; i++) {
1289                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1290
1291                 tdc->chan_base_offset = TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1292                                         i * TEGRA_APBDMA_CHANNEL_REGISTER_SIZE;
1293
1294                 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1295                 if (!res) {
1296                         ret = -EINVAL;
1297                         dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1298                         goto err_irq;
1299                 }
1300                 tdc->irq = res->start;
1301                 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1302                 ret = devm_request_irq(&pdev->dev, tdc->irq,
1303                                 tegra_dma_isr, 0, tdc->name, tdc);
1304                 if (ret) {
1305                         dev_err(&pdev->dev,
1306                                 "request_irq failed with err %d channel %d\n",
1307                                 i, ret);
1308                         goto err_irq;
1309                 }
1310
1311                 tdc->dma_chan.device = &tdma->dma_dev;
1312                 dma_cookie_init(&tdc->dma_chan);
1313                 list_add_tail(&tdc->dma_chan.device_node,
1314                                 &tdma->dma_dev.channels);
1315                 tdc->tdma = tdma;
1316                 tdc->id = i;
1317
1318                 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1319                                 (unsigned long)tdc);
1320                 spin_lock_init(&tdc->lock);
1321
1322                 INIT_LIST_HEAD(&tdc->pending_sg_req);
1323                 INIT_LIST_HEAD(&tdc->free_sg_req);
1324                 INIT_LIST_HEAD(&tdc->free_dma_desc);
1325                 INIT_LIST_HEAD(&tdc->cb_desc);
1326         }
1327
1328         dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1329         dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1330         dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1331
1332         tdma->dma_dev.dev = &pdev->dev;
1333         tdma->dma_dev.device_alloc_chan_resources =
1334                                         tegra_dma_alloc_chan_resources;
1335         tdma->dma_dev.device_free_chan_resources =
1336                                         tegra_dma_free_chan_resources;
1337         tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1338         tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1339         tdma->dma_dev.device_control = tegra_dma_device_control;
1340         tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1341         tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1342
1343         ret = dma_async_device_register(&tdma->dma_dev);
1344         if (ret < 0) {
1345                 dev_err(&pdev->dev,
1346                         "Tegra20 APB DMA driver registration failed %d\n", ret);
1347                 goto err_irq;
1348         }
1349
1350         dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1351                         cdata->nr_channels);
1352         return 0;
1353
1354 err_irq:
1355         while (--i >= 0) {
1356                 struct tegra_dma_channel *tdc = &tdma->channels[i];
1357                 tasklet_kill(&tdc->tasklet);
1358         }
1359
1360 err_pm_disable:
1361         pm_runtime_disable(&pdev->dev);
1362         if (!pm_runtime_status_suspended(&pdev->dev))
1363                 tegra_dma_runtime_suspend(&pdev->dev);
1364         return ret;
1365 }
1366
1367 static int tegra_dma_remove(struct platform_device *pdev)
1368 {
1369         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1370         int i;
1371         struct tegra_dma_channel *tdc;
1372
1373         dma_async_device_unregister(&tdma->dma_dev);
1374
1375         for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1376                 tdc = &tdma->channels[i];
1377                 tasklet_kill(&tdc->tasklet);
1378         }
1379
1380         pm_runtime_disable(&pdev->dev);
1381         if (!pm_runtime_status_suspended(&pdev->dev))
1382                 tegra_dma_runtime_suspend(&pdev->dev);
1383
1384         return 0;
1385 }
1386
1387 static int tegra_dma_runtime_suspend(struct device *dev)
1388 {
1389         struct platform_device *pdev = to_platform_device(dev);
1390         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1391
1392         clk_disable_unprepare(tdma->dma_clk);
1393         return 0;
1394 }
1395
1396 static int tegra_dma_runtime_resume(struct device *dev)
1397 {
1398         struct platform_device *pdev = to_platform_device(dev);
1399         struct tegra_dma *tdma = platform_get_drvdata(pdev);
1400         int ret;
1401
1402         ret = clk_prepare_enable(tdma->dma_clk);
1403         if (ret < 0) {
1404                 dev_err(dev, "clk_enable failed: %d\n", ret);
1405                 return ret;
1406         }
1407         return 0;
1408 }
1409
1410 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1411 #ifdef CONFIG_PM_RUNTIME
1412         .runtime_suspend = tegra_dma_runtime_suspend,
1413         .runtime_resume = tegra_dma_runtime_resume,
1414 #endif
1415 };
1416
1417 static struct platform_driver tegra_dmac_driver = {
1418         .driver = {
1419                 .name   = "tegra-apbdma",
1420                 .owner = THIS_MODULE,
1421                 .pm     = &tegra_dma_dev_pm_ops,
1422                 .of_match_table = of_match_ptr(tegra_dma_of_match),
1423         },
1424         .probe          = tegra_dma_probe,
1425         .remove         = tegra_dma_remove,
1426 };
1427
1428 module_platform_driver(tegra_dmac_driver);
1429
1430 MODULE_ALIAS("platform:tegra20-apbdma");
1431 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1432 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1433 MODULE_LICENSE("GPL v2");