2 * Renesas R-Car Gen2 DMA Controller Driver
4 * Copyright (C) 2014 Renesas Electronics Inc.
6 * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 * This is free software; you can redistribute it and/or modify
9 * it under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
27 #include "../dmaengine.h"
30 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
31 * @node: entry in the parent's chunks list
32 * @src_addr: device source address
33 * @dst_addr: device destination address
34 * @size: transfer size in bytes
36 struct rcar_dmac_xfer_chunk {
37 struct list_head node;
45 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
46 * @sar: value of the SAR register (source address)
47 * @dar: value of the DAR register (destination address)
48 * @tcr: value of the TCR register (transfer count)
50 struct rcar_dmac_hw_desc {
55 } __attribute__((__packed__));
58 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
59 * @async_tx: base DMA asynchronous transaction descriptor
60 * @direction: direction of the DMA transfer
61 * @xfer_shift: log2 of the transfer size
62 * @chcr: value of the channel configuration register for this transfer
63 * @node: entry in the channel's descriptors lists
64 * @chunks: list of transfer chunks for this transfer
65 * @running: the transfer chunk being currently processed
66 * @nchunks: number of transfer chunks for this transfer
67 * @hwdescs.use: whether the transfer descriptor uses hardware descriptors
68 * @hwdescs.mem: hardware descriptors memory for the transfer
69 * @hwdescs.dma: device address of the hardware descriptors memory
70 * @hwdescs.size: size of the hardware descriptors in bytes
71 * @size: transfer size in bytes
72 * @cyclic: when set indicates that the DMA transfer is cyclic
74 struct rcar_dmac_desc {
75 struct dma_async_tx_descriptor async_tx;
76 enum dma_transfer_direction direction;
77 unsigned int xfer_shift;
80 struct list_head node;
81 struct list_head chunks;
82 struct rcar_dmac_xfer_chunk *running;
87 struct rcar_dmac_hw_desc *mem;
96 #define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx)
99 * struct rcar_dmac_desc_page - One page worth of descriptors
100 * @node: entry in the channel's pages list
101 * @descs: array of DMA descriptors
102 * @chunks: array of transfer chunk descriptors
104 struct rcar_dmac_desc_page {
105 struct list_head node;
108 struct rcar_dmac_desc descs[0];
109 struct rcar_dmac_xfer_chunk chunks[0];
113 #define RCAR_DMAC_DESCS_PER_PAGE \
114 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \
115 sizeof(struct rcar_dmac_desc))
116 #define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \
117 ((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \
118 sizeof(struct rcar_dmac_xfer_chunk))
121 * struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel
122 * @chan: base DMA channel object
123 * @iomem: channel I/O memory base
124 * @index: index of this channel in the controller
125 * @src_xfer_size: size (in bytes) of hardware transfers on the source side
126 * @dst_xfer_size: size (in bytes) of hardware transfers on the destination side
127 * @src_slave_addr: slave source memory address
128 * @dst_slave_addr: slave destination memory address
129 * @mid_rid: hardware MID/RID for the DMA client using this channel
130 * @lock: protects the channel CHCR register and the desc members
131 * @desc.free: list of free descriptors
132 * @desc.pending: list of pending descriptors (submitted with tx_submit)
133 * @desc.active: list of active descriptors (activated with issue_pending)
134 * @desc.done: list of completed descriptors
135 * @desc.wait: list of descriptors waiting for an ack
136 * @desc.running: the descriptor being processed (a member of the active list)
137 * @desc.chunks_free: list of free transfer chunk descriptors
138 * @desc.pages: list of pages used by allocated descriptors
140 struct rcar_dmac_chan {
141 struct dma_chan chan;
145 unsigned int src_xfer_size;
146 unsigned int dst_xfer_size;
147 dma_addr_t src_slave_addr;
148 dma_addr_t dst_slave_addr;
154 struct list_head free;
155 struct list_head pending;
156 struct list_head active;
157 struct list_head done;
158 struct list_head wait;
159 struct rcar_dmac_desc *running;
161 struct list_head chunks_free;
163 struct list_head pages;
167 #define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan)
170 * struct rcar_dmac - R-Car Gen2 DMA Controller
171 * @engine: base DMA engine object
172 * @dev: the hardware device
173 * @iomem: remapped I/O memory base
174 * @n_channels: number of available channels
175 * @channels: array of DMAC channels
176 * @modules: bitmask of client modules in use
179 struct dma_device engine;
183 unsigned int n_channels;
184 struct rcar_dmac_chan *channels;
186 unsigned long modules[256 / BITS_PER_LONG];
189 #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
191 /* -----------------------------------------------------------------------------
195 #define RCAR_DMAC_CHAN_OFFSET(i) (0x8000 + 0x80 * (i))
197 #define RCAR_DMAISTA 0x0020
198 #define RCAR_DMASEC 0x0030
199 #define RCAR_DMAOR 0x0060
200 #define RCAR_DMAOR_PRI_FIXED (0 << 8)
201 #define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8)
202 #define RCAR_DMAOR_AE (1 << 2)
203 #define RCAR_DMAOR_DME (1 << 0)
204 #define RCAR_DMACHCLR 0x0080
205 #define RCAR_DMADPSEC 0x00a0
207 #define RCAR_DMASAR 0x0000
208 #define RCAR_DMADAR 0x0004
209 #define RCAR_DMATCR 0x0008
210 #define RCAR_DMATCR_MASK 0x00ffffff
211 #define RCAR_DMATSR 0x0028
212 #define RCAR_DMACHCR 0x000c
213 #define RCAR_DMACHCR_CAE (1 << 31)
214 #define RCAR_DMACHCR_CAIE (1 << 30)
215 #define RCAR_DMACHCR_DPM_DISABLED (0 << 28)
216 #define RCAR_DMACHCR_DPM_ENABLED (1 << 28)
217 #define RCAR_DMACHCR_DPM_REPEAT (2 << 28)
218 #define RCAR_DMACHCR_DPM_INFINITE (3 << 28)
219 #define RCAR_DMACHCR_RPT_SAR (1 << 27)
220 #define RCAR_DMACHCR_RPT_DAR (1 << 26)
221 #define RCAR_DMACHCR_RPT_TCR (1 << 25)
222 #define RCAR_DMACHCR_DPB (1 << 22)
223 #define RCAR_DMACHCR_DSE (1 << 19)
224 #define RCAR_DMACHCR_DSIE (1 << 18)
225 #define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3))
226 #define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3))
227 #define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3))
228 #define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3))
229 #define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3))
230 #define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3))
231 #define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3))
232 #define RCAR_DMACHCR_DM_FIXED (0 << 14)
233 #define RCAR_DMACHCR_DM_INC (1 << 14)
234 #define RCAR_DMACHCR_DM_DEC (2 << 14)
235 #define RCAR_DMACHCR_SM_FIXED (0 << 12)
236 #define RCAR_DMACHCR_SM_INC (1 << 12)
237 #define RCAR_DMACHCR_SM_DEC (2 << 12)
238 #define RCAR_DMACHCR_RS_AUTO (4 << 8)
239 #define RCAR_DMACHCR_RS_DMARS (8 << 8)
240 #define RCAR_DMACHCR_IE (1 << 2)
241 #define RCAR_DMACHCR_TE (1 << 1)
242 #define RCAR_DMACHCR_DE (1 << 0)
243 #define RCAR_DMATCRB 0x0018
244 #define RCAR_DMATSRB 0x0038
245 #define RCAR_DMACHCRB 0x001c
246 #define RCAR_DMACHCRB_DCNT(n) ((n) << 24)
247 #define RCAR_DMACHCRB_DPTR_MASK (0xff << 16)
248 #define RCAR_DMACHCRB_DPTR_SHIFT 16
249 #define RCAR_DMACHCRB_DRST (1 << 15)
250 #define RCAR_DMACHCRB_DTS (1 << 8)
251 #define RCAR_DMACHCRB_SLM_NORMAL (0 << 4)
252 #define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4)
253 #define RCAR_DMACHCRB_PRI(n) ((n) << 0)
254 #define RCAR_DMARS 0x0040
255 #define RCAR_DMABUFCR 0x0048
256 #define RCAR_DMABUFCR_MBU(n) ((n) << 16)
257 #define RCAR_DMABUFCR_ULB(n) ((n) << 0)
258 #define RCAR_DMADPBASE 0x0050
259 #define RCAR_DMADPBASE_MASK 0xfffffff0
260 #define RCAR_DMADPBASE_SEL (1 << 0)
261 #define RCAR_DMADPCR 0x0054
262 #define RCAR_DMADPCR_DIPT(n) ((n) << 24)
263 #define RCAR_DMAFIXSAR 0x0010
264 #define RCAR_DMAFIXDAR 0x0014
265 #define RCAR_DMAFIXDPBASE 0x0060
267 /* Hardcode the MEMCPY transfer size to 4 bytes. */
268 #define RCAR_DMAC_MEMCPY_XFER_SIZE 4
270 /* -----------------------------------------------------------------------------
274 static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data)
276 if (reg == RCAR_DMAOR)
277 writew(data, dmac->iomem + reg);
279 writel(data, dmac->iomem + reg);
282 static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg)
284 if (reg == RCAR_DMAOR)
285 return readw(dmac->iomem + reg);
287 return readl(dmac->iomem + reg);
290 static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg)
292 if (reg == RCAR_DMARS)
293 return readw(chan->iomem + reg);
295 return readl(chan->iomem + reg);
298 static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
300 if (reg == RCAR_DMARS)
301 writew(data, chan->iomem + reg);
303 writel(data, chan->iomem + reg);
306 /* -----------------------------------------------------------------------------
307 * Initialization and configuration
310 static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan)
312 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
314 return (chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE)) == RCAR_DMACHCR_DE;
317 static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
319 struct rcar_dmac_desc *desc = chan->desc.running;
320 u32 chcr = desc->chcr;
322 WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan));
324 if (chan->mid_rid >= 0)
325 rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
327 if (desc->hwdescs.use) {
328 dev_dbg(chan->chan.device->dev,
329 "chan%u: queue desc %p: %u@%pad\n",
330 chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
332 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
333 rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
334 desc->hwdescs.dma >> 32);
336 rcar_dmac_chan_write(chan, RCAR_DMADPBASE,
337 (desc->hwdescs.dma & 0xfffffff0) |
339 rcar_dmac_chan_write(chan, RCAR_DMACHCRB,
340 RCAR_DMACHCRB_DCNT(desc->nchunks - 1) |
344 * Program the descriptor stage interrupt to occur after the end
345 * of the first stage.
347 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1));
349 chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
350 | RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB;
353 * If the descriptor isn't cyclic enable normal descriptor mode
354 * and the transfer completion interrupt.
357 chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
359 * If the descriptor is cyclic and has a callback enable the
360 * descriptor stage interrupt in infinite repeat mode.
362 else if (desc->async_tx.callback)
363 chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
365 * Otherwise just select infinite repeat mode without any
369 chcr |= RCAR_DMACHCR_DPM_INFINITE;
371 struct rcar_dmac_xfer_chunk *chunk = desc->running;
373 dev_dbg(chan->chan.device->dev,
374 "chan%u: queue chunk %p: %u@%pad -> %pad\n",
375 chan->index, chunk, chunk->size, &chunk->src_addr,
378 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
379 rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
380 chunk->src_addr >> 32);
381 rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
382 chunk->dst_addr >> 32);
384 rcar_dmac_chan_write(chan, RCAR_DMASAR,
385 chunk->src_addr & 0xffffffff);
386 rcar_dmac_chan_write(chan, RCAR_DMADAR,
387 chunk->dst_addr & 0xffffffff);
388 rcar_dmac_chan_write(chan, RCAR_DMATCR,
389 chunk->size >> desc->xfer_shift);
391 chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
394 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr | RCAR_DMACHCR_DE);
397 static int rcar_dmac_init(struct rcar_dmac *dmac)
401 /* Clear all channels and enable the DMAC globally. */
402 rcar_dmac_write(dmac, RCAR_DMACHCLR, 0x7fff);
403 rcar_dmac_write(dmac, RCAR_DMAOR,
404 RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
406 dmaor = rcar_dmac_read(dmac, RCAR_DMAOR);
407 if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) {
408 dev_warn(dmac->dev, "DMAOR initialization failed.\n");
415 /* -----------------------------------------------------------------------------
416 * Descriptors submission
419 static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx)
421 struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan);
422 struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx);
426 spin_lock_irqsave(&chan->lock, flags);
428 cookie = dma_cookie_assign(tx);
430 dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n",
431 chan->index, tx->cookie, desc);
433 list_add_tail(&desc->node, &chan->desc.pending);
434 desc->running = list_first_entry(&desc->chunks,
435 struct rcar_dmac_xfer_chunk, node);
437 spin_unlock_irqrestore(&chan->lock, flags);
442 /* -----------------------------------------------------------------------------
443 * Descriptors allocation and free
447 * rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors
448 * @chan: the DMA channel
449 * @gfp: allocation flags
451 static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
453 struct rcar_dmac_desc_page *page;
457 page = (void *)get_zeroed_page(gfp);
461 for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) {
462 struct rcar_dmac_desc *desc = &page->descs[i];
464 dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
465 desc->async_tx.tx_submit = rcar_dmac_tx_submit;
466 INIT_LIST_HEAD(&desc->chunks);
468 list_add_tail(&desc->node, &list);
471 spin_lock_irq(&chan->lock);
472 list_splice_tail(&list, &chan->desc.free);
473 list_add_tail(&page->node, &chan->desc.pages);
474 spin_unlock_irq(&chan->lock);
480 * rcar_dmac_desc_put - Release a DMA transfer descriptor
481 * @chan: the DMA channel
482 * @desc: the descriptor
484 * Put the descriptor and its transfer chunk descriptors back in the channel's
485 * free descriptors lists. The descriptor's chunks list will be reinitialized to
486 * an empty list as a result.
488 * The descriptor must have been removed from the channel's lists before calling
491 * Locking: Must be called in non-atomic context.
493 static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan,
494 struct rcar_dmac_desc *desc)
496 spin_lock_irq(&chan->lock);
497 list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free);
498 list_add_tail(&desc->node, &chan->desc.free);
499 spin_unlock_irq(&chan->lock);
502 static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan)
504 struct rcar_dmac_desc *desc, *_desc;
508 * We have to temporarily move all descriptors from the wait list to a
509 * local list as iterating over the wait list, even with
510 * list_for_each_entry_safe, isn't safe if we release the channel lock
511 * around the rcar_dmac_desc_put() call.
513 spin_lock_irq(&chan->lock);
514 list_splice_init(&chan->desc.wait, &list);
515 spin_unlock_irq(&chan->lock);
517 list_for_each_entry_safe(desc, _desc, &list, node) {
518 if (async_tx_test_ack(&desc->async_tx)) {
519 list_del(&desc->node);
520 rcar_dmac_desc_put(chan, desc);
524 if (list_empty(&list))
527 /* Put the remaining descriptors back in the wait list. */
528 spin_lock_irq(&chan->lock);
529 list_splice(&list, &chan->desc.wait);
530 spin_unlock_irq(&chan->lock);
534 * rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer
535 * @chan: the DMA channel
537 * Locking: This function must be called in a non-atomic context.
539 * Return: A pointer to the allocated descriptor or NULL if no descriptor can
542 static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan)
544 struct rcar_dmac_desc *desc;
547 /* Recycle acked descriptors before attempting allocation. */
548 rcar_dmac_desc_recycle_acked(chan);
550 spin_lock_irq(&chan->lock);
552 while (list_empty(&chan->desc.free)) {
554 * No free descriptors, allocate a page worth of them and try
555 * again, as someone else could race us to get the newly
556 * allocated descriptors. If the allocation fails return an
559 spin_unlock_irq(&chan->lock);
560 ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT);
563 spin_lock_irq(&chan->lock);
566 desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc, node);
567 list_del(&desc->node);
569 spin_unlock_irq(&chan->lock);
575 * rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks
576 * @chan: the DMA channel
577 * @gfp: allocation flags
579 static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
581 struct rcar_dmac_desc_page *page;
585 page = (void *)get_zeroed_page(gfp);
589 for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) {
590 struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i];
592 list_add_tail(&chunk->node, &list);
595 spin_lock_irq(&chan->lock);
596 list_splice_tail(&list, &chan->desc.chunks_free);
597 list_add_tail(&page->node, &chan->desc.pages);
598 spin_unlock_irq(&chan->lock);
604 * rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer
605 * @chan: the DMA channel
607 * Locking: This function must be called in a non-atomic context.
609 * Return: A pointer to the allocated transfer chunk descriptor or NULL if no
610 * descriptor can be allocated.
612 static struct rcar_dmac_xfer_chunk *
613 rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan)
615 struct rcar_dmac_xfer_chunk *chunk;
618 spin_lock_irq(&chan->lock);
620 while (list_empty(&chan->desc.chunks_free)) {
622 * No free descriptors, allocate a page worth of them and try
623 * again, as someone else could race us to get the newly
624 * allocated descriptors. If the allocation fails return an
627 spin_unlock_irq(&chan->lock);
628 ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT);
631 spin_lock_irq(&chan->lock);
634 chunk = list_first_entry(&chan->desc.chunks_free,
635 struct rcar_dmac_xfer_chunk, node);
636 list_del(&chunk->node);
638 spin_unlock_irq(&chan->lock);
643 static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan,
644 struct rcar_dmac_desc *desc, size_t size)
647 * dma_alloc_coherent() allocates memory in page size increments. To
648 * avoid reallocating the hardware descriptors when the allocated size
649 * wouldn't change align the requested size to a multiple of the page
652 size = PAGE_ALIGN(size);
654 if (desc->hwdescs.size == size)
657 if (desc->hwdescs.mem) {
658 dma_free_coherent(NULL, desc->hwdescs.size, desc->hwdescs.mem,
660 desc->hwdescs.mem = NULL;
661 desc->hwdescs.size = 0;
667 desc->hwdescs.mem = dma_alloc_coherent(NULL, size, &desc->hwdescs.dma,
669 if (!desc->hwdescs.mem)
672 desc->hwdescs.size = size;
675 static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan,
676 struct rcar_dmac_desc *desc)
678 struct rcar_dmac_xfer_chunk *chunk;
679 struct rcar_dmac_hw_desc *hwdesc;
681 rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc));
683 hwdesc = desc->hwdescs.mem;
687 list_for_each_entry(chunk, &desc->chunks, node) {
688 hwdesc->sar = chunk->src_addr;
689 hwdesc->dar = chunk->dst_addr;
690 hwdesc->tcr = chunk->size >> desc->xfer_shift;
697 /* -----------------------------------------------------------------------------
701 static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
703 u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
705 chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
706 RCAR_DMACHCR_TE | RCAR_DMACHCR_DE);
707 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
710 static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
712 struct rcar_dmac_desc *desc, *_desc;
716 spin_lock_irqsave(&chan->lock, flags);
718 /* Move all non-free descriptors to the local lists. */
719 list_splice_init(&chan->desc.pending, &descs);
720 list_splice_init(&chan->desc.active, &descs);
721 list_splice_init(&chan->desc.done, &descs);
722 list_splice_init(&chan->desc.wait, &descs);
724 chan->desc.running = NULL;
726 spin_unlock_irqrestore(&chan->lock, flags);
728 list_for_each_entry_safe(desc, _desc, &descs, node) {
729 list_del(&desc->node);
730 rcar_dmac_desc_put(chan, desc);
734 static void rcar_dmac_stop(struct rcar_dmac *dmac)
736 rcar_dmac_write(dmac, RCAR_DMAOR, 0);
739 static void rcar_dmac_abort(struct rcar_dmac *dmac)
743 /* Stop all channels. */
744 for (i = 0; i < dmac->n_channels; ++i) {
745 struct rcar_dmac_chan *chan = &dmac->channels[i];
747 /* Stop and reinitialize the channel. */
748 spin_lock(&chan->lock);
749 rcar_dmac_chan_halt(chan);
750 spin_unlock(&chan->lock);
752 rcar_dmac_chan_reinit(chan);
756 /* -----------------------------------------------------------------------------
757 * Descriptors preparation
760 static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan,
761 struct rcar_dmac_desc *desc)
763 static const u32 chcr_ts[] = {
764 RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B,
765 RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B,
766 RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B,
770 unsigned int xfer_size;
773 switch (desc->direction) {
775 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED
776 | RCAR_DMACHCR_RS_DMARS;
777 xfer_size = chan->src_xfer_size;
781 chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC
782 | RCAR_DMACHCR_RS_DMARS;
783 xfer_size = chan->dst_xfer_size;
788 chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC
789 | RCAR_DMACHCR_RS_AUTO;
790 xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE;
794 desc->xfer_shift = ilog2(xfer_size);
795 desc->chcr = chcr | chcr_ts[desc->xfer_shift];
799 * rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list
801 * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
802 * converted to scatter-gather to guarantee consistent locking and a correct
803 * list manipulation. For slave DMA direction carries the usual meaning, and,
804 * logically, the SG list is RAM and the addr variable contains slave address,
805 * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
806 * and the SG list contains only one element and points at the source buffer.
808 static struct dma_async_tx_descriptor *
809 rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
810 unsigned int sg_len, dma_addr_t dev_addr,
811 enum dma_transfer_direction dir, unsigned long dma_flags,
814 struct rcar_dmac_xfer_chunk *chunk;
815 struct rcar_dmac_desc *desc;
816 struct scatterlist *sg;
817 unsigned int nchunks = 0;
818 unsigned int max_chunk_size;
819 unsigned int full_size = 0;
820 bool highmem = false;
823 desc = rcar_dmac_desc_get(chan);
827 desc->async_tx.flags = dma_flags;
828 desc->async_tx.cookie = -EBUSY;
830 desc->cyclic = cyclic;
831 desc->direction = dir;
833 rcar_dmac_chan_configure_desc(chan, desc);
835 max_chunk_size = (RCAR_DMATCR_MASK + 1) << desc->xfer_shift;
838 * Allocate and fill the transfer chunk descriptors. We own the only
839 * reference to the DMA descriptor, there's no need for locking.
841 for_each_sg(sgl, sg, sg_len, i) {
842 dma_addr_t mem_addr = sg_dma_address(sg);
843 unsigned int len = sg_dma_len(sg);
848 unsigned int size = min(len, max_chunk_size);
850 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
852 * Prevent individual transfers from crossing 4GB
855 if (dev_addr >> 32 != (dev_addr + size - 1) >> 32)
856 size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
857 if (mem_addr >> 32 != (mem_addr + size - 1) >> 32)
858 size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
861 * Check if either of the source or destination address
862 * can't be expressed in 32 bits. If so we can't use
863 * hardware descriptor lists.
865 if (dev_addr >> 32 || mem_addr >> 32)
869 chunk = rcar_dmac_xfer_chunk_get(chan);
871 rcar_dmac_desc_put(chan, desc);
875 if (dir == DMA_DEV_TO_MEM) {
876 chunk->src_addr = dev_addr;
877 chunk->dst_addr = mem_addr;
879 chunk->src_addr = mem_addr;
880 chunk->dst_addr = dev_addr;
885 dev_dbg(chan->chan.device->dev,
886 "chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n",
887 chan->index, chunk, desc, i, sg, size, len,
888 &chunk->src_addr, &chunk->dst_addr);
891 if (dir == DMA_MEM_TO_MEM)
896 list_add_tail(&chunk->node, &desc->chunks);
901 desc->nchunks = nchunks;
902 desc->size = full_size;
905 * Use hardware descriptor lists if possible when more than one chunk
906 * needs to be transferred (otherwise they don't make much sense).
908 * The highmem check currently covers the whole transfer. As an
909 * optimization we could use descriptor lists for consecutive lowmem
910 * chunks and direct manual mode for highmem chunks. Whether the
911 * performance improvement would be significant enough compared to the
912 * additional complexity remains to be investigated.
914 desc->hwdescs.use = !highmem && nchunks > 1;
915 if (desc->hwdescs.use) {
916 if (rcar_dmac_fill_hwdesc(chan, desc) < 0)
917 desc->hwdescs.use = false;
920 return &desc->async_tx;
923 /* -----------------------------------------------------------------------------
924 * DMA engine operations
927 static int rcar_dmac_alloc_chan_resources(struct dma_chan *chan)
929 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
932 INIT_LIST_HEAD(&rchan->desc.free);
933 INIT_LIST_HEAD(&rchan->desc.pending);
934 INIT_LIST_HEAD(&rchan->desc.active);
935 INIT_LIST_HEAD(&rchan->desc.done);
936 INIT_LIST_HEAD(&rchan->desc.wait);
937 INIT_LIST_HEAD(&rchan->desc.chunks_free);
938 INIT_LIST_HEAD(&rchan->desc.pages);
940 /* Preallocate descriptors. */
941 ret = rcar_dmac_xfer_chunk_alloc(rchan, GFP_KERNEL);
945 ret = rcar_dmac_desc_alloc(rchan, GFP_KERNEL);
949 return pm_runtime_get_sync(chan->device->dev);
952 static void rcar_dmac_free_chan_resources(struct dma_chan *chan)
954 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
955 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
956 struct rcar_dmac_desc_page *page, *_page;
957 struct rcar_dmac_desc *desc;
960 /* Protect against ISR */
961 spin_lock_irq(&rchan->lock);
962 rcar_dmac_chan_halt(rchan);
963 spin_unlock_irq(&rchan->lock);
965 /* Now no new interrupts will occur */
967 if (rchan->mid_rid >= 0) {
968 /* The caller is holding dma_list_mutex */
969 clear_bit(rchan->mid_rid, dmac->modules);
970 rchan->mid_rid = -EINVAL;
973 list_splice(&rchan->desc.free, &list);
974 list_splice(&rchan->desc.pending, &list);
975 list_splice(&rchan->desc.active, &list);
976 list_splice(&rchan->desc.done, &list);
977 list_splice(&rchan->desc.wait, &list);
979 list_for_each_entry(desc, &list, node)
980 rcar_dmac_realloc_hwdesc(rchan, desc, 0);
982 list_for_each_entry_safe(page, _page, &rchan->desc.pages, node) {
983 list_del(&page->node);
984 free_page((unsigned long)page);
987 pm_runtime_put(chan->device->dev);
990 static struct dma_async_tx_descriptor *
991 rcar_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
992 dma_addr_t dma_src, size_t len, unsigned long flags)
994 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
995 struct scatterlist sgl;
1000 sg_init_table(&sgl, 1);
1001 sg_set_page(&sgl, pfn_to_page(PFN_DOWN(dma_src)), len,
1002 offset_in_page(dma_src));
1003 sg_dma_address(&sgl) = dma_src;
1004 sg_dma_len(&sgl) = len;
1006 return rcar_dmac_chan_prep_sg(rchan, &sgl, 1, dma_dest,
1007 DMA_MEM_TO_MEM, flags, false);
1010 static struct dma_async_tx_descriptor *
1011 rcar_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1012 unsigned int sg_len, enum dma_transfer_direction dir,
1013 unsigned long flags, void *context)
1015 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1016 dma_addr_t dev_addr;
1018 /* Someone calling slave DMA on a generic channel? */
1019 if (rchan->mid_rid < 0 || !sg_len) {
1020 dev_warn(chan->device->dev,
1021 "%s: bad parameter: len=%d, id=%d\n",
1022 __func__, sg_len, rchan->mid_rid);
1026 dev_addr = dir == DMA_DEV_TO_MEM
1027 ? rchan->src_slave_addr : rchan->dst_slave_addr;
1028 return rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, dev_addr,
1032 #define RCAR_DMAC_MAX_SG_LEN 32
1034 static struct dma_async_tx_descriptor *
1035 rcar_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
1036 size_t buf_len, size_t period_len,
1037 enum dma_transfer_direction dir, unsigned long flags)
1039 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1040 struct dma_async_tx_descriptor *desc;
1041 struct scatterlist *sgl;
1042 dma_addr_t dev_addr;
1043 unsigned int sg_len;
1046 /* Someone calling slave DMA on a generic channel? */
1047 if (rchan->mid_rid < 0 || buf_len < period_len) {
1048 dev_warn(chan->device->dev,
1049 "%s: bad parameter: buf_len=%zu, period_len=%zu, id=%d\n",
1050 __func__, buf_len, period_len, rchan->mid_rid);
1054 sg_len = buf_len / period_len;
1055 if (sg_len > RCAR_DMAC_MAX_SG_LEN) {
1056 dev_err(chan->device->dev,
1057 "chan%u: sg length %d exceds limit %d",
1058 rchan->index, sg_len, RCAR_DMAC_MAX_SG_LEN);
1063 * Allocate the sg list dynamically as it would consume too much stack
1066 sgl = kcalloc(sg_len, sizeof(*sgl), GFP_NOWAIT);
1070 sg_init_table(sgl, sg_len);
1072 for (i = 0; i < sg_len; ++i) {
1073 dma_addr_t src = buf_addr + (period_len * i);
1075 sg_set_page(&sgl[i], pfn_to_page(PFN_DOWN(src)), period_len,
1076 offset_in_page(src));
1077 sg_dma_address(&sgl[i]) = src;
1078 sg_dma_len(&sgl[i]) = period_len;
1081 dev_addr = dir == DMA_DEV_TO_MEM
1082 ? rchan->src_slave_addr : rchan->dst_slave_addr;
1083 desc = rcar_dmac_chan_prep_sg(rchan, sgl, sg_len, dev_addr,
1090 static int rcar_dmac_device_config(struct dma_chan *chan,
1091 struct dma_slave_config *cfg)
1093 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1096 * We could lock this, but you shouldn't be configuring the
1097 * channel, while using it...
1099 rchan->src_slave_addr = cfg->src_addr;
1100 rchan->dst_slave_addr = cfg->dst_addr;
1101 rchan->src_xfer_size = cfg->src_addr_width;
1102 rchan->dst_xfer_size = cfg->dst_addr_width;
1107 static int rcar_dmac_chan_terminate_all(struct dma_chan *chan)
1109 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1110 unsigned long flags;
1112 spin_lock_irqsave(&rchan->lock, flags);
1113 rcar_dmac_chan_halt(rchan);
1114 spin_unlock_irqrestore(&rchan->lock, flags);
1117 * FIXME: No new interrupt can occur now, but the IRQ thread might still
1121 rcar_dmac_chan_reinit(rchan);
1126 static unsigned int rcar_dmac_chan_get_residue(struct rcar_dmac_chan *chan,
1127 dma_cookie_t cookie)
1129 struct rcar_dmac_desc *desc = chan->desc.running;
1130 struct rcar_dmac_xfer_chunk *running = NULL;
1131 struct rcar_dmac_xfer_chunk *chunk;
1132 unsigned int residue = 0;
1133 unsigned int dptr = 0;
1139 * If the cookie doesn't correspond to the currently running transfer
1140 * then the descriptor hasn't been processed yet, and the residue is
1141 * equal to the full descriptor size.
1143 if (cookie != desc->async_tx.cookie)
1147 * In descriptor mode the descriptor running pointer is not maintained
1148 * by the interrupt handler, find the running descriptor from the
1149 * descriptor pointer field in the CHCRB register. In non-descriptor
1150 * mode just use the running descriptor pointer.
1152 if (desc->hwdescs.use) {
1153 dptr = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1154 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1155 WARN_ON(dptr >= desc->nchunks);
1157 running = desc->running;
1160 /* Compute the size of all chunks still to be transferred. */
1161 list_for_each_entry_reverse(chunk, &desc->chunks, node) {
1162 if (chunk == running || ++dptr == desc->nchunks)
1165 residue += chunk->size;
1168 /* Add the residue for the current chunk. */
1169 residue += rcar_dmac_chan_read(chan, RCAR_DMATCR) << desc->xfer_shift;
1174 static enum dma_status rcar_dmac_tx_status(struct dma_chan *chan,
1175 dma_cookie_t cookie,
1176 struct dma_tx_state *txstate)
1178 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1179 enum dma_status status;
1180 unsigned long flags;
1181 unsigned int residue;
1183 status = dma_cookie_status(chan, cookie, txstate);
1184 if (status == DMA_COMPLETE || !txstate)
1187 spin_lock_irqsave(&rchan->lock, flags);
1188 residue = rcar_dmac_chan_get_residue(rchan, cookie);
1189 spin_unlock_irqrestore(&rchan->lock, flags);
1191 dma_set_residue(txstate, residue);
1196 static void rcar_dmac_issue_pending(struct dma_chan *chan)
1198 struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
1199 unsigned long flags;
1201 spin_lock_irqsave(&rchan->lock, flags);
1203 if (list_empty(&rchan->desc.pending))
1206 /* Append the pending list to the active list. */
1207 list_splice_tail_init(&rchan->desc.pending, &rchan->desc.active);
1210 * If no transfer is running pick the first descriptor from the active
1211 * list and start the transfer.
1213 if (!rchan->desc.running) {
1214 struct rcar_dmac_desc *desc;
1216 desc = list_first_entry(&rchan->desc.active,
1217 struct rcar_dmac_desc, node);
1218 rchan->desc.running = desc;
1220 rcar_dmac_chan_start_xfer(rchan);
1224 spin_unlock_irqrestore(&rchan->lock, flags);
1227 /* -----------------------------------------------------------------------------
1231 static irqreturn_t rcar_dmac_isr_desc_stage_end(struct rcar_dmac_chan *chan)
1233 struct rcar_dmac_desc *desc = chan->desc.running;
1236 if (WARN_ON(!desc || !desc->cyclic)) {
1238 * This should never happen, there should always be a running
1239 * cyclic descriptor when a descriptor stage end interrupt is
1240 * triggered. Warn and return.
1245 /* Program the interrupt pointer to the next stage. */
1246 stage = (rcar_dmac_chan_read(chan, RCAR_DMACHCRB) &
1247 RCAR_DMACHCRB_DPTR_MASK) >> RCAR_DMACHCRB_DPTR_SHIFT;
1248 rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(stage));
1250 return IRQ_WAKE_THREAD;
1253 static irqreturn_t rcar_dmac_isr_transfer_end(struct rcar_dmac_chan *chan)
1255 struct rcar_dmac_desc *desc = chan->desc.running;
1256 irqreturn_t ret = IRQ_WAKE_THREAD;
1258 if (WARN_ON_ONCE(!desc)) {
1260 * This should never happen, there should always be a running
1261 * descriptor when a transfer end interrupt is triggered. Warn
1268 * The transfer end interrupt isn't generated for each chunk when using
1269 * descriptor mode. Only update the running chunk pointer in
1270 * non-descriptor mode.
1272 if (!desc->hwdescs.use) {
1274 * If we haven't completed the last transfer chunk simply move
1275 * to the next one. Only wake the IRQ thread if the transfer is
1278 if (!list_is_last(&desc->running->node, &desc->chunks)) {
1279 desc->running = list_next_entry(desc->running, node);
1286 * We've completed the last transfer chunk. If the transfer is
1287 * cyclic, move back to the first one.
1291 list_first_entry(&desc->chunks,
1292 struct rcar_dmac_xfer_chunk,
1298 /* The descriptor is complete, move it to the done list. */
1299 list_move_tail(&desc->node, &chan->desc.done);
1301 /* Queue the next descriptor, if any. */
1302 if (!list_empty(&chan->desc.active))
1303 chan->desc.running = list_first_entry(&chan->desc.active,
1304 struct rcar_dmac_desc,
1307 chan->desc.running = NULL;
1310 if (chan->desc.running)
1311 rcar_dmac_chan_start_xfer(chan);
1316 static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
1318 u32 mask = RCAR_DMACHCR_DSE | RCAR_DMACHCR_TE;
1319 struct rcar_dmac_chan *chan = dev;
1320 irqreturn_t ret = IRQ_NONE;
1323 spin_lock(&chan->lock);
1325 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
1326 if (chcr & RCAR_DMACHCR_TE)
1327 mask |= RCAR_DMACHCR_DE;
1328 rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr & ~mask);
1330 if (chcr & RCAR_DMACHCR_DSE)
1331 ret |= rcar_dmac_isr_desc_stage_end(chan);
1333 if (chcr & RCAR_DMACHCR_TE)
1334 ret |= rcar_dmac_isr_transfer_end(chan);
1336 spin_unlock(&chan->lock);
1341 static irqreturn_t rcar_dmac_isr_channel_thread(int irq, void *dev)
1343 struct rcar_dmac_chan *chan = dev;
1344 struct rcar_dmac_desc *desc;
1346 spin_lock_irq(&chan->lock);
1348 /* For cyclic transfers notify the user after every chunk. */
1349 if (chan->desc.running && chan->desc.running->cyclic) {
1350 dma_async_tx_callback callback;
1351 void *callback_param;
1353 desc = chan->desc.running;
1354 callback = desc->async_tx.callback;
1355 callback_param = desc->async_tx.callback_param;
1358 spin_unlock_irq(&chan->lock);
1359 callback(callback_param);
1360 spin_lock_irq(&chan->lock);
1365 * Call the callback function for all descriptors on the done list and
1366 * move them to the ack wait list.
1368 while (!list_empty(&chan->desc.done)) {
1369 desc = list_first_entry(&chan->desc.done, struct rcar_dmac_desc,
1371 dma_cookie_complete(&desc->async_tx);
1372 list_del(&desc->node);
1374 if (desc->async_tx.callback) {
1375 spin_unlock_irq(&chan->lock);
1377 * We own the only reference to this descriptor, we can
1378 * safely dereference it without holding the channel
1381 desc->async_tx.callback(desc->async_tx.callback_param);
1382 spin_lock_irq(&chan->lock);
1385 list_add_tail(&desc->node, &chan->desc.wait);
1388 spin_unlock_irq(&chan->lock);
1390 /* Recycle all acked descriptors. */
1391 rcar_dmac_desc_recycle_acked(chan);
1396 static irqreturn_t rcar_dmac_isr_error(int irq, void *data)
1398 struct rcar_dmac *dmac = data;
1400 if (!(rcar_dmac_read(dmac, RCAR_DMAOR) & RCAR_DMAOR_AE))
1404 * An unrecoverable error occurred on an unknown channel. Halt the DMAC,
1405 * abort transfers on all channels, and reinitialize the DMAC.
1407 rcar_dmac_stop(dmac);
1408 rcar_dmac_abort(dmac);
1409 rcar_dmac_init(dmac);
1414 /* -----------------------------------------------------------------------------
1415 * OF xlate and channel filter
1418 static bool rcar_dmac_chan_filter(struct dma_chan *chan, void *arg)
1420 struct rcar_dmac *dmac = to_rcar_dmac(chan->device);
1421 struct of_phandle_args *dma_spec = arg;
1424 * FIXME: Using a filter on OF platforms is a nonsense. The OF xlate
1425 * function knows from which device it wants to allocate a channel from,
1426 * and would be perfectly capable of selecting the channel it wants.
1427 * Forcing it to call dma_request_channel() and iterate through all
1428 * channels from all controllers is just pointless.
1430 if (chan->device->device_config != rcar_dmac_device_config ||
1431 dma_spec->np != chan->device->dev->of_node)
1434 return !test_and_set_bit(dma_spec->args[0], dmac->modules);
1437 static struct dma_chan *rcar_dmac_of_xlate(struct of_phandle_args *dma_spec,
1438 struct of_dma *ofdma)
1440 struct rcar_dmac_chan *rchan;
1441 struct dma_chan *chan;
1442 dma_cap_mask_t mask;
1444 if (dma_spec->args_count != 1)
1447 /* Only slave DMA channels can be allocated via DT */
1449 dma_cap_set(DMA_SLAVE, mask);
1451 chan = dma_request_channel(mask, rcar_dmac_chan_filter, dma_spec);
1455 rchan = to_rcar_dmac_chan(chan);
1456 rchan->mid_rid = dma_spec->args[0];
1461 /* -----------------------------------------------------------------------------
1465 #ifdef CONFIG_PM_SLEEP
1466 static int rcar_dmac_sleep_suspend(struct device *dev)
1469 * TODO: Wait for the current transfer to complete and stop the device.
1474 static int rcar_dmac_sleep_resume(struct device *dev)
1476 /* TODO: Resume transfers, if any. */
1482 static int rcar_dmac_runtime_suspend(struct device *dev)
1487 static int rcar_dmac_runtime_resume(struct device *dev)
1489 struct rcar_dmac *dmac = dev_get_drvdata(dev);
1491 return rcar_dmac_init(dmac);
1495 static const struct dev_pm_ops rcar_dmac_pm = {
1496 SET_SYSTEM_SLEEP_PM_OPS(rcar_dmac_sleep_suspend, rcar_dmac_sleep_resume)
1497 SET_RUNTIME_PM_OPS(rcar_dmac_runtime_suspend, rcar_dmac_runtime_resume,
1501 /* -----------------------------------------------------------------------------
1505 static int rcar_dmac_chan_probe(struct rcar_dmac *dmac,
1506 struct rcar_dmac_chan *rchan,
1509 struct platform_device *pdev = to_platform_device(dmac->dev);
1510 struct dma_chan *chan = &rchan->chan;
1511 char pdev_irqname[5];
1516 rchan->index = index;
1517 rchan->iomem = dmac->iomem + RCAR_DMAC_CHAN_OFFSET(index);
1518 rchan->mid_rid = -EINVAL;
1520 spin_lock_init(&rchan->lock);
1522 /* Request the channel interrupt. */
1523 sprintf(pdev_irqname, "ch%u", index);
1524 irq = platform_get_irq_byname(pdev, pdev_irqname);
1526 dev_err(dmac->dev, "no IRQ specified for channel %u\n", index);
1530 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:%u",
1531 dev_name(dmac->dev), index);
1535 ret = devm_request_threaded_irq(dmac->dev, irq, rcar_dmac_isr_channel,
1536 rcar_dmac_isr_channel_thread, 0,
1539 dev_err(dmac->dev, "failed to request IRQ %u (%d)\n", irq, ret);
1544 * Initialize the DMA engine channel and add it to the DMA engine
1547 chan->device = &dmac->engine;
1548 dma_cookie_init(chan);
1550 list_add_tail(&chan->device_node, &dmac->engine.channels);
1555 static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
1557 struct device_node *np = dev->of_node;
1560 ret = of_property_read_u32(np, "dma-channels", &dmac->n_channels);
1562 dev_err(dev, "unable to read dma-channels property\n");
1566 if (dmac->n_channels <= 0 || dmac->n_channels >= 100) {
1567 dev_err(dev, "invalid number of channels %u\n",
1575 static int rcar_dmac_probe(struct platform_device *pdev)
1577 const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE |
1578 DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
1579 DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
1580 DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
1581 struct dma_device *engine;
1582 struct rcar_dmac *dmac;
1583 struct resource *mem;
1589 dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
1593 dmac->dev = &pdev->dev;
1594 platform_set_drvdata(pdev, dmac);
1596 ret = rcar_dmac_parse_of(&pdev->dev, dmac);
1600 dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
1601 sizeof(*dmac->channels), GFP_KERNEL);
1602 if (!dmac->channels)
1605 /* Request resources. */
1606 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1607 dmac->iomem = devm_ioremap_resource(&pdev->dev, mem);
1608 if (IS_ERR(dmac->iomem))
1609 return PTR_ERR(dmac->iomem);
1611 irq = platform_get_irq_byname(pdev, "error");
1613 dev_err(&pdev->dev, "no error IRQ specified\n");
1617 irqname = devm_kasprintf(dmac->dev, GFP_KERNEL, "%s:error",
1618 dev_name(dmac->dev));
1622 ret = devm_request_irq(&pdev->dev, irq, rcar_dmac_isr_error, 0,
1625 dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
1630 /* Enable runtime PM and initialize the device. */
1631 pm_runtime_enable(&pdev->dev);
1632 ret = pm_runtime_get_sync(&pdev->dev);
1634 dev_err(&pdev->dev, "runtime PM get sync failed (%d)\n", ret);
1638 ret = rcar_dmac_init(dmac);
1639 pm_runtime_put(&pdev->dev);
1642 dev_err(&pdev->dev, "failed to reset device\n");
1646 /* Initialize the channels. */
1647 INIT_LIST_HEAD(&dmac->engine.channels);
1649 for (i = 0; i < dmac->n_channels; ++i) {
1650 ret = rcar_dmac_chan_probe(dmac, &dmac->channels[i], i);
1655 /* Register the DMAC as a DMA provider for DT. */
1656 ret = of_dma_controller_register(pdev->dev.of_node, rcar_dmac_of_xlate,
1662 * Register the DMA engine device.
1664 * Default transfer size of 32 bytes requires 32-byte alignment.
1666 engine = &dmac->engine;
1667 dma_cap_set(DMA_MEMCPY, engine->cap_mask);
1668 dma_cap_set(DMA_SLAVE, engine->cap_mask);
1670 engine->dev = &pdev->dev;
1671 engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE);
1673 engine->src_addr_widths = widths;
1674 engine->dst_addr_widths = widths;
1675 engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1676 engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1678 engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources;
1679 engine->device_free_chan_resources = rcar_dmac_free_chan_resources;
1680 engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy;
1681 engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg;
1682 engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic;
1683 engine->device_config = rcar_dmac_device_config;
1684 engine->device_terminate_all = rcar_dmac_chan_terminate_all;
1685 engine->device_tx_status = rcar_dmac_tx_status;
1686 engine->device_issue_pending = rcar_dmac_issue_pending;
1688 ret = dma_async_device_register(engine);
1695 of_dma_controller_free(pdev->dev.of_node);
1696 pm_runtime_disable(&pdev->dev);
1700 static int rcar_dmac_remove(struct platform_device *pdev)
1702 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1704 of_dma_controller_free(pdev->dev.of_node);
1705 dma_async_device_unregister(&dmac->engine);
1707 pm_runtime_disable(&pdev->dev);
1712 static void rcar_dmac_shutdown(struct platform_device *pdev)
1714 struct rcar_dmac *dmac = platform_get_drvdata(pdev);
1716 rcar_dmac_stop(dmac);
1719 static const struct of_device_id rcar_dmac_of_ids[] = {
1720 { .compatible = "renesas,rcar-dmac", },
1723 MODULE_DEVICE_TABLE(of, rcar_dmac_of_ids);
1725 static struct platform_driver rcar_dmac_driver = {
1727 .pm = &rcar_dmac_pm,
1728 .name = "rcar-dmac",
1729 .of_match_table = rcar_dmac_of_ids,
1731 .probe = rcar_dmac_probe,
1732 .remove = rcar_dmac_remove,
1733 .shutdown = rcar_dmac_shutdown,
1736 module_platform_driver(rcar_dmac_driver);
1738 MODULE_DESCRIPTION("R-Car Gen2 DMA Controller Driver");
1739 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1740 MODULE_LICENSE("GPL v2");