drivers/dma/imx-dma.c

   1 /*
   2  * drivers/dma/imx-dma.c
   3  *
   4  * This file contains a driver for the Freescale i.MX DMA engine
   5  * found on i.MX1/21/27
   6  *
   7  * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
   8  * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
   9  *
  10  * The code contained herein is licensed under the GNU General Public
  11  * License. You may obtain a copy of the GNU General Public License
  12  * Version 2 or later at the following locations:
  13  *
  14  * http://www.opensource.org/licenses/gpl-license.html
  15  * http://www.gnu.org/copyleft/gpl.html
  16  */
  17 #include <linux/init.h>
  18 #include <linux/types.h>
  19 #include <linux/mm.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/slab.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/module.h>
  29
  30 #include <asm/irq.h>
  31 #include <mach/dma.h>
  32 #include <mach/hardware.h>
  33
  34 #include "dmaengine.h"
  35 #define IMXDMA_MAX_CHAN_DESCRIPTORS     16
  36 #define IMX_DMA_CHANNELS  16
  37
  38 #define IMX_DMA_2D_SLOTS        2
  39 #define IMX_DMA_2D_SLOT_A       0
  40 #define IMX_DMA_2D_SLOT_B       1
  41
  42 #define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
  43 #define IMX_DMA_MEMSIZE_32      (0 << 4)
  44 #define IMX_DMA_MEMSIZE_8       (1 << 4)
  45 #define IMX_DMA_MEMSIZE_16      (2 << 4)
  46 #define IMX_DMA_TYPE_LINEAR     (0 << 10)
  47 #define IMX_DMA_TYPE_2D         (1 << 10)
  48 #define IMX_DMA_TYPE_FIFO       (2 << 10)
  49
  50 #define IMX_DMA_ERR_BURST     (1 << 0)
  51 #define IMX_DMA_ERR_REQUEST   (1 << 1)
  52 #define IMX_DMA_ERR_TRANSFER  (1 << 2)
  53 #define IMX_DMA_ERR_BUFFER    (1 << 3)
  54 #define IMX_DMA_ERR_TIMEOUT   (1 << 4)
  55
  56 #define DMA_DCR     0x00                /* Control Register */
  57 #define DMA_DISR    0x04                /* Interrupt status Register */
  58 #define DMA_DIMR    0x08                /* Interrupt mask Register */
  59 #define DMA_DBTOSR  0x0c                /* Burst timeout status Register */
  60 #define DMA_DRTOSR  0x10                /* Request timeout Register */
  61 #define DMA_DSESR   0x14                /* Transfer Error Status Register */
  62 #define DMA_DBOSR   0x18                /* Buffer overflow status Register */
  63 #define DMA_DBTOCR  0x1c                /* Burst timeout control Register */
  64 #define DMA_WSRA    0x40                /* W-Size Register A */
  65 #define DMA_XSRA    0x44                /* X-Size Register A */
  66 #define DMA_YSRA    0x48                /* Y-Size Register A */
  67 #define DMA_WSRB    0x4c                /* W-Size Register B */
  68 #define DMA_XSRB    0x50                /* X-Size Register B */
  69 #define DMA_YSRB    0x54                /* Y-Size Register B */
  70 #define DMA_SAR(x)  (0x80 + ((x) << 6)) /* Source Address Registers */
  71 #define DMA_DAR(x)  (0x84 + ((x) << 6)) /* Destination Address Registers */
  72 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
  73 #define DMA_CCR(x)  (0x8c + ((x) << 6)) /* Control Registers */
  74 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
  75 #define DMA_BLR(x)  (0x94 + ((x) << 6)) /* Burst length Registers */
  76 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
  77 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
  78 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
  79
  80 #define DCR_DRST           (1<<1)
  81 #define DCR_DEN            (1<<0)
  82 #define DBTOCR_EN          (1<<15)
  83 #define DBTOCR_CNT(x)      ((x) & 0x7fff)
  84 #define CNTR_CNT(x)        ((x) & 0xffffff)
  85 #define CCR_ACRPT          (1<<14)
  86 #define CCR_DMOD_LINEAR    (0x0 << 12)
  87 #define CCR_DMOD_2D        (0x1 << 12)
  88 #define CCR_DMOD_FIFO      (0x2 << 12)
  89 #define CCR_DMOD_EOBFIFO   (0x3 << 12)
  90 #define CCR_SMOD_LINEAR    (0x0 << 10)
  91 #define CCR_SMOD_2D        (0x1 << 10)
  92 #define CCR_SMOD_FIFO      (0x2 << 10)
  93 #define CCR_SMOD_EOBFIFO   (0x3 << 10)
  94 #define CCR_MDIR_DEC       (1<<9)
  95 #define CCR_MSEL_B         (1<<8)
  96 #define CCR_DSIZ_32        (0x0 << 6)
  97 #define CCR_DSIZ_8         (0x1 << 6)
  98 #define CCR_DSIZ_16        (0x2 << 6)
  99 #define CCR_SSIZ_32        (0x0 << 4)
 100 #define CCR_SSIZ_8         (0x1 << 4)
 101 #define CCR_SSIZ_16        (0x2 << 4)
 102 #define CCR_REN            (1<<3)
 103 #define CCR_RPT            (1<<2)
 104 #define CCR_FRC            (1<<1)
 105 #define CCR_CEN            (1<<0)
 106 #define RTOR_EN            (1<<15)
 107 #define RTOR_CLK           (1<<14)
 108 #define RTOR_PSC           (1<<13)
 109
 110 enum  imxdma_prep_type {
 111         IMXDMA_DESC_MEMCPY,
 112         IMXDMA_DESC_INTERLEAVED,
 113         IMXDMA_DESC_SLAVE_SG,
 114         IMXDMA_DESC_CYCLIC,
 115 };
 116
 117 struct imx_dma_2d_config {
 118         u16             xsr;
 119         u16             ysr;
 120         u16             wsr;
 121         int             count;
 122 };
 123
 124 struct imxdma_desc {
 125         struct list_head                node;
 126         struct dma_async_tx_descriptor  desc;
 127         enum dma_status                 status;
 128         dma_addr_t                      src;
 129         dma_addr_t                      dest;
 130         size_t                          len;
 131         enum dma_transfer_direction     direction;
 132         enum imxdma_prep_type           type;
 133         /* For memcpy and interleaved */
 134         unsigned int                    config_port;
 135         unsigned int                    config_mem;
 136         /* For interleaved transfers */
 137         unsigned int                    x;
 138         unsigned int                    y;
 139         unsigned int                    w;
 140         /* For slave sg and cyclic */
 141         struct scatterlist              *sg;
 142         unsigned int                    sgcount;
 143 };
 144
 145 struct imxdma_channel {
 146         int                             hw_chaining;
 147         struct timer_list               watchdog;
 148         struct imxdma_engine            *imxdma;
 149         unsigned int                    channel;
 150
 151         struct tasklet_struct           dma_tasklet;
 152         struct list_head                ld_free;
 153         struct list_head                ld_queue;
 154         struct list_head                ld_active;
 155         int                             descs_allocated;
 156         enum dma_slave_buswidth         word_size;
 157         dma_addr_t                      per_address;
 158         u32                             watermark_level;
 159         struct dma_chan                 chan;
 160         struct dma_async_tx_descriptor  desc;
 161         enum dma_status                 status;
 162         int                             dma_request;
 163         struct scatterlist              *sg_list;
 164         u32                             ccr_from_device;
 165         u32                             ccr_to_device;
 166         bool                            enabled_2d;
 167         int                             slot_2d;
 168 };
 169
 170 struct imxdma_engine {
 171         struct device                   *dev;
 172         struct device_dma_parameters    dma_parms;
 173         struct dma_device               dma_device;
 174         void __iomem                    *base;
 175         struct clk                      *dma_clk;
 176         spinlock_t                      lock;
 177         struct imx_dma_2d_config        slots_2d[IMX_DMA_2D_SLOTS];
 178         struct imxdma_channel           channel[IMX_DMA_CHANNELS];
 179 };
 180
 181 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
 182 {
 183         return container_of(chan, struct imxdma_channel, chan);
 184 }
 185
 186 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
 187 {
 188         struct imxdma_desc *desc;
 189
 190         if (!list_empty(&imxdmac->ld_active)) {
 191                 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
 192                                         node);
 193                 if (desc->type == IMXDMA_DESC_CYCLIC)
 194                         return true;
 195         }
 196         return false;
 197 }
 198
 199
 200
 201 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
 202                              unsigned offset)
 203 {
 204         __raw_writel(val, imxdma->base + offset);
 205 }
 206
 207 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
 208 {
 209         return __raw_readl(imxdma->base + offset);
 210 }
 211
 212 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
 213 {
 214         if (cpu_is_mx27())
 215                 return imxdmac->hw_chaining;
 216         else
 217                 return 0;
 218 }
 219
 220 /*
 221  * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
 222  */
 223 static inline int imxdma_sg_next(struct imxdma_desc *d)
 224 {
 225         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 226         struct imxdma_engine *imxdma = imxdmac->imxdma;
 227         struct scatterlist *sg = d->sg;
 228         unsigned long now;
 229
 230         now = min(d->len, sg->length);
 231         if (d->len != IMX_DMA_LENGTH_LOOP)
 232                 d->len -= now;
 233
 234         if (d->direction == DMA_DEV_TO_MEM)
 235                 imx_dmav1_writel(imxdma, sg->dma_address,
 236                                  DMA_DAR(imxdmac->channel));
 237         else
 238                 imx_dmav1_writel(imxdma, sg->dma_address,
 239                                  DMA_SAR(imxdmac->channel));
 240
 241         imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
 242
 243         dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
 244                 "size 0x%08x\n", __func__, imxdmac->channel,
 245                  imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
 246                  imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
 247                  imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
 248
 249         return now;
 250 }
 251
 252 static void imxdma_enable_hw(struct imxdma_desc *d)
 253 {
 254         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 255         struct imxdma_engine *imxdma = imxdmac->imxdma;
 256         int channel = imxdmac->channel;
 257         unsigned long flags;
 258
 259         dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 260
 261         local_irq_save(flags);
 262
 263         imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 264         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
 265                          ~(1 << channel), DMA_DIMR);
 266         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
 267                          CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
 268
 269         if ((cpu_is_mx21() || cpu_is_mx27()) &&
 270                         d->sg && imxdma_hw_chain(imxdmac)) {
 271                 d->sg = sg_next(d->sg);
 272                 if (d->sg) {
 273                         u32 tmp;
 274                         imxdma_sg_next(d);
 275                         tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
 276                         imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
 277                                          DMA_CCR(channel));
 278                 }
 279         }
 280
 281         local_irq_restore(flags);
 282 }
 283
 284 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
 285 {
 286         struct imxdma_engine *imxdma = imxdmac->imxdma;
 287         int channel = imxdmac->channel;
 288         unsigned long flags;
 289
 290         dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
 291
 292         if (imxdma_hw_chain(imxdmac))
 293                 del_timer(&imxdmac->watchdog);
 294
 295         local_irq_save(flags);
 296         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
 297                          (1 << channel), DMA_DIMR);
 298         imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
 299                          ~CCR_CEN, DMA_CCR(channel));
 300         imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
 301         local_irq_restore(flags);
 302 }
 303
 304 static void imxdma_watchdog(unsigned long data)
 305 {
 306         struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
 307         struct imxdma_engine *imxdma = imxdmac->imxdma;
 308         int channel = imxdmac->channel;
 309
 310         imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
 311
 312         /* Tasklet watchdog error handler */
 313         tasklet_schedule(&imxdmac->dma_tasklet);
 314         dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
 315                 imxdmac->channel);
 316 }
 317
 318 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
 319 {
 320         struct imxdma_engine *imxdma = dev_id;
 321         unsigned int err_mask;
 322         int i, disr;
 323         int errcode;
 324
 325         disr = imx_dmav1_readl(imxdma, DMA_DISR);
 326
 327         err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
 328                    imx_dmav1_readl(imxdma, DMA_DRTOSR) |
 329                    imx_dmav1_readl(imxdma, DMA_DSESR)  |
 330                    imx_dmav1_readl(imxdma, DMA_DBOSR);
 331
 332         if (!err_mask)
 333                 return IRQ_HANDLED;
 334
 335         imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
 336
 337         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 338                 if (!(err_mask & (1 << i)))
 339                         continue;
 340                 errcode = 0;
 341
 342                 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
 343                         imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
 344                         errcode |= IMX_DMA_ERR_BURST;
 345                 }
 346                 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
 347                         imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
 348                         errcode |= IMX_DMA_ERR_REQUEST;
 349                 }
 350                 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
 351                         imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
 352                         errcode |= IMX_DMA_ERR_TRANSFER;
 353                 }
 354                 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
 355                         imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
 356                         errcode |= IMX_DMA_ERR_BUFFER;
 357                 }
 358                 /* Tasklet error handler */
 359                 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
 360
 361                 printk(KERN_WARNING
 362                        "DMA timeout on channel %d -%s%s%s%s\n", i,
 363                        errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
 364                        errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
 365                        errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
 366                        errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
 367         }
 368         return IRQ_HANDLED;
 369 }
 370
 371 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 372 {
 373         struct imxdma_engine *imxdma = imxdmac->imxdma;
 374         int chno = imxdmac->channel;
 375         struct imxdma_desc *desc;
 376
 377         spin_lock(&imxdma->lock);
 378         if (list_empty(&imxdmac->ld_active)) {
 379                 spin_unlock(&imxdma->lock);
 380                 goto out;
 381         }
 382
 383         desc = list_first_entry(&imxdmac->ld_active,
 384                                 struct imxdma_desc,
 385                                 node);
 386         spin_unlock(&imxdma->lock);
 387
 388         if (desc->sg) {
 389                 u32 tmp;
 390                 desc->sg = sg_next(desc->sg);
 391
 392                 if (desc->sg) {
 393                         imxdma_sg_next(desc);
 394
 395                         tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
 396
 397                         if (imxdma_hw_chain(imxdmac)) {
 398                                 /* FIXME: The timeout should probably be
 399                                  * configurable
 400                                  */
 401                                 mod_timer(&imxdmac->watchdog,
 402                                         jiffies + msecs_to_jiffies(500));
 403
 404                                 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
 405                                 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 406                         } else {
 407                                 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
 408                                                  DMA_CCR(chno));
 409                                 tmp |= CCR_CEN;
 410                         }
 411
 412                         imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
 413
 414                         if (imxdma_chan_is_doing_cyclic(imxdmac))
 415                                 /* Tasklet progression */
 416                                 tasklet_schedule(&imxdmac->dma_tasklet);
 417
 418                         return;
 419                 }
 420
 421                 if (imxdma_hw_chain(imxdmac)) {
 422                         del_timer(&imxdmac->watchdog);
 423                         return;
 424                 }
 425         }
 426
 427 out:
 428         imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
 429         /* Tasklet irq */
 430         tasklet_schedule(&imxdmac->dma_tasklet);
 431 }
 432
 433 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 434 {
 435         struct imxdma_engine *imxdma = dev_id;
 436         int i, disr;
 437
 438         if (cpu_is_mx21() || cpu_is_mx27())
 439                 imxdma_err_handler(irq, dev_id);
 440
 441         disr = imx_dmav1_readl(imxdma, DMA_DISR);
 442
 443         dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
 444
 445         imx_dmav1_writel(imxdma, disr, DMA_DISR);
 446         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 447                 if (disr & (1 << i))
 448                         dma_irq_handle_channel(&imxdma->channel[i]);
 449         }
 450
 451         return IRQ_HANDLED;
 452 }
 453
 454 static int imxdma_xfer_desc(struct imxdma_desc *d)
 455 {
 456         struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
 457         struct imxdma_engine *imxdma = imxdmac->imxdma;
 458         unsigned long flags;
 459         int slot = -1;
 460         int i;
 461
 462         /* Configure and enable */
 463         switch (d->type) {
 464         case IMXDMA_DESC_INTERLEAVED:
 465                 /* Try to get a free 2D slot */
 466                 spin_lock_irqsave(&imxdma->lock, flags);
 467                 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
 468                         if ((imxdma->slots_2d[i].count > 0) &&
 469                         ((imxdma->slots_2d[i].xsr != d->x) ||
 470                         (imxdma->slots_2d[i].ysr != d->y) ||
 471                         (imxdma->slots_2d[i].wsr != d->w)))
 472                                 continue;
 473                         slot = i;
 474                         break;
 475                 }
 476                 if (slot < 0)
 477                         return -EBUSY;
 478
 479                 imxdma->slots_2d[slot].xsr = d->x;
 480                 imxdma->slots_2d[slot].ysr = d->y;
 481                 imxdma->slots_2d[slot].wsr = d->w;
 482                 imxdma->slots_2d[slot].count++;
 483
 484                 imxdmac->slot_2d = slot;
 485                 imxdmac->enabled_2d = true;
 486                 spin_unlock_irqrestore(&imxdma->lock, flags);
 487
 488                 if (slot == IMX_DMA_2D_SLOT_A) {
 489                         d->config_mem &= ~CCR_MSEL_B;
 490                         d->config_port &= ~CCR_MSEL_B;
 491                         imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
 492                         imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
 493                         imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
 494                 } else {
 495                         d->config_mem |= CCR_MSEL_B;
 496                         d->config_port |= CCR_MSEL_B;
 497                         imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
 498                         imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
 499                         imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
 500                 }
 501                 /*
 502                  * We fall-through here intentionally, since a 2D transfer is
 503                  * similar to MEMCPY just adding the 2D slot configuration.
 504                  */
 505         case IMXDMA_DESC_MEMCPY:
 506                 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
 507                 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
 508                 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
 509                          DMA_CCR(imxdmac->channel));
 510
 511                 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
 512
 513                 dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
 514                         "dma_length=%d\n", __func__, imxdmac->channel,
 515                         d->dest, d->src, d->len);
 516
 517                 break;
 518         /* Cyclic transfer is the same as slave_sg with special sg configuration. */
 519         case IMXDMA_DESC_CYCLIC:
 520         case IMXDMA_DESC_SLAVE_SG:
 521                 if (d->direction == DMA_DEV_TO_MEM) {
 522                         imx_dmav1_writel(imxdma, imxdmac->per_address,
 523                                          DMA_SAR(imxdmac->channel));
 524                         imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
 525                                          DMA_CCR(imxdmac->channel));
 526
 527                         dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
 528                                 "total length=%d dev_addr=0x%08x (dev2mem)\n",
 529                                 __func__, imxdmac->channel, d->sg, d->sgcount,
 530                                 d->len, imxdmac->per_address);
 531                 } else if (d->direction == DMA_MEM_TO_DEV) {
 532                         imx_dmav1_writel(imxdma, imxdmac->per_address,
 533                                          DMA_DAR(imxdmac->channel));
 534                         imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
 535                                          DMA_CCR(imxdmac->channel));
 536
 537                         dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
 538                                 "total length=%d dev_addr=0x%08x (mem2dev)\n",
 539                                 __func__, imxdmac->channel, d->sg, d->sgcount,
 540                                 d->len, imxdmac->per_address);
 541                 } else {
 542                         dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
 543                                 __func__, imxdmac->channel);
 544                         return -EINVAL;
 545                 }
 546
 547                 imxdma_sg_next(d);
 548
 549                 break;
 550         default:
 551                 return -EINVAL;
 552         }
 553         imxdma_enable_hw(d);
 554         return 0;
 555 }
 556
 557 static void imxdma_tasklet(unsigned long data)
 558 {
 559         struct imxdma_channel *imxdmac = (void *)data;
 560         struct imxdma_engine *imxdma = imxdmac->imxdma;
 561         struct imxdma_desc *desc;
 562
 563         spin_lock(&imxdma->lock);
 564
 565         if (list_empty(&imxdmac->ld_active)) {
 566                 /* Someone might have called terminate all */
 567                 goto out;
 568         }
 569         desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
 570
 571         if (desc->desc.callback)
 572                 desc->desc.callback(desc->desc.callback_param);
 573
 574         /* If we are dealing with a cyclic descriptor keep it on ld_active
 575          * and dont mark the descripor as complete.
 576          * Only in non-cyclic cases it would be marked as complete
 577          */
 578         if (imxdma_chan_is_doing_cyclic(imxdmac))
 579                 goto out;
 580         else
 581                 dma_cookie_complete(&desc->desc);
 582
 583         /* Free 2D slot if it was an interleaved transfer */
 584         if (imxdmac->enabled_2d) {
 585                 imxdma->slots_2d[imxdmac->slot_2d].count--;
 586                 imxdmac->enabled_2d = false;
 587         }
 588
 589         list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
 590
 591         if (!list_empty(&imxdmac->ld_queue)) {
 592                 desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
 593                                         node);
 594                 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
 595                 if (imxdma_xfer_desc(desc) < 0)
 596                         dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
 597                                  __func__, imxdmac->channel);
 598         }
 599 out:
 600         spin_unlock(&imxdma->lock);
 601 }
 602
 603 static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 604                 unsigned long arg)
 605 {
 606         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 607         struct dma_slave_config *dmaengine_cfg = (void *)arg;
 608         struct imxdma_engine *imxdma = imxdmac->imxdma;
 609         unsigned long flags;
 610         unsigned int mode = 0;
 611
 612         switch (cmd) {
 613         case DMA_TERMINATE_ALL:
 614                 imxdma_disable_hw(imxdmac);
 615
 616                 spin_lock_irqsave(&imxdma->lock, flags);
 617                 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 618                 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 619                 spin_unlock_irqrestore(&imxdma->lock, flags);
 620                 return 0;
 621         case DMA_SLAVE_CONFIG:
 622                 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
 623                         imxdmac->per_address = dmaengine_cfg->src_addr;
 624                         imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
 625                         imxdmac->word_size = dmaengine_cfg->src_addr_width;
 626                 } else {
 627                         imxdmac->per_address = dmaengine_cfg->dst_addr;
 628                         imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
 629                         imxdmac->word_size = dmaengine_cfg->dst_addr_width;
 630                 }
 631
 632                 switch (imxdmac->word_size) {
 633                 case DMA_SLAVE_BUSWIDTH_1_BYTE:
 634                         mode = IMX_DMA_MEMSIZE_8;
 635                         break;
 636                 case DMA_SLAVE_BUSWIDTH_2_BYTES:
 637                         mode = IMX_DMA_MEMSIZE_16;
 638                         break;
 639                 default:
 640                 case DMA_SLAVE_BUSWIDTH_4_BYTES:
 641                         mode = IMX_DMA_MEMSIZE_32;
 642                         break;
 643                 }
 644
 645                 imxdmac->hw_chaining = 1;
 646                 if (!imxdma_hw_chain(imxdmac))
 647                         return -EINVAL;
 648                 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
 649                         ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
 650                         CCR_REN;
 651                 imxdmac->ccr_to_device =
 652                         (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
 653                         ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
 654                 imx_dmav1_writel(imxdma, imxdmac->dma_request,
 655                                  DMA_RSSR(imxdmac->channel));
 656
 657                 /* Set burst length */
 658                 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
 659                                 imxdmac->word_size, DMA_BLR(imxdmac->channel));
 660
 661                 return 0;
 662         default:
 663                 return -ENOSYS;
 664         }
 665
 666         return -EINVAL;
 667 }
 668
 669 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
 670                                             dma_cookie_t cookie,
 671                                             struct dma_tx_state *txstate)
 672 {
 673         return dma_cookie_status(chan, cookie, txstate);
 674 }
 675
 676 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
 677 {
 678         struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
 679         struct imxdma_engine *imxdma = imxdmac->imxdma;
 680         dma_cookie_t cookie;
 681         unsigned long flags;
 682
 683         spin_lock_irqsave(&imxdma->lock, flags);
 684         list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
 685         cookie = dma_cookie_assign(tx);
 686         spin_unlock_irqrestore(&imxdma->lock, flags);
 687
 688         return cookie;
 689 }
 690
 691 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
 692 {
 693         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 694         struct imx_dma_data *data = chan->private;
 695
 696         if (data != NULL)
 697                 imxdmac->dma_request = data->dma_request;
 698
 699         while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
 700                 struct imxdma_desc *desc;
 701
 702                 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
 703                 if (!desc)
 704                         break;
 705                 __memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
 706                 dma_async_tx_descriptor_init(&desc->desc, chan);
 707                 desc->desc.tx_submit = imxdma_tx_submit;
 708                 /* txd.flags will be overwritten in prep funcs */
 709                 desc->desc.flags = DMA_CTRL_ACK;
 710                 desc->status = DMA_SUCCESS;
 711
 712                 list_add_tail(&desc->node, &imxdmac->ld_free);
 713                 imxdmac->descs_allocated++;
 714         }
 715
 716         if (!imxdmac->descs_allocated)
 717                 return -ENOMEM;
 718
 719         return imxdmac->descs_allocated;
 720 }
 721
 722 static void imxdma_free_chan_resources(struct dma_chan *chan)
 723 {
 724         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 725         struct imxdma_engine *imxdma = imxdmac->imxdma;
 726         struct imxdma_desc *desc, *_desc;
 727         unsigned long flags;
 728
 729         spin_lock_irqsave(&imxdma->lock, flags);
 730
 731         imxdma_disable_hw(imxdmac);
 732         list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
 733         list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
 734
 735         spin_unlock_irqrestore(&imxdma->lock, flags);
 736
 737         list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
 738                 kfree(desc);
 739                 imxdmac->descs_allocated--;
 740         }
 741         INIT_LIST_HEAD(&imxdmac->ld_free);
 742
 743         if (imxdmac->sg_list) {
 744                 kfree(imxdmac->sg_list);
 745                 imxdmac->sg_list = NULL;
 746         }
 747 }
 748
 749 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
 750                 struct dma_chan *chan, struct scatterlist *sgl,
 751                 unsigned int sg_len, enum dma_transfer_direction direction,
 752                 unsigned long flags, void *context)
 753 {
 754         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 755         struct scatterlist *sg;
 756         int i, dma_length = 0;
 757         struct imxdma_desc *desc;
 758
 759         if (list_empty(&imxdmac->ld_free) ||
 760             imxdma_chan_is_doing_cyclic(imxdmac))
 761                 return NULL;
 762
 763         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 764
 765         for_each_sg(sgl, sg, sg_len, i) {
 766                 dma_length += sg->length;
 767         }
 768
 769         switch (imxdmac->word_size) {
 770         case DMA_SLAVE_BUSWIDTH_4_BYTES:
 771                 if (sgl->length & 3 || sgl->dma_address & 3)
 772                         return NULL;
 773                 break;
 774         case DMA_SLAVE_BUSWIDTH_2_BYTES:
 775                 if (sgl->length & 1 || sgl->dma_address & 1)
 776                         return NULL;
 777                 break;
 778         case DMA_SLAVE_BUSWIDTH_1_BYTE:
 779                 break;
 780         default:
 781                 return NULL;
 782         }
 783
 784         desc->type = IMXDMA_DESC_SLAVE_SG;
 785         desc->sg = sgl;
 786         desc->sgcount = sg_len;
 787         desc->len = dma_length;
 788         desc->direction = direction;
 789         if (direction == DMA_DEV_TO_MEM) {
 790                 desc->src = imxdmac->per_address;
 791         } else {
 792                 desc->dest = imxdmac->per_address;
 793         }
 794         desc->desc.callback = NULL;
 795         desc->desc.callback_param = NULL;
 796
 797         return &desc->desc;
 798 }
 799
 800 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
 801                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 802                 size_t period_len, enum dma_transfer_direction direction,
 803                 void *context)
 804 {
 805         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 806         struct imxdma_engine *imxdma = imxdmac->imxdma;
 807         struct imxdma_desc *desc;
 808         int i;
 809         unsigned int periods = buf_len / period_len;
 810
 811         dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
 812                         __func__, imxdmac->channel, buf_len, period_len);
 813
 814         if (list_empty(&imxdmac->ld_free) ||
 815             imxdma_chan_is_doing_cyclic(imxdmac))
 816                 return NULL;
 817
 818         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 819
 820         if (imxdmac->sg_list)
 821                 kfree(imxdmac->sg_list);
 822
 823         imxdmac->sg_list = kcalloc(periods + 1,
 824                         sizeof(struct scatterlist), GFP_KERNEL);
 825         if (!imxdmac->sg_list)
 826                 return NULL;
 827
 828         sg_init_table(imxdmac->sg_list, periods);
 829
 830         for (i = 0; i < periods; i++) {
 831                 imxdmac->sg_list[i].page_link = 0;
 832                 imxdmac->sg_list[i].offset = 0;
 833                 imxdmac->sg_list[i].dma_address = dma_addr;
 834                 imxdmac->sg_list[i].length = period_len;
 835                 dma_addr += period_len;
 836         }
 837
 838         /* close the loop */
 839         imxdmac->sg_list[periods].offset = 0;
 840         imxdmac->sg_list[periods].length = 0;
 841         imxdmac->sg_list[periods].page_link =
 842                 ((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;
 843
 844         desc->type = IMXDMA_DESC_CYCLIC;
 845         desc->sg = imxdmac->sg_list;
 846         desc->sgcount = periods;
 847         desc->len = IMX_DMA_LENGTH_LOOP;
 848         desc->direction = direction;
 849         if (direction == DMA_DEV_TO_MEM) {
 850                 desc->src = imxdmac->per_address;
 851         } else {
 852                 desc->dest = imxdmac->per_address;
 853         }
 854         desc->desc.callback = NULL;
 855         desc->desc.callback_param = NULL;
 856
 857         return &desc->desc;
 858 }
 859
 860 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
 861         struct dma_chan *chan, dma_addr_t dest,
 862         dma_addr_t src, size_t len, unsigned long flags)
 863 {
 864         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 865         struct imxdma_engine *imxdma = imxdmac->imxdma;
 866         struct imxdma_desc *desc;
 867
 868         dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
 869                         __func__, imxdmac->channel, src, dest, len);
 870
 871         if (list_empty(&imxdmac->ld_free) ||
 872             imxdma_chan_is_doing_cyclic(imxdmac))
 873                 return NULL;
 874
 875         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 876
 877         desc->type = IMXDMA_DESC_MEMCPY;
 878         desc->src = src;
 879         desc->dest = dest;
 880         desc->len = len;
 881         desc->direction = DMA_MEM_TO_MEM;
 882         desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 883         desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
 884         desc->desc.callback = NULL;
 885         desc->desc.callback_param = NULL;
 886
 887         return &desc->desc;
 888 }
 889
 890 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
 891         struct dma_chan *chan, struct dma_interleaved_template *xt,
 892         unsigned long flags)
 893 {
 894         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 895         struct imxdma_engine *imxdma = imxdmac->imxdma;
 896         struct imxdma_desc *desc;
 897
 898         dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
 899                 "   src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
 900                 imxdmac->channel, xt->src_start, xt->dst_start,
 901                 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
 902                 xt->numf, xt->frame_size);
 903
 904         if (list_empty(&imxdmac->ld_free) ||
 905             imxdma_chan_is_doing_cyclic(imxdmac))
 906                 return NULL;
 907
 908         if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
 909                 return NULL;
 910
 911         desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
 912
 913         desc->type = IMXDMA_DESC_INTERLEAVED;
 914         desc->src = xt->src_start;
 915         desc->dest = xt->dst_start;
 916         desc->x = xt->sgl[0].size;
 917         desc->y = xt->numf;
 918         desc->w = xt->sgl[0].icg + desc->x;
 919         desc->len = desc->x * desc->y;
 920         desc->direction = DMA_MEM_TO_MEM;
 921         desc->config_port = IMX_DMA_MEMSIZE_32;
 922         desc->config_mem = IMX_DMA_MEMSIZE_32;
 923         if (xt->src_sgl)
 924                 desc->config_mem |= IMX_DMA_TYPE_2D;
 925         if (xt->dst_sgl)
 926                 desc->config_port |= IMX_DMA_TYPE_2D;
 927         desc->desc.callback = NULL;
 928         desc->desc.callback_param = NULL;
 929
 930         return &desc->desc;
 931 }
 932
 933 static void imxdma_issue_pending(struct dma_chan *chan)
 934 {
 935         struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
 936         struct imxdma_engine *imxdma = imxdmac->imxdma;
 937         struct imxdma_desc *desc;
 938         unsigned long flags;
 939
 940         spin_lock_irqsave(&imxdma->lock, flags);
 941         if (list_empty(&imxdmac->ld_active) &&
 942             !list_empty(&imxdmac->ld_queue)) {
 943                 desc = list_first_entry(&imxdmac->ld_queue,
 944                                         struct imxdma_desc, node);
 945
 946                 if (imxdma_xfer_desc(desc) < 0) {
 947                         dev_warn(imxdma->dev,
 948                                  "%s: channel: %d couldn't issue DMA xfer\n",
 949                                  __func__, imxdmac->channel);
 950                 } else {
 951                         list_move_tail(imxdmac->ld_queue.next,
 952                                        &imxdmac->ld_active);
 953                 }
 954         }
 955         spin_unlock_irqrestore(&imxdma->lock, flags);
 956 }
 957
 958 static int __init imxdma_probe(struct platform_device *pdev)
 959         {
 960         struct imxdma_engine *imxdma;
 961         int ret, i;
 962
 963
 964         imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
 965         if (!imxdma)
 966                 return -ENOMEM;
 967
 968         if (cpu_is_mx1()) {
 969                 imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
 970         } else if (cpu_is_mx21()) {
 971                 imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
 972         } else if (cpu_is_mx27()) {
 973                 imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
 974         } else {
 975                 kfree(imxdma);
 976                 return 0;
 977         }
 978
 979         imxdma->dma_clk = clk_get(NULL, "dma");
 980         if (IS_ERR(imxdma->dma_clk))
 981                 return PTR_ERR(imxdma->dma_clk);
 982         clk_enable(imxdma->dma_clk);
 983
 984         /* reset DMA module */
 985         imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
 986
 987         if (cpu_is_mx1()) {
 988                 ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
 989                 if (ret) {
 990                         dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
 991                         kfree(imxdma);
 992                         return ret;
 993                 }
 994
 995                 ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
 996                 if (ret) {
 997                         dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
 998                         free_irq(MX1_DMA_INT, NULL);
 999                         kfree(imxdma);
1000                         return ret;
1001                 }
1002         }
1003
1004         /* enable DMA module */
1005         imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1006
1007         /* clear all interrupts */
1008         imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1009
1010         /* disable interrupts */
1011         imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1012
1013         INIT_LIST_HEAD(&imxdma->dma_device.channels);
1014
1015         dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1016         dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1017         dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1018         dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1019
1020         /* Initialize 2D global parameters */
1021         for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1022                 imxdma->slots_2d[i].count = 0;
1023
1024         spin_lock_init(&imxdma->lock);
1025
1026         /* Initialize channel parameters */
1027         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1028                 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1029
1030                 if (cpu_is_mx21() || cpu_is_mx27()) {
1031                         ret = request_irq(MX2x_INT_DMACH0 + i,
1032                                         dma_irq_handler, 0, "DMA", imxdma);
1033                         if (ret) {
1034                                 dev_warn(imxdma->dev, "Can't register IRQ %d "
1035                                          "for DMA channel %d\n",
1036                                          MX2x_INT_DMACH0 + i, i);
1037                                 goto err_init;
1038                         }
1039                         init_timer(&imxdmac->watchdog);
1040                         imxdmac->watchdog.function = &imxdma_watchdog;
1041                         imxdmac->watchdog.data = (unsigned long)imxdmac;
1042                 }
1043
1044                 imxdmac->imxdma = imxdma;
1045
1046                 INIT_LIST_HEAD(&imxdmac->ld_queue);
1047                 INIT_LIST_HEAD(&imxdmac->ld_free);
1048                 INIT_LIST_HEAD(&imxdmac->ld_active);
1049
1050                 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1051                              (unsigned long)imxdmac);
1052                 imxdmac->chan.device = &imxdma->dma_device;
1053                 dma_cookie_init(&imxdmac->chan);
1054                 imxdmac->channel = i;
1055
1056                 /* Add the channel to the DMAC list */
1057                 list_add_tail(&imxdmac->chan.device_node,
1058                               &imxdma->dma_device.channels);
1059         }
1060
1061         imxdma->dev = &pdev->dev;
1062         imxdma->dma_device.dev = &pdev->dev;
1063
1064         imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1065         imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1066         imxdma->dma_device.device_tx_status = imxdma_tx_status;
1067         imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1068         imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1069         imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1070         imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1071         imxdma->dma_device.device_control = imxdma_control;
1072         imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1073
1074         platform_set_drvdata(pdev, imxdma);
1075
1076         imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
1077         imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1078         dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1079
1080         ret = dma_async_device_register(&imxdma->dma_device);
1081         if (ret) {
1082                 dev_err(&pdev->dev, "unable to register\n");
1083                 goto err_init;
1084         }
1085
1086         return 0;
1087
1088 err_init:
1089
1090         if (cpu_is_mx21() || cpu_is_mx27()) {
1091                 while (--i >= 0)
1092                         free_irq(MX2x_INT_DMACH0 + i, NULL);
1093         } else if cpu_is_mx1() {
1094                 free_irq(MX1_DMA_INT, NULL);
1095                 free_irq(MX1_DMA_ERR, NULL);
1096         }
1097
1098         kfree(imxdma);
1099         return ret;
1100 }
1101
1102 static int __exit imxdma_remove(struct platform_device *pdev)
1103 {
1104         struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1105         int i;
1106
1107         dma_async_device_unregister(&imxdma->dma_device);
1108
1109         if (cpu_is_mx21() || cpu_is_mx27()) {
1110                 for (i = 0; i < IMX_DMA_CHANNELS; i++)
1111                         free_irq(MX2x_INT_DMACH0 + i, NULL);
1112         } else if cpu_is_mx1() {
1113                 free_irq(MX1_DMA_INT, NULL);
1114                 free_irq(MX1_DMA_ERR, NULL);
1115         }
1116
1117         kfree(imxdma);
1118
1119         return 0;
1120 }
1121
1122 static struct platform_driver imxdma_driver = {
1123         .driver         = {
1124                 .name   = "imx-dma",
1125         },
1126         .remove         = __exit_p(imxdma_remove),
1127 };
1128
1129 static int __init imxdma_module_init(void)
1130 {
1131         return platform_driver_probe(&imxdma_driver, imxdma_probe);
1132 }
1133 subsys_initcall(imxdma_module_init);
1134
1135 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1136 MODULE_DESCRIPTION("i.MX dma driver");
1137 MODULE_LICENSE("GPL");