drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/delay.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/err.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/mm.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has been tested with the Atmel AT32AP7000, which does not
  37  * support descriptor writeback.
  38  */
  39
  40 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  41                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  42                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  43                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  44                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  45                         DW_DMA_MSIZE_16;                        \
  46                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  47                         DW_DMA_MSIZE_16;                        \
  48                                                                 \
  49                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  50                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  51                  | DWC_CTLL_LLP_D_EN                            \
  52                  | DWC_CTLL_LLP_S_EN                            \
  53                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  54                  | DWC_CTLL_SMS(_dwc->src_master));             \
  55         })
  56
  57 /*
  58  * Number of descriptors to allocate for each channel. This should be
  59  * made configurable somehow; preferably, the clients (at least the
  60  * ones using slave transfers) should be able to give us a hint.
  61  */
  62 #define NR_DESCS_PER_CHANNEL    64
  63
  64 /* The set of bus widths supported by the DMA controller */
  65 #define DW_DMA_BUSWIDTHS                          \
  66         BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
  67         BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)          | \
  68         BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)         | \
  69         BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
  70
  71 /*----------------------------------------------------------------------*/
  72
  73 static struct device *chan2dev(struct dma_chan *chan)
  74 {
  75         return &chan->dev->device;
  76 }
  77
  78 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  79 {
  80         return to_dw_desc(dwc->active_list.next);
  81 }
  82
  83 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  84 {
  85         struct dw_desc *desc, *_desc;
  86         struct dw_desc *ret = NULL;
  87         unsigned int i = 0;
  88         unsigned long flags;
  89
  90         spin_lock_irqsave(&dwc->lock, flags);
  91         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
  92                 i++;
  93                 if (async_tx_test_ack(&desc->txd)) {
  94                         list_del(&desc->desc_node);
  95                         ret = desc;
  96                         break;
  97                 }
  98                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
  99         }
 100         spin_unlock_irqrestore(&dwc->lock, flags);
 101
 102         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 103
 104         return ret;
 105 }
 106
 107 /*
 108  * Move a descriptor, including any children, to the free list.
 109  * `desc' must not be on any lists.
 110  */
 111 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 112 {
 113         unsigned long flags;
 114
 115         if (desc) {
 116                 struct dw_desc *child;
 117
 118                 spin_lock_irqsave(&dwc->lock, flags);
 119                 list_for_each_entry(child, &desc->tx_list, desc_node)
 120                         dev_vdbg(chan2dev(&dwc->chan),
 121                                         "moving child desc %p to freelist\n",
 122                                         child);
 123                 list_splice_init(&desc->tx_list, &dwc->free_list);
 124                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 125                 list_add(&desc->desc_node, &dwc->free_list);
 126                 spin_unlock_irqrestore(&dwc->lock, flags);
 127         }
 128 }
 129
 130 static void dwc_initialize(struct dw_dma_chan *dwc)
 131 {
 132         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 133         struct dw_dma_slave *dws = dwc->chan.private;
 134         u32 cfghi = DWC_CFGH_FIFO_MODE;
 135         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 136
 137         if (dwc->initialized == true)
 138                 return;
 139
 140         if (dws) {
 141                 /*
 142                  * We need controller-specific data to set up slave
 143                  * transfers.
 144                  */
 145                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 146
 147                 cfghi |= DWC_CFGH_DST_PER(dws->dst_id);
 148                 cfghi |= DWC_CFGH_SRC_PER(dws->src_id);
 149         } else {
 150                 cfghi |= DWC_CFGH_DST_PER(dwc->dst_id);
 151                 cfghi |= DWC_CFGH_SRC_PER(dwc->src_id);
 152         }
 153
 154         channel_writel(dwc, CFG_LO, cfglo);
 155         channel_writel(dwc, CFG_HI, cfghi);
 156
 157         /* Enable interrupts */
 158         channel_set_bit(dw, MASK.XFER, dwc->mask);
 159         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
 160         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 161
 162         dwc->initialized = true;
 163 }
 164
 165 /*----------------------------------------------------------------------*/
 166
 167 static inline unsigned int dwc_fast_ffs(unsigned long long v)
 168 {
 169         /*
 170          * We can be a lot more clever here, but this should take care
 171          * of the most common optimization.
 172          */
 173         if (!(v & 7))
 174                 return 3;
 175         else if (!(v & 3))
 176                 return 2;
 177         else if (!(v & 1))
 178                 return 1;
 179         return 0;
 180 }
 181
 182 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 183 {
 184         dev_err(chan2dev(&dwc->chan),
 185                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 186                 channel_readl(dwc, SAR),
 187                 channel_readl(dwc, DAR),
 188                 channel_readl(dwc, LLP),
 189                 channel_readl(dwc, CTL_HI),
 190                 channel_readl(dwc, CTL_LO));
 191 }
 192
 193 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 194 {
 195         channel_clear_bit(dw, CH_EN, dwc->mask);
 196         while (dma_readl(dw, CH_EN) & dwc->mask)
 197                 cpu_relax();
 198 }
 199
 200 /*----------------------------------------------------------------------*/
 201
 202 /* Perform single block transfer */
 203 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 204                                        struct dw_desc *desc)
 205 {
 206         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 207         u32             ctllo;
 208
 209         /*
 210          * Software emulation of LLP mode relies on interrupts to continue
 211          * multi block transfer.
 212          */
 213         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 214
 215         channel_writel(dwc, SAR, desc->lli.sar);
 216         channel_writel(dwc, DAR, desc->lli.dar);
 217         channel_writel(dwc, CTL_LO, ctllo);
 218         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 219         channel_set_bit(dw, CH_EN, dwc->mask);
 220
 221         /* Move pointer to next descriptor */
 222         dwc->tx_node_active = dwc->tx_node_active->next;
 223 }
 224
 225 /* Called with dwc->lock held and bh disabled */
 226 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 227 {
 228         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 229         unsigned long   was_soft_llp;
 230
 231         /* ASSERT:  channel is idle */
 232         if (dma_readl(dw, CH_EN) & dwc->mask) {
 233                 dev_err(chan2dev(&dwc->chan),
 234                         "%s: BUG: Attempted to start non-idle channel\n",
 235                         __func__);
 236                 dwc_dump_chan_regs(dwc);
 237
 238                 /* The tasklet will hopefully advance the queue... */
 239                 return;
 240         }
 241
 242         if (dwc->nollp) {
 243                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 244                                                 &dwc->flags);
 245                 if (was_soft_llp) {
 246                         dev_err(chan2dev(&dwc->chan),
 247                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 248                         return;
 249                 }
 250
 251                 dwc_initialize(dwc);
 252
 253                 dwc->residue = first->total_len;
 254                 dwc->tx_node_active = &first->tx_list;
 255
 256                 /* Submit first block */
 257                 dwc_do_single_block(dwc, first);
 258
 259                 return;
 260         }
 261
 262         dwc_initialize(dwc);
 263
 264         channel_writel(dwc, LLP, first->txd.phys);
 265         channel_writel(dwc, CTL_LO,
 266                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 267         channel_writel(dwc, CTL_HI, 0);
 268         channel_set_bit(dw, CH_EN, dwc->mask);
 269 }
 270
 271 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc)
 272 {
 273         struct dw_desc *desc;
 274
 275         if (list_empty(&dwc->queue))
 276                 return;
 277
 278         list_move(dwc->queue.next, &dwc->active_list);
 279         desc = dwc_first_active(dwc);
 280         dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie);
 281         dwc_dostart(dwc, desc);
 282 }
 283
 284 /*----------------------------------------------------------------------*/
 285
 286 static void
 287 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 288                 bool callback_required)
 289 {
 290         dma_async_tx_callback           callback = NULL;
 291         void                            *param = NULL;
 292         struct dma_async_tx_descriptor  *txd = &desc->txd;
 293         struct dw_desc                  *child;
 294         unsigned long                   flags;
 295
 296         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 297
 298         spin_lock_irqsave(&dwc->lock, flags);
 299         dma_cookie_complete(txd);
 300         if (callback_required) {
 301                 callback = txd->callback;
 302                 param = txd->callback_param;
 303         }
 304
 305         /* async_tx_ack */
 306         list_for_each_entry(child, &desc->tx_list, desc_node)
 307                 async_tx_ack(&child->txd);
 308         async_tx_ack(&desc->txd);
 309
 310         list_splice_init(&desc->tx_list, &dwc->free_list);
 311         list_move(&desc->desc_node, &dwc->free_list);
 312
 313         dma_descriptor_unmap(txd);
 314         spin_unlock_irqrestore(&dwc->lock, flags);
 315
 316         if (callback)
 317                 callback(param);
 318 }
 319
 320 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 321 {
 322         struct dw_desc *desc, *_desc;
 323         LIST_HEAD(list);
 324         unsigned long flags;
 325
 326         spin_lock_irqsave(&dwc->lock, flags);
 327         if (dma_readl(dw, CH_EN) & dwc->mask) {
 328                 dev_err(chan2dev(&dwc->chan),
 329                         "BUG: XFER bit set, but channel not idle!\n");
 330
 331                 /* Try to continue after resetting the channel... */
 332                 dwc_chan_disable(dw, dwc);
 333         }
 334
 335         /*
 336          * Submit queued descriptors ASAP, i.e. before we go through
 337          * the completed ones.
 338          */
 339         list_splice_init(&dwc->active_list, &list);
 340         dwc_dostart_first_queued(dwc);
 341
 342         spin_unlock_irqrestore(&dwc->lock, flags);
 343
 344         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 345                 dwc_descriptor_complete(dwc, desc, true);
 346 }
 347
 348 /* Returns how many bytes were already received from source */
 349 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 350 {
 351         u32 ctlhi = channel_readl(dwc, CTL_HI);
 352         u32 ctllo = channel_readl(dwc, CTL_LO);
 353
 354         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 355 }
 356
 357 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 358 {
 359         dma_addr_t llp;
 360         struct dw_desc *desc, *_desc;
 361         struct dw_desc *child;
 362         u32 status_xfer;
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&dwc->lock, flags);
 366         llp = channel_readl(dwc, LLP);
 367         status_xfer = dma_readl(dw, RAW.XFER);
 368
 369         if (status_xfer & dwc->mask) {
 370                 /* Everything we've submitted is done */
 371                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 372
 373                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 374                         struct list_head *head, *active = dwc->tx_node_active;
 375
 376                         /*
 377                          * We are inside first active descriptor.
 378                          * Otherwise something is really wrong.
 379                          */
 380                         desc = dwc_first_active(dwc);
 381
 382                         head = &desc->tx_list;
 383                         if (active != head) {
 384                                 /* Update desc to reflect last sent one */
 385                                 if (active != head->next)
 386                                         desc = to_dw_desc(active->prev);
 387
 388                                 dwc->residue -= desc->len;
 389
 390                                 child = to_dw_desc(active);
 391
 392                                 /* Submit next block */
 393                                 dwc_do_single_block(dwc, child);
 394
 395                                 spin_unlock_irqrestore(&dwc->lock, flags);
 396                                 return;
 397                         }
 398
 399                         /* We are done here */
 400                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 401                 }
 402
 403                 dwc->residue = 0;
 404
 405                 spin_unlock_irqrestore(&dwc->lock, flags);
 406
 407                 dwc_complete_all(dw, dwc);
 408                 return;
 409         }
 410
 411         if (list_empty(&dwc->active_list)) {
 412                 dwc->residue = 0;
 413                 spin_unlock_irqrestore(&dwc->lock, flags);
 414                 return;
 415         }
 416
 417         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 418                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 419                 spin_unlock_irqrestore(&dwc->lock, flags);
 420                 return;
 421         }
 422
 423         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 424
 425         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 426                 /* Initial residue value */
 427                 dwc->residue = desc->total_len;
 428
 429                 /* Check first descriptors addr */
 430                 if (desc->txd.phys == llp) {
 431                         spin_unlock_irqrestore(&dwc->lock, flags);
 432                         return;
 433                 }
 434
 435                 /* Check first descriptors llp */
 436                 if (desc->lli.llp == llp) {
 437                         /* This one is currently in progress */
 438                         dwc->residue -= dwc_get_sent(dwc);
 439                         spin_unlock_irqrestore(&dwc->lock, flags);
 440                         return;
 441                 }
 442
 443                 dwc->residue -= desc->len;
 444                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 445                         if (child->lli.llp == llp) {
 446                                 /* Currently in progress */
 447                                 dwc->residue -= dwc_get_sent(dwc);
 448                                 spin_unlock_irqrestore(&dwc->lock, flags);
 449                                 return;
 450                         }
 451                         dwc->residue -= child->len;
 452                 }
 453
 454                 /*
 455                  * No descriptors so far seem to be in progress, i.e.
 456                  * this one must be done.
 457                  */
 458                 spin_unlock_irqrestore(&dwc->lock, flags);
 459                 dwc_descriptor_complete(dwc, desc, true);
 460                 spin_lock_irqsave(&dwc->lock, flags);
 461         }
 462
 463         dev_err(chan2dev(&dwc->chan),
 464                 "BUG: All descriptors done, but channel not idle!\n");
 465
 466         /* Try to continue after resetting the channel... */
 467         dwc_chan_disable(dw, dwc);
 468
 469         dwc_dostart_first_queued(dwc);
 470         spin_unlock_irqrestore(&dwc->lock, flags);
 471 }
 472
 473 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 474 {
 475         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 476                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 477 }
 478
 479 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 480 {
 481         struct dw_desc *bad_desc;
 482         struct dw_desc *child;
 483         unsigned long flags;
 484
 485         dwc_scan_descriptors(dw, dwc);
 486
 487         spin_lock_irqsave(&dwc->lock, flags);
 488
 489         /*
 490          * The descriptor currently at the head of the active list is
 491          * borked. Since we don't have any way to report errors, we'll
 492          * just have to scream loudly and try to carry on.
 493          */
 494         bad_desc = dwc_first_active(dwc);
 495         list_del_init(&bad_desc->desc_node);
 496         list_move(dwc->queue.next, dwc->active_list.prev);
 497
 498         /* Clear the error flag and try to restart the controller */
 499         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 500         if (!list_empty(&dwc->active_list))
 501                 dwc_dostart(dwc, dwc_first_active(dwc));
 502
 503         /*
 504          * WARN may seem harsh, but since this only happens
 505          * when someone submits a bad physical address in a
 506          * descriptor, we should consider ourselves lucky that the
 507          * controller flagged an error instead of scribbling over
 508          * random memory locations.
 509          */
 510         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 511                                        "  cookie: %d\n", bad_desc->txd.cookie);
 512         dwc_dump_lli(dwc, &bad_desc->lli);
 513         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 514                 dwc_dump_lli(dwc, &child->lli);
 515
 516         spin_unlock_irqrestore(&dwc->lock, flags);
 517
 518         /* Pretend the descriptor completed successfully */
 519         dwc_descriptor_complete(dwc, bad_desc, true);
 520 }
 521
 522 /* --------------------- Cyclic DMA API extensions -------------------- */
 523
 524 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 525 {
 526         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 527         return channel_readl(dwc, SAR);
 528 }
 529 EXPORT_SYMBOL(dw_dma_get_src_addr);
 530
 531 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 532 {
 533         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 534         return channel_readl(dwc, DAR);
 535 }
 536 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 537
 538 /* Called with dwc->lock held and all DMAC interrupts disabled */
 539 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 540                 u32 status_block, u32 status_err, u32 status_xfer)
 541 {
 542         unsigned long flags;
 543
 544         if (status_block & dwc->mask) {
 545                 void (*callback)(void *param);
 546                 void *callback_param;
 547
 548                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 549                                 channel_readl(dwc, LLP));
 550                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 551
 552                 callback = dwc->cdesc->period_callback;
 553                 callback_param = dwc->cdesc->period_callback_param;
 554
 555                 if (callback)
 556                         callback(callback_param);
 557         }
 558
 559         /*
 560          * Error and transfer complete are highly unlikely, and will most
 561          * likely be due to a configuration error by the user.
 562          */
 563         if (unlikely(status_err & dwc->mask) ||
 564                         unlikely(status_xfer & dwc->mask)) {
 565                 int i;
 566
 567                 dev_err(chan2dev(&dwc->chan),
 568                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 569                         status_xfer ? "xfer" : "error");
 570
 571                 spin_lock_irqsave(&dwc->lock, flags);
 572
 573                 dwc_dump_chan_regs(dwc);
 574
 575                 dwc_chan_disable(dw, dwc);
 576
 577                 /* Make sure DMA does not restart by loading a new list */
 578                 channel_writel(dwc, LLP, 0);
 579                 channel_writel(dwc, CTL_LO, 0);
 580                 channel_writel(dwc, CTL_HI, 0);
 581
 582                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 583                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 584                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 585
 586                 for (i = 0; i < dwc->cdesc->periods; i++)
 587                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 588
 589                 spin_unlock_irqrestore(&dwc->lock, flags);
 590         }
 591 }
 592
 593 /* ------------------------------------------------------------------------- */
 594
 595 static void dw_dma_tasklet(unsigned long data)
 596 {
 597         struct dw_dma *dw = (struct dw_dma *)data;
 598         struct dw_dma_chan *dwc;
 599         u32 status_block;
 600         u32 status_xfer;
 601         u32 status_err;
 602         int i;
 603
 604         status_block = dma_readl(dw, RAW.BLOCK);
 605         status_xfer = dma_readl(dw, RAW.XFER);
 606         status_err = dma_readl(dw, RAW.ERROR);
 607
 608         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 609
 610         for (i = 0; i < dw->dma.chancnt; i++) {
 611                 dwc = &dw->chan[i];
 612                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 613                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 614                                         status_xfer);
 615                 else if (status_err & (1 << i))
 616                         dwc_handle_error(dw, dwc);
 617                 else if (status_xfer & (1 << i))
 618                         dwc_scan_descriptors(dw, dwc);
 619         }
 620
 621         /*
 622          * Re-enable interrupts.
 623          */
 624         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 625         channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 626         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 627 }
 628
 629 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 630 {
 631         struct dw_dma *dw = dev_id;
 632         u32 status = dma_readl(dw, STATUS_INT);
 633
 634         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 635
 636         /* Check if we have any interrupt from the DMAC */
 637         if (!status || !dw->in_use)
 638                 return IRQ_NONE;
 639
 640         /*
 641          * Just disable the interrupts. We'll turn them back on in the
 642          * softirq handler.
 643          */
 644         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 645         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 646         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 647
 648         status = dma_readl(dw, STATUS_INT);
 649         if (status) {
 650                 dev_err(dw->dma.dev,
 651                         "BUG: Unexpected interrupts pending: 0x%x\n",
 652                         status);
 653
 654                 /* Try to recover */
 655                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 656                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 657                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 658                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 659                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 660         }
 661
 662         tasklet_schedule(&dw->tasklet);
 663
 664         return IRQ_HANDLED;
 665 }
 666
 667 /*----------------------------------------------------------------------*/
 668
 669 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 670 {
 671         struct dw_desc          *desc = txd_to_dw_desc(tx);
 672         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 673         dma_cookie_t            cookie;
 674         unsigned long           flags;
 675
 676         spin_lock_irqsave(&dwc->lock, flags);
 677         cookie = dma_cookie_assign(tx);
 678
 679         /*
 680          * REVISIT: We should attempt to chain as many descriptors as
 681          * possible, perhaps even appending to those already submitted
 682          * for DMA. But this is hard to do in a race-free manner.
 683          */
 684
 685         dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, desc->txd.cookie);
 686         list_add_tail(&desc->desc_node, &dwc->queue);
 687
 688         spin_unlock_irqrestore(&dwc->lock, flags);
 689
 690         return cookie;
 691 }
 692
 693 static struct dma_async_tx_descriptor *
 694 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 695                 size_t len, unsigned long flags)
 696 {
 697         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 698         struct dw_dma           *dw = to_dw_dma(chan->device);
 699         struct dw_desc          *desc;
 700         struct dw_desc          *first;
 701         struct dw_desc          *prev;
 702         size_t                  xfer_count;
 703         size_t                  offset;
 704         unsigned int            src_width;
 705         unsigned int            dst_width;
 706         unsigned int            data_width;
 707         u32                     ctllo;
 708
 709         dev_vdbg(chan2dev(chan),
 710                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 711                         &dest, &src, len, flags);
 712
 713         if (unlikely(!len)) {
 714                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 715                 return NULL;
 716         }
 717
 718         dwc->direction = DMA_MEM_TO_MEM;
 719
 720         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 721                            dw->data_width[dwc->dst_master]);
 722
 723         src_width = dst_width = min_t(unsigned int, data_width,
 724                                       dwc_fast_ffs(src | dest | len));
 725
 726         ctllo = DWC_DEFAULT_CTLLO(chan)
 727                         | DWC_CTLL_DST_WIDTH(dst_width)
 728                         | DWC_CTLL_SRC_WIDTH(src_width)
 729                         | DWC_CTLL_DST_INC
 730                         | DWC_CTLL_SRC_INC
 731                         | DWC_CTLL_FC_M2M;
 732         prev = first = NULL;
 733
 734         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 735                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 736                                            dwc->block_size);
 737
 738                 desc = dwc_desc_get(dwc);
 739                 if (!desc)
 740                         goto err_desc_get;
 741
 742                 desc->lli.sar = src + offset;
 743                 desc->lli.dar = dest + offset;
 744                 desc->lli.ctllo = ctllo;
 745                 desc->lli.ctlhi = xfer_count;
 746                 desc->len = xfer_count << src_width;
 747
 748                 if (!first) {
 749                         first = desc;
 750                 } else {
 751                         prev->lli.llp = desc->txd.phys;
 752                         list_add_tail(&desc->desc_node,
 753                                         &first->tx_list);
 754                 }
 755                 prev = desc;
 756         }
 757
 758         if (flags & DMA_PREP_INTERRUPT)
 759                 /* Trigger interrupt after last block */
 760                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 761
 762         prev->lli.llp = 0;
 763         first->txd.flags = flags;
 764         first->total_len = len;
 765
 766         return &first->txd;
 767
 768 err_desc_get:
 769         dwc_desc_put(dwc, first);
 770         return NULL;
 771 }
 772
 773 static struct dma_async_tx_descriptor *
 774 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 775                 unsigned int sg_len, enum dma_transfer_direction direction,
 776                 unsigned long flags, void *context)
 777 {
 778         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 779         struct dw_dma           *dw = to_dw_dma(chan->device);
 780         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 781         struct dw_desc          *prev;
 782         struct dw_desc          *first;
 783         u32                     ctllo;
 784         dma_addr_t              reg;
 785         unsigned int            reg_width;
 786         unsigned int            mem_width;
 787         unsigned int            data_width;
 788         unsigned int            i;
 789         struct scatterlist      *sg;
 790         size_t                  total_len = 0;
 791
 792         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 793
 794         if (unlikely(!is_slave_direction(direction) || !sg_len))
 795                 return NULL;
 796
 797         dwc->direction = direction;
 798
 799         prev = first = NULL;
 800
 801         switch (direction) {
 802         case DMA_MEM_TO_DEV:
 803                 reg_width = __ffs(sconfig->dst_addr_width);
 804                 reg = sconfig->dst_addr;
 805                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 806                                 | DWC_CTLL_DST_WIDTH(reg_width)
 807                                 | DWC_CTLL_DST_FIX
 808                                 | DWC_CTLL_SRC_INC);
 809
 810                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 811                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 812
 813                 data_width = dw->data_width[dwc->src_master];
 814
 815                 for_each_sg(sgl, sg, sg_len, i) {
 816                         struct dw_desc  *desc;
 817                         u32             len, dlen, mem;
 818
 819                         mem = sg_dma_address(sg);
 820                         len = sg_dma_len(sg);
 821
 822                         mem_width = min_t(unsigned int,
 823                                           data_width, dwc_fast_ffs(mem | len));
 824
 825 slave_sg_todev_fill_desc:
 826                         desc = dwc_desc_get(dwc);
 827                         if (!desc)
 828                                 goto err_desc_get;
 829
 830                         desc->lli.sar = mem;
 831                         desc->lli.dar = reg;
 832                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 833                         if ((len >> mem_width) > dwc->block_size) {
 834                                 dlen = dwc->block_size << mem_width;
 835                                 mem += dlen;
 836                                 len -= dlen;
 837                         } else {
 838                                 dlen = len;
 839                                 len = 0;
 840                         }
 841
 842                         desc->lli.ctlhi = dlen >> mem_width;
 843                         desc->len = dlen;
 844
 845                         if (!first) {
 846                                 first = desc;
 847                         } else {
 848                                 prev->lli.llp = desc->txd.phys;
 849                                 list_add_tail(&desc->desc_node,
 850                                                 &first->tx_list);
 851                         }
 852                         prev = desc;
 853                         total_len += dlen;
 854
 855                         if (len)
 856                                 goto slave_sg_todev_fill_desc;
 857                 }
 858                 break;
 859         case DMA_DEV_TO_MEM:
 860                 reg_width = __ffs(sconfig->src_addr_width);
 861                 reg = sconfig->src_addr;
 862                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 863                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 864                                 | DWC_CTLL_DST_INC
 865                                 | DWC_CTLL_SRC_FIX);
 866
 867                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 868                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 869
 870                 data_width = dw->data_width[dwc->dst_master];
 871
 872                 for_each_sg(sgl, sg, sg_len, i) {
 873                         struct dw_desc  *desc;
 874                         u32             len, dlen, mem;
 875
 876                         mem = sg_dma_address(sg);
 877                         len = sg_dma_len(sg);
 878
 879                         mem_width = min_t(unsigned int,
 880                                           data_width, dwc_fast_ffs(mem | len));
 881
 882 slave_sg_fromdev_fill_desc:
 883                         desc = dwc_desc_get(dwc);
 884                         if (!desc)
 885                                 goto err_desc_get;
 886
 887                         desc->lli.sar = reg;
 888                         desc->lli.dar = mem;
 889                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 890                         if ((len >> reg_width) > dwc->block_size) {
 891                                 dlen = dwc->block_size << reg_width;
 892                                 mem += dlen;
 893                                 len -= dlen;
 894                         } else {
 895                                 dlen = len;
 896                                 len = 0;
 897                         }
 898                         desc->lli.ctlhi = dlen >> reg_width;
 899                         desc->len = dlen;
 900
 901                         if (!first) {
 902                                 first = desc;
 903                         } else {
 904                                 prev->lli.llp = desc->txd.phys;
 905                                 list_add_tail(&desc->desc_node,
 906                                                 &first->tx_list);
 907                         }
 908                         prev = desc;
 909                         total_len += dlen;
 910
 911                         if (len)
 912                                 goto slave_sg_fromdev_fill_desc;
 913                 }
 914                 break;
 915         default:
 916                 return NULL;
 917         }
 918
 919         if (flags & DMA_PREP_INTERRUPT)
 920                 /* Trigger interrupt after last block */
 921                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 922
 923         prev->lli.llp = 0;
 924         first->total_len = total_len;
 925
 926         return &first->txd;
 927
 928 err_desc_get:
 929         dev_err(chan2dev(chan),
 930                 "not enough descriptors available. Direction %d\n", direction);
 931         dwc_desc_put(dwc, first);
 932         return NULL;
 933 }
 934
 935 bool dw_dma_filter(struct dma_chan *chan, void *param)
 936 {
 937         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 938         struct dw_dma_slave *dws = param;
 939
 940         if (!dws || dws->dma_dev != chan->device->dev)
 941                 return false;
 942
 943         /* We have to copy data since dws can be temporary storage */
 944
 945         dwc->src_id = dws->src_id;
 946         dwc->dst_id = dws->dst_id;
 947
 948         dwc->src_master = dws->src_master;
 949         dwc->dst_master = dws->dst_master;
 950
 951         return true;
 952 }
 953 EXPORT_SYMBOL_GPL(dw_dma_filter);
 954
 955 /*
 956  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 957  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 958  *
 959  * NOTE: burst size 2 is not supported by controller.
 960  *
 961  * This can be done by finding least significant bit set: n & (n - 1)
 962  */
 963 static inline void convert_burst(u32 *maxburst)
 964 {
 965         if (*maxburst > 1)
 966                 *maxburst = fls(*maxburst) - 2;
 967         else
 968                 *maxburst = 0;
 969 }
 970
 971 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 972 {
 973         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 974
 975         /* Check if chan will be configured for slave transfers */
 976         if (!is_slave_direction(sconfig->direction))
 977                 return -EINVAL;
 978
 979         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 980         dwc->direction = sconfig->direction;
 981
 982         convert_burst(&dwc->dma_sconfig.src_maxburst);
 983         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 984
 985         return 0;
 986 }
 987
 988 static int dwc_pause(struct dma_chan *chan)
 989 {
 990         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 991         unsigned long           flags;
 992         unsigned int            count = 20;     /* timeout iterations */
 993         u32                     cfglo;
 994
 995         spin_lock_irqsave(&dwc->lock, flags);
 996
 997         cfglo = channel_readl(dwc, CFG_LO);
 998         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 999         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
1000                 udelay(2);
1001
1002         dwc->paused = true;
1003
1004         spin_unlock_irqrestore(&dwc->lock, flags);
1005
1006         return 0;
1007 }
1008
1009 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
1010 {
1011         u32 cfglo = channel_readl(dwc, CFG_LO);
1012
1013         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
1014
1015         dwc->paused = false;
1016 }
1017
1018 static int dwc_resume(struct dma_chan *chan)
1019 {
1020         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1021         unsigned long           flags;
1022
1023         if (!dwc->paused)
1024                 return 0;
1025
1026         spin_lock_irqsave(&dwc->lock, flags);
1027
1028         dwc_chan_resume(dwc);
1029
1030         spin_unlock_irqrestore(&dwc->lock, flags);
1031
1032         return 0;
1033 }
1034
1035 static int dwc_terminate_all(struct dma_chan *chan)
1036 {
1037         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1038         struct dw_dma           *dw = to_dw_dma(chan->device);
1039         struct dw_desc          *desc, *_desc;
1040         unsigned long           flags;
1041         LIST_HEAD(list);
1042
1043         spin_lock_irqsave(&dwc->lock, flags);
1044
1045         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1046
1047         dwc_chan_disable(dw, dwc);
1048
1049         dwc_chan_resume(dwc);
1050
1051         /* active_list entries will end up before queued entries */
1052         list_splice_init(&dwc->queue, &list);
1053         list_splice_init(&dwc->active_list, &list);
1054
1055         spin_unlock_irqrestore(&dwc->lock, flags);
1056
1057         /* Flush all pending and queued descriptors */
1058         list_for_each_entry_safe(desc, _desc, &list, desc_node)
1059                 dwc_descriptor_complete(dwc, desc, false);
1060
1061         return 0;
1062 }
1063
1064 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1065 {
1066         unsigned long flags;
1067         u32 residue;
1068
1069         spin_lock_irqsave(&dwc->lock, flags);
1070
1071         residue = dwc->residue;
1072         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1073                 residue -= dwc_get_sent(dwc);
1074
1075         spin_unlock_irqrestore(&dwc->lock, flags);
1076         return residue;
1077 }
1078
1079 static enum dma_status
1080 dwc_tx_status(struct dma_chan *chan,
1081               dma_cookie_t cookie,
1082               struct dma_tx_state *txstate)
1083 {
1084         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1085         enum dma_status         ret;
1086
1087         ret = dma_cookie_status(chan, cookie, txstate);
1088         if (ret == DMA_COMPLETE)
1089                 return ret;
1090
1091         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1092
1093         ret = dma_cookie_status(chan, cookie, txstate);
1094         if (ret != DMA_COMPLETE)
1095                 dma_set_residue(txstate, dwc_get_residue(dwc));
1096
1097         if (dwc->paused && ret == DMA_IN_PROGRESS)
1098                 return DMA_PAUSED;
1099
1100         return ret;
1101 }
1102
1103 static void dwc_issue_pending(struct dma_chan *chan)
1104 {
1105         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1106         unsigned long           flags;
1107
1108         spin_lock_irqsave(&dwc->lock, flags);
1109         if (list_empty(&dwc->active_list))
1110                 dwc_dostart_first_queued(dwc);
1111         spin_unlock_irqrestore(&dwc->lock, flags);
1112 }
1113
1114 /*----------------------------------------------------------------------*/
1115
1116 static void dw_dma_off(struct dw_dma *dw)
1117 {
1118         int i;
1119
1120         dma_writel(dw, CFG, 0);
1121
1122         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1123         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1124         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1125         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1126         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1127
1128         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1129                 cpu_relax();
1130
1131         for (i = 0; i < dw->dma.chancnt; i++)
1132                 dw->chan[i].initialized = false;
1133 }
1134
1135 static void dw_dma_on(struct dw_dma *dw)
1136 {
1137         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1138 }
1139
1140 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1141 {
1142         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1143         struct dw_dma           *dw = to_dw_dma(chan->device);
1144         struct dw_desc          *desc;
1145         int                     i;
1146         unsigned long           flags;
1147
1148         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1149
1150         /* ASSERT:  channel is idle */
1151         if (dma_readl(dw, CH_EN) & dwc->mask) {
1152                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1153                 return -EIO;
1154         }
1155
1156         dma_cookie_init(chan);
1157
1158         /*
1159          * NOTE: some controllers may have additional features that we
1160          * need to initialize here, like "scatter-gather" (which
1161          * doesn't mean what you think it means), and status writeback.
1162          */
1163
1164         /* Enable controller here if needed */
1165         if (!dw->in_use)
1166                 dw_dma_on(dw);
1167         dw->in_use |= dwc->mask;
1168
1169         spin_lock_irqsave(&dwc->lock, flags);
1170         i = dwc->descs_allocated;
1171         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1172                 dma_addr_t phys;
1173
1174                 spin_unlock_irqrestore(&dwc->lock, flags);
1175
1176                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1177                 if (!desc)
1178                         goto err_desc_alloc;
1179
1180                 memset(desc, 0, sizeof(struct dw_desc));
1181
1182                 INIT_LIST_HEAD(&desc->tx_list);
1183                 dma_async_tx_descriptor_init(&desc->txd, chan);
1184                 desc->txd.tx_submit = dwc_tx_submit;
1185                 desc->txd.flags = DMA_CTRL_ACK;
1186                 desc->txd.phys = phys;
1187
1188                 dwc_desc_put(dwc, desc);
1189
1190                 spin_lock_irqsave(&dwc->lock, flags);
1191                 i = ++dwc->descs_allocated;
1192         }
1193
1194         spin_unlock_irqrestore(&dwc->lock, flags);
1195
1196         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1197
1198         return i;
1199
1200 err_desc_alloc:
1201         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1202
1203         return i;
1204 }
1205
1206 static void dwc_free_chan_resources(struct dma_chan *chan)
1207 {
1208         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1209         struct dw_dma           *dw = to_dw_dma(chan->device);
1210         struct dw_desc          *desc, *_desc;
1211         unsigned long           flags;
1212         LIST_HEAD(list);
1213
1214         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1215                         dwc->descs_allocated);
1216
1217         /* ASSERT:  channel is idle */
1218         BUG_ON(!list_empty(&dwc->active_list));
1219         BUG_ON(!list_empty(&dwc->queue));
1220         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1221
1222         spin_lock_irqsave(&dwc->lock, flags);
1223         list_splice_init(&dwc->free_list, &list);
1224         dwc->descs_allocated = 0;
1225         dwc->initialized = false;
1226
1227         /* Disable interrupts */
1228         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1229         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1230         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1231
1232         spin_unlock_irqrestore(&dwc->lock, flags);
1233
1234         /* Disable controller in case it was a last user */
1235         dw->in_use &= ~dwc->mask;
1236         if (!dw->in_use)
1237                 dw_dma_off(dw);
1238
1239         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1240                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1241                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1242         }
1243
1244         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1245 }
1246
1247 /* --------------------- Cyclic DMA API extensions -------------------- */
1248
1249 /**
1250  * dw_dma_cyclic_start - start the cyclic DMA transfer
1251  * @chan: the DMA channel to start
1252  *
1253  * Must be called with soft interrupts disabled. Returns zero on success or
1254  * -errno on failure.
1255  */
1256 int dw_dma_cyclic_start(struct dma_chan *chan)
1257 {
1258         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1259         unsigned long           flags;
1260
1261         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1262                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1263                 return -ENODEV;
1264         }
1265
1266         spin_lock_irqsave(&dwc->lock, flags);
1267         dwc_dostart(dwc, dwc->cdesc->desc[0]);
1268         spin_unlock_irqrestore(&dwc->lock, flags);
1269
1270         return 0;
1271 }
1272 EXPORT_SYMBOL(dw_dma_cyclic_start);
1273
1274 /**
1275  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1276  * @chan: the DMA channel to stop
1277  *
1278  * Must be called with soft interrupts disabled.
1279  */
1280 void dw_dma_cyclic_stop(struct dma_chan *chan)
1281 {
1282         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1283         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1284         unsigned long           flags;
1285
1286         spin_lock_irqsave(&dwc->lock, flags);
1287
1288         dwc_chan_disable(dw, dwc);
1289
1290         spin_unlock_irqrestore(&dwc->lock, flags);
1291 }
1292 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1293
1294 /**
1295  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1296  * @chan: the DMA channel to prepare
1297  * @buf_addr: physical DMA address where the buffer starts
1298  * @buf_len: total number of bytes for the entire buffer
1299  * @period_len: number of bytes for each period
1300  * @direction: transfer direction, to or from device
1301  *
1302  * Must be called before trying to start the transfer. Returns a valid struct
1303  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1304  */
1305 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1306                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1307                 enum dma_transfer_direction direction)
1308 {
1309         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1310         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1311         struct dw_cyclic_desc           *cdesc;
1312         struct dw_cyclic_desc           *retval = NULL;
1313         struct dw_desc                  *desc;
1314         struct dw_desc                  *last = NULL;
1315         unsigned long                   was_cyclic;
1316         unsigned int                    reg_width;
1317         unsigned int                    periods;
1318         unsigned int                    i;
1319         unsigned long                   flags;
1320
1321         spin_lock_irqsave(&dwc->lock, flags);
1322         if (dwc->nollp) {
1323                 spin_unlock_irqrestore(&dwc->lock, flags);
1324                 dev_dbg(chan2dev(&dwc->chan),
1325                                 "channel doesn't support LLP transfers\n");
1326                 return ERR_PTR(-EINVAL);
1327         }
1328
1329         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1330                 spin_unlock_irqrestore(&dwc->lock, flags);
1331                 dev_dbg(chan2dev(&dwc->chan),
1332                                 "queue and/or active list are not empty\n");
1333                 return ERR_PTR(-EBUSY);
1334         }
1335
1336         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1337         spin_unlock_irqrestore(&dwc->lock, flags);
1338         if (was_cyclic) {
1339                 dev_dbg(chan2dev(&dwc->chan),
1340                                 "channel already prepared for cyclic DMA\n");
1341                 return ERR_PTR(-EBUSY);
1342         }
1343
1344         retval = ERR_PTR(-EINVAL);
1345
1346         if (unlikely(!is_slave_direction(direction)))
1347                 goto out_err;
1348
1349         dwc->direction = direction;
1350
1351         if (direction == DMA_MEM_TO_DEV)
1352                 reg_width = __ffs(sconfig->dst_addr_width);
1353         else
1354                 reg_width = __ffs(sconfig->src_addr_width);
1355
1356         periods = buf_len / period_len;
1357
1358         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1359         if (period_len > (dwc->block_size << reg_width))
1360                 goto out_err;
1361         if (unlikely(period_len & ((1 << reg_width) - 1)))
1362                 goto out_err;
1363         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1364                 goto out_err;
1365
1366         retval = ERR_PTR(-ENOMEM);
1367
1368         if (periods > NR_DESCS_PER_CHANNEL)
1369                 goto out_err;
1370
1371         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1372         if (!cdesc)
1373                 goto out_err;
1374
1375         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1376         if (!cdesc->desc)
1377                 goto out_err_alloc;
1378
1379         for (i = 0; i < periods; i++) {
1380                 desc = dwc_desc_get(dwc);
1381                 if (!desc)
1382                         goto out_err_desc_get;
1383
1384                 switch (direction) {
1385                 case DMA_MEM_TO_DEV:
1386                         desc->lli.dar = sconfig->dst_addr;
1387                         desc->lli.sar = buf_addr + (period_len * i);
1388                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1389                                         | DWC_CTLL_DST_WIDTH(reg_width)
1390                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1391                                         | DWC_CTLL_DST_FIX
1392                                         | DWC_CTLL_SRC_INC
1393                                         | DWC_CTLL_INT_EN);
1394
1395                         desc->lli.ctllo |= sconfig->device_fc ?
1396                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1397                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1398
1399                         break;
1400                 case DMA_DEV_TO_MEM:
1401                         desc->lli.dar = buf_addr + (period_len * i);
1402                         desc->lli.sar = sconfig->src_addr;
1403                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1404                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1405                                         | DWC_CTLL_DST_WIDTH(reg_width)
1406                                         | DWC_CTLL_DST_INC
1407                                         | DWC_CTLL_SRC_FIX
1408                                         | DWC_CTLL_INT_EN);
1409
1410                         desc->lli.ctllo |= sconfig->device_fc ?
1411                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1412                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1413
1414                         break;
1415                 default:
1416                         break;
1417                 }
1418
1419                 desc->lli.ctlhi = (period_len >> reg_width);
1420                 cdesc->desc[i] = desc;
1421
1422                 if (last)
1423                         last->lli.llp = desc->txd.phys;
1424
1425                 last = desc;
1426         }
1427
1428         /* Let's make a cyclic list */
1429         last->lli.llp = cdesc->desc[0]->txd.phys;
1430
1431         dev_dbg(chan2dev(&dwc->chan),
1432                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1433                         &buf_addr, buf_len, period_len, periods);
1434
1435         cdesc->periods = periods;
1436         dwc->cdesc = cdesc;
1437
1438         return cdesc;
1439
1440 out_err_desc_get:
1441         while (i--)
1442                 dwc_desc_put(dwc, cdesc->desc[i]);
1443 out_err_alloc:
1444         kfree(cdesc);
1445 out_err:
1446         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1447         return (struct dw_cyclic_desc *)retval;
1448 }
1449 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1450
1451 /**
1452  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1453  * @chan: the DMA channel to free
1454  */
1455 void dw_dma_cyclic_free(struct dma_chan *chan)
1456 {
1457         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1458         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1459         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1460         int                     i;
1461         unsigned long           flags;
1462
1463         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1464
1465         if (!cdesc)
1466                 return;
1467
1468         spin_lock_irqsave(&dwc->lock, flags);
1469
1470         dwc_chan_disable(dw, dwc);
1471
1472         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1473         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1474         dma_writel(dw, CLEAR.XFER, dwc->mask);
1475
1476         spin_unlock_irqrestore(&dwc->lock, flags);
1477
1478         for (i = 0; i < cdesc->periods; i++)
1479                 dwc_desc_put(dwc, cdesc->desc[i]);
1480
1481         kfree(cdesc->desc);
1482         kfree(cdesc);
1483
1484         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1485 }
1486 EXPORT_SYMBOL(dw_dma_cyclic_free);
1487
1488 /*----------------------------------------------------------------------*/
1489
1490 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1491 {
1492         struct dw_dma           *dw;
1493         bool                    autocfg = false;
1494         unsigned int            dw_params;
1495         unsigned int            max_blk_size = 0;
1496         int                     err;
1497         int                     i;
1498
1499         dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
1500         if (!dw)
1501                 return -ENOMEM;
1502
1503         dw->regs = chip->regs;
1504         chip->dw = dw;
1505
1506         pm_runtime_get_sync(chip->dev);
1507
1508         if (!pdata) {
1509                 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1510                 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1511
1512                 autocfg = dw_params >> DW_PARAMS_EN & 1;
1513                 if (!autocfg) {
1514                         err = -EINVAL;
1515                         goto err_pdata;
1516                 }
1517
1518                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1519                 if (!pdata) {
1520                         err = -ENOMEM;
1521                         goto err_pdata;
1522                 }
1523
1524                 /* Get hardware configuration parameters */
1525                 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1;
1526                 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1527                 for (i = 0; i < pdata->nr_masters; i++) {
1528                         pdata->data_width[i] =
1529                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1530                 }
1531                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1532
1533                 /* Fill platform data with the default values */
1534                 pdata->is_private = true;
1535                 pdata->is_memcpy = true;
1536                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1537                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1538         } else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
1539                 err = -EINVAL;
1540                 goto err_pdata;
1541         }
1542
1543         dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan),
1544                                 GFP_KERNEL);
1545         if (!dw->chan) {
1546                 err = -ENOMEM;
1547                 goto err_pdata;
1548         }
1549
1550         /* Get hardware configuration parameters */
1551         dw->nr_masters = pdata->nr_masters;
1552         for (i = 0; i < dw->nr_masters; i++)
1553                 dw->data_width[i] = pdata->data_width[i];
1554
1555         /* Calculate all channel mask before DMA setup */
1556         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1557
1558         /* Force dma off, just in case */
1559         dw_dma_off(dw);
1560
1561         /* Create a pool of consistent memory blocks for hardware descriptors */
1562         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1563                                          sizeof(struct dw_desc), 4, 0);
1564         if (!dw->desc_pool) {
1565                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1566                 err = -ENOMEM;
1567                 goto err_pdata;
1568         }
1569
1570         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1571
1572         err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED,
1573                           "dw_dmac", dw);
1574         if (err)
1575                 goto err_pdata;
1576
1577         INIT_LIST_HEAD(&dw->dma.channels);
1578         for (i = 0; i < pdata->nr_channels; i++) {
1579                 struct dw_dma_chan      *dwc = &dw->chan[i];
1580
1581                 dwc->chan.device = &dw->dma;
1582                 dma_cookie_init(&dwc->chan);
1583                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1584                         list_add_tail(&dwc->chan.device_node,
1585                                         &dw->dma.channels);
1586                 else
1587                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1588
1589                 /* 7 is highest priority & 0 is lowest. */
1590                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1591                         dwc->priority = pdata->nr_channels - i - 1;
1592                 else
1593                         dwc->priority = i;
1594
1595                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1596                 spin_lock_init(&dwc->lock);
1597                 dwc->mask = 1 << i;
1598
1599                 INIT_LIST_HEAD(&dwc->active_list);
1600                 INIT_LIST_HEAD(&dwc->queue);
1601                 INIT_LIST_HEAD(&dwc->free_list);
1602
1603                 channel_clear_bit(dw, CH_EN, dwc->mask);
1604
1605                 dwc->direction = DMA_TRANS_NONE;
1606
1607                 /* Hardware configuration */
1608                 if (autocfg) {
1609                         unsigned int dwc_params;
1610                         unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1;
1611                         void __iomem *addr = chip->regs + r * sizeof(u32);
1612
1613                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1614
1615                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1616                                            dwc_params);
1617
1618                         /*
1619                          * Decode maximum block size for given channel. The
1620                          * stored 4 bit value represents blocks from 0x00 for 3
1621                          * up to 0x0a for 4095.
1622                          */
1623                         dwc->block_size =
1624                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1625                         dwc->nollp =
1626                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1627                 } else {
1628                         dwc->block_size = pdata->block_size;
1629
1630                         /* Check if channel supports multi block transfer */
1631                         channel_writel(dwc, LLP, 0xfffffffc);
1632                         dwc->nollp =
1633                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1634                         channel_writel(dwc, LLP, 0);
1635                 }
1636         }
1637
1638         /* Clear all interrupts on all channels. */
1639         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1640         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1641         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1642         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1643         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1644
1645         /* Set capabilities */
1646         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1647         if (pdata->is_private)
1648                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1649         if (pdata->is_memcpy)
1650                 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1651
1652         dw->dma.dev = chip->dev;
1653         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1654         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1655
1656         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1657         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1658
1659         dw->dma.device_config = dwc_config;
1660         dw->dma.device_pause = dwc_pause;
1661         dw->dma.device_resume = dwc_resume;
1662         dw->dma.device_terminate_all = dwc_terminate_all;
1663
1664         dw->dma.device_tx_status = dwc_tx_status;
1665         dw->dma.device_issue_pending = dwc_issue_pending;
1666
1667         /* DMA capabilities */
1668         dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS;
1669         dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS;
1670         dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
1671                              BIT(DMA_MEM_TO_MEM);
1672         dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1673
1674         err = dma_async_device_register(&dw->dma);
1675         if (err)
1676                 goto err_dma_register;
1677
1678         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1679                  pdata->nr_channels);
1680
1681         pm_runtime_put_sync_suspend(chip->dev);
1682
1683         return 0;
1684
1685 err_dma_register:
1686         free_irq(chip->irq, dw);
1687 err_pdata:
1688         pm_runtime_put_sync_suspend(chip->dev);
1689         return err;
1690 }
1691 EXPORT_SYMBOL_GPL(dw_dma_probe);
1692
1693 int dw_dma_remove(struct dw_dma_chip *chip)
1694 {
1695         struct dw_dma           *dw = chip->dw;
1696         struct dw_dma_chan      *dwc, *_dwc;
1697
1698         pm_runtime_get_sync(chip->dev);
1699
1700         dw_dma_off(dw);
1701         dma_async_device_unregister(&dw->dma);
1702
1703         free_irq(chip->irq, dw);
1704         tasklet_kill(&dw->tasklet);
1705
1706         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1707                         chan.device_node) {
1708                 list_del(&dwc->chan.device_node);
1709                 channel_clear_bit(dw, CH_EN, dwc->mask);
1710         }
1711
1712         pm_runtime_put_sync_suspend(chip->dev);
1713         return 0;
1714 }
1715 EXPORT_SYMBOL_GPL(dw_dma_remove);
1716
1717 int dw_dma_disable(struct dw_dma_chip *chip)
1718 {
1719         struct dw_dma *dw = chip->dw;
1720
1721         dw_dma_off(dw);
1722         return 0;
1723 }
1724 EXPORT_SYMBOL_GPL(dw_dma_disable);
1725
1726 int dw_dma_enable(struct dw_dma_chip *chip)
1727 {
1728         struct dw_dma *dw = chip->dw;
1729
1730         dw_dma_on(dw);
1731         return 0;
1732 }
1733 EXPORT_SYMBOL_GPL(dw_dma_enable);
1734
1735 MODULE_LICENSE("GPL v2");
1736 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1737 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1738 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");