2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
4 * Copyright (C) 2014 Atmel Corporation
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
36 #include "dmaengine.h"
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
176 #define AT_XDMAC_MAX_CHAN 0x20
177 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
179 #define AT_XDMAC_RESIDUE_MAX_RETRIES 5
181 #define AT_XDMAC_DMA_BUSWIDTHS\
182 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
183 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
184 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
186 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
189 AT_XDMAC_CHAN_IS_CYCLIC = 0,
190 AT_XDMAC_CHAN_IS_PAUSED,
193 /* ----- Channels ----- */
194 struct at_xdmac_chan {
195 struct dma_chan chan;
196 void __iomem *ch_regs;
197 u32 mask; /* Channel Mask */
198 u32 cfg; /* Channel Configuration Register */
199 u8 perid; /* Peripheral ID */
200 u8 perif; /* Peripheral Interface */
201 u8 memif; /* Memory Interface */
206 unsigned long status;
207 struct tasklet_struct tasklet;
208 struct dma_slave_config sconfig;
212 struct list_head xfers_list;
213 struct list_head free_descs_list;
217 /* ----- Controller ----- */
219 struct dma_device dma;
225 struct dma_pool *at_xdmac_desc_pool;
226 struct at_xdmac_chan chan[0];
230 /* ----- Descriptors ----- */
232 /* Linked List Descriptor */
233 struct at_xdmac_lld {
234 dma_addr_t mbr_nda; /* Next Descriptor Member */
235 u32 mbr_ubc; /* Microblock Control Member */
236 dma_addr_t mbr_sa; /* Source Address Member */
237 dma_addr_t mbr_da; /* Destination Address Member */
238 u32 mbr_cfg; /* Configuration Register */
239 u32 mbr_bc; /* Block Control Register */
240 u32 mbr_ds; /* Data Stride Register */
241 u32 mbr_sus; /* Source Microblock Stride Register */
242 u32 mbr_dus; /* Destination Microblock Stride Register */
245 /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */
246 struct at_xdmac_desc {
247 struct at_xdmac_lld lld;
248 enum dma_transfer_direction direction;
249 struct dma_async_tx_descriptor tx_dma_desc;
250 struct list_head desc_node;
251 /* Following members are only used by the first descriptor */
253 unsigned int xfer_size;
254 struct list_head descs_list;
255 struct list_head xfer_node;
256 } __aligned(sizeof(u64));
258 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
260 return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
263 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
264 #define at_xdmac_write(atxdmac, reg, value) \
265 writel_relaxed((value), (atxdmac)->regs + (reg))
267 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
268 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
270 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
272 return container_of(dchan, struct at_xdmac_chan, chan);
275 static struct device *chan2dev(struct dma_chan *chan)
277 return &chan->dev->device;
280 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
282 return container_of(ddev, struct at_xdmac, dma);
285 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
287 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
290 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
292 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
295 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
297 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
300 static inline int at_xdmac_csize(u32 maxburst)
304 csize = ffs(maxburst) - 1;
311 static inline u8 at_xdmac_get_dwidth(u32 cfg)
313 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
316 static unsigned int init_nr_desc_per_channel = 64;
317 module_param(init_nr_desc_per_channel, uint, 0644);
318 MODULE_PARM_DESC(init_nr_desc_per_channel,
319 "initial descriptors per channel (default: 64)");
322 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
324 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
327 static void at_xdmac_off(struct at_xdmac *atxdmac)
329 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
331 /* Wait that all chans are disabled. */
332 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
335 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
338 /* Call with lock hold. */
339 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
340 struct at_xdmac_desc *first)
342 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
345 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
347 if (at_xdmac_chan_is_enabled(atchan))
350 /* Set transfer as active to not try to start it again. */
351 first->active_xfer = true;
353 /* Tell xdmac where to get the first descriptor. */
354 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
355 | AT_XDMAC_CNDA_NDAIF(atchan->memif);
356 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
359 * When doing non cyclic transfer we need to use the next
360 * descriptor view 2 since some fields of the configuration register
361 * depend on transfer size and src/dest addresses.
363 if (at_xdmac_chan_is_cyclic(atchan))
364 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
365 else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)
366 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
368 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
370 * Even if the register will be updated from the configuration in the
371 * descriptor when using view 2 or higher, the PROT bit won't be set
372 * properly. This bit can be modified only by using the channel
373 * configuration register.
375 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
377 reg |= AT_XDMAC_CNDC_NDDUP
378 | AT_XDMAC_CNDC_NDSUP
380 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
382 dev_vdbg(chan2dev(&atchan->chan),
383 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
384 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
385 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
386 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
387 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
388 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
389 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
391 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
392 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE | AT_XDMAC_CIE_ROIE;
394 * There is no end of list when doing cyclic dma, we need to get
395 * an interrupt after each periods.
397 if (at_xdmac_chan_is_cyclic(atchan))
398 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
399 reg | AT_XDMAC_CIE_BIE);
401 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
402 reg | AT_XDMAC_CIE_LIE);
403 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
404 dev_vdbg(chan2dev(&atchan->chan),
405 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
407 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
409 dev_vdbg(chan2dev(&atchan->chan),
410 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
411 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
412 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
413 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
414 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
415 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
416 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
420 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
422 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
423 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
425 unsigned long irqflags;
427 spin_lock_irqsave(&atchan->lock, irqflags);
428 cookie = dma_cookie_assign(tx);
430 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
431 __func__, atchan, desc);
432 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
433 if (list_is_singular(&atchan->xfers_list))
434 at_xdmac_start_xfer(atchan, desc);
436 spin_unlock_irqrestore(&atchan->lock, irqflags);
440 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
443 struct at_xdmac_desc *desc;
444 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
447 desc = dma_pool_alloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
449 memset(desc, 0, sizeof(*desc));
450 INIT_LIST_HEAD(&desc->descs_list);
451 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
452 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
453 desc->tx_dma_desc.phys = phys;
459 void at_xdmac_init_used_desc(struct at_xdmac_desc *desc)
461 memset(&desc->lld, 0, sizeof(desc->lld));
462 INIT_LIST_HEAD(&desc->descs_list);
463 desc->direction = DMA_TRANS_NONE;
465 desc->active_xfer = false;
468 /* Call must be protected by lock. */
469 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
471 struct at_xdmac_desc *desc;
473 if (list_empty(&atchan->free_descs_list)) {
474 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
476 desc = list_first_entry(&atchan->free_descs_list,
477 struct at_xdmac_desc, desc_node);
478 list_del(&desc->desc_node);
479 at_xdmac_init_used_desc(desc);
485 static void at_xdmac_queue_desc(struct dma_chan *chan,
486 struct at_xdmac_desc *prev,
487 struct at_xdmac_desc *desc)
492 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
493 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
495 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
496 __func__, prev, &prev->lld.mbr_nda);
499 static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
500 struct at_xdmac_desc *desc)
507 dev_dbg(chan2dev(chan),
508 "%s: incrementing the block count of the desc 0x%p\n",
512 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
513 struct of_dma *of_dma)
515 struct at_xdmac *atxdmac = of_dma->of_dma_data;
516 struct at_xdmac_chan *atchan;
517 struct dma_chan *chan;
518 struct device *dev = atxdmac->dma.dev;
520 if (dma_spec->args_count != 1) {
521 dev_err(dev, "dma phandler args: bad number of args\n");
525 chan = dma_get_any_slave_channel(&atxdmac->dma);
527 dev_err(dev, "can't get a dma channel\n");
531 atchan = to_at_xdmac_chan(chan);
532 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
533 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
534 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
535 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
536 atchan->memif, atchan->perif, atchan->perid);
541 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
542 enum dma_transfer_direction direction)
544 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
547 if (direction == DMA_DEV_TO_MEM) {
549 AT91_XDMAC_DT_PERID(atchan->perid)
550 | AT_XDMAC_CC_DAM_INCREMENTED_AM
551 | AT_XDMAC_CC_SAM_FIXED_AM
552 | AT_XDMAC_CC_DIF(atchan->memif)
553 | AT_XDMAC_CC_SIF(atchan->perif)
554 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
555 | AT_XDMAC_CC_DSYNC_PER2MEM
556 | AT_XDMAC_CC_MBSIZE_SIXTEEN
557 | AT_XDMAC_CC_TYPE_PER_TRAN;
558 csize = ffs(atchan->sconfig.src_maxburst) - 1;
560 dev_err(chan2dev(chan), "invalid src maxburst value\n");
563 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
564 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
566 dev_err(chan2dev(chan), "invalid src addr width value\n");
569 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
570 } else if (direction == DMA_MEM_TO_DEV) {
572 AT91_XDMAC_DT_PERID(atchan->perid)
573 | AT_XDMAC_CC_DAM_FIXED_AM
574 | AT_XDMAC_CC_SAM_INCREMENTED_AM
575 | AT_XDMAC_CC_DIF(atchan->perif)
576 | AT_XDMAC_CC_SIF(atchan->memif)
577 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
578 | AT_XDMAC_CC_DSYNC_MEM2PER
579 | AT_XDMAC_CC_MBSIZE_SIXTEEN
580 | AT_XDMAC_CC_TYPE_PER_TRAN;
581 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
583 dev_err(chan2dev(chan), "invalid src maxburst value\n");
586 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
587 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
589 dev_err(chan2dev(chan), "invalid dst addr width value\n");
592 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
595 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
601 * Only check that maxburst and addr width values are supported by the
602 * the controller but not that the configuration is good to perform the
603 * transfer since we don't know the direction at this stage.
605 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
607 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
608 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
611 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
612 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
618 static int at_xdmac_set_slave_config(struct dma_chan *chan,
619 struct dma_slave_config *sconfig)
621 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
623 if (at_xdmac_check_slave_config(sconfig)) {
624 dev_err(chan2dev(chan), "invalid slave configuration\n");
628 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
633 static struct dma_async_tx_descriptor *
634 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
635 unsigned int sg_len, enum dma_transfer_direction direction,
636 unsigned long flags, void *context)
638 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
639 struct at_xdmac_desc *first = NULL, *prev = NULL;
640 struct scatterlist *sg;
642 unsigned int xfer_size = 0;
643 unsigned long irqflags;
644 struct dma_async_tx_descriptor *ret = NULL;
649 if (!is_slave_direction(direction)) {
650 dev_err(chan2dev(chan), "invalid DMA direction\n");
654 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
656 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
659 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
660 spin_lock_irqsave(&atchan->lock, irqflags);
662 if (at_xdmac_compute_chan_conf(chan, direction))
665 /* Prepare descriptors. */
666 for_each_sg(sgl, sg, sg_len, i) {
667 struct at_xdmac_desc *desc = NULL;
668 u32 len, mem, dwidth, fixed_dwidth;
670 len = sg_dma_len(sg);
671 mem = sg_dma_address(sg);
672 if (unlikely(!len)) {
673 dev_err(chan2dev(chan), "sg data length is zero\n");
676 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
677 __func__, i, len, mem);
679 desc = at_xdmac_get_desc(atchan);
681 dev_err(chan2dev(chan), "can't get descriptor\n");
683 list_splice_init(&first->descs_list, &atchan->free_descs_list);
687 /* Linked list descriptor setup. */
688 if (direction == DMA_DEV_TO_MEM) {
689 desc->lld.mbr_sa = atchan->sconfig.src_addr;
690 desc->lld.mbr_da = mem;
692 desc->lld.mbr_sa = mem;
693 desc->lld.mbr_da = atchan->sconfig.dst_addr;
695 dwidth = at_xdmac_get_dwidth(atchan->cfg);
696 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
698 : AT_XDMAC_CC_DWIDTH_BYTE;
699 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
700 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
701 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
702 | (len >> fixed_dwidth); /* microblock length */
703 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
704 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
705 dev_dbg(chan2dev(chan),
706 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
707 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
711 at_xdmac_queue_desc(chan, prev, desc);
717 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
718 __func__, desc, first);
719 list_add_tail(&desc->desc_node, &first->descs_list);
724 first->tx_dma_desc.flags = flags;
725 first->xfer_size = xfer_size;
726 first->direction = direction;
727 ret = &first->tx_dma_desc;
730 spin_unlock_irqrestore(&atchan->lock, irqflags);
734 static struct dma_async_tx_descriptor *
735 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
736 size_t buf_len, size_t period_len,
737 enum dma_transfer_direction direction,
740 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
741 struct at_xdmac_desc *first = NULL, *prev = NULL;
742 unsigned int periods = buf_len / period_len;
744 unsigned long irqflags;
746 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
747 __func__, &buf_addr, buf_len, period_len,
748 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
750 if (!is_slave_direction(direction)) {
751 dev_err(chan2dev(chan), "invalid DMA direction\n");
755 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
756 dev_err(chan2dev(chan), "channel currently used\n");
760 if (at_xdmac_compute_chan_conf(chan, direction))
763 for (i = 0; i < periods; i++) {
764 struct at_xdmac_desc *desc = NULL;
766 spin_lock_irqsave(&atchan->lock, irqflags);
767 desc = at_xdmac_get_desc(atchan);
769 dev_err(chan2dev(chan), "can't get descriptor\n");
771 list_splice_init(&first->descs_list, &atchan->free_descs_list);
772 spin_unlock_irqrestore(&atchan->lock, irqflags);
775 spin_unlock_irqrestore(&atchan->lock, irqflags);
776 dev_dbg(chan2dev(chan),
777 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
778 __func__, desc, &desc->tx_dma_desc.phys);
780 if (direction == DMA_DEV_TO_MEM) {
781 desc->lld.mbr_sa = atchan->sconfig.src_addr;
782 desc->lld.mbr_da = buf_addr + i * period_len;
784 desc->lld.mbr_sa = buf_addr + i * period_len;
785 desc->lld.mbr_da = atchan->sconfig.dst_addr;
787 desc->lld.mbr_cfg = atchan->cfg;
788 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
789 | AT_XDMAC_MBR_UBC_NDEN
790 | AT_XDMAC_MBR_UBC_NSEN
791 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
793 dev_dbg(chan2dev(chan),
794 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
795 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
799 at_xdmac_queue_desc(chan, prev, desc);
805 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
806 __func__, desc, first);
807 list_add_tail(&desc->desc_node, &first->descs_list);
810 at_xdmac_queue_desc(chan, prev, first);
811 first->tx_dma_desc.flags = flags;
812 first->xfer_size = buf_len;
813 first->direction = direction;
815 return &first->tx_dma_desc;
818 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
823 * Check address alignment to select the greater data width we
826 * Some XDMAC implementations don't provide dword transfer, in
827 * this case selecting dword has the same behavior as
828 * selecting word transfers.
831 width = AT_XDMAC_CC_DWIDTH_DWORD;
832 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
833 } else if (!(addr & 3)) {
834 width = AT_XDMAC_CC_DWIDTH_WORD;
835 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
836 } else if (!(addr & 1)) {
837 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
838 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
840 width = AT_XDMAC_CC_DWIDTH_BYTE;
841 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
847 static struct at_xdmac_desc *
848 at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
849 struct at_xdmac_chan *atchan,
850 struct at_xdmac_desc *prev,
851 dma_addr_t src, dma_addr_t dst,
852 struct dma_interleaved_template *xt,
853 struct data_chunk *chunk)
855 struct at_xdmac_desc *desc;
860 * WARNING: The channel configuration is set here since there is no
861 * dmaengine_slave_config call in this case. Moreover we don't know the
862 * direction, it involves we can't dynamically set the source and dest
863 * interface so we have to use the same one. Only interface 0 allows EBI
864 * access. Hopefully we can access DDR through both ports (at least on
865 * SAMA5D4x), so we can use the same interface for source and dest,
866 * that solves the fact we don't know the direction.
868 u32 chan_cc = AT_XDMAC_CC_DIF(0)
870 | AT_XDMAC_CC_MBSIZE_SIXTEEN
871 | AT_XDMAC_CC_TYPE_MEM_TRAN;
873 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
874 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
875 dev_dbg(chan2dev(chan),
876 "%s: chunk too big (%d, max size %lu)...\n",
877 __func__, chunk->size,
878 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
883 dev_dbg(chan2dev(chan),
884 "Adding items at the end of desc 0x%p\n", prev);
888 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM;
890 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
895 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM;
897 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
900 spin_lock_irqsave(&atchan->lock, flags);
901 desc = at_xdmac_get_desc(atchan);
902 spin_unlock_irqrestore(&atchan->lock, flags);
904 dev_err(chan2dev(chan), "can't get descriptor\n");
908 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
910 ublen = chunk->size >> dwidth;
912 desc->lld.mbr_sa = src;
913 desc->lld.mbr_da = dst;
914 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
915 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
917 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
918 | AT_XDMAC_MBR_UBC_NDEN
919 | AT_XDMAC_MBR_UBC_NSEN
921 desc->lld.mbr_cfg = chan_cc;
923 dev_dbg(chan2dev(chan),
924 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
925 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da,
926 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
930 at_xdmac_queue_desc(chan, prev, desc);
935 static struct dma_async_tx_descriptor *
936 at_xdmac_prep_interleaved(struct dma_chan *chan,
937 struct dma_interleaved_template *xt,
940 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
941 struct at_xdmac_desc *prev = NULL, *first = NULL;
942 dma_addr_t dst_addr, src_addr;
943 size_t src_skip = 0, dst_skip = 0, len = 0;
944 struct data_chunk *chunk;
947 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM))
951 * TODO: Handle the case where we have to repeat a chain of
954 if ((xt->numf > 1) && (xt->frame_size > 1))
957 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n",
958 __func__, &xt->src_start, &xt->dst_start, xt->numf,
959 xt->frame_size, flags);
961 src_addr = xt->src_start;
962 dst_addr = xt->dst_start;
965 first = at_xdmac_interleaved_queue_desc(chan, atchan,
970 /* Length of the block is (BLEN+1) microblocks. */
971 for (i = 0; i < xt->numf - 1; i++)
972 at_xdmac_increment_block_count(chan, first);
974 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
975 __func__, first, first);
976 list_add_tail(&first->desc_node, &first->descs_list);
978 for (i = 0; i < xt->frame_size; i++) {
979 size_t src_icg = 0, dst_icg = 0;
980 struct at_xdmac_desc *desc;
984 dst_icg = dmaengine_get_dst_icg(xt, chunk);
985 src_icg = dmaengine_get_src_icg(xt, chunk);
987 src_skip = chunk->size + src_icg;
988 dst_skip = chunk->size + dst_icg;
990 dev_dbg(chan2dev(chan),
991 "%s: chunk size=%d, src icg=%d, dst icg=%d\n",
992 __func__, chunk->size, src_icg, dst_icg);
994 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
999 list_splice_init(&first->descs_list,
1000 &atchan->free_descs_list);
1007 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1008 __func__, desc, first);
1009 list_add_tail(&desc->desc_node, &first->descs_list);
1012 src_addr += src_skip;
1015 dst_addr += dst_skip;
1022 first->tx_dma_desc.cookie = -EBUSY;
1023 first->tx_dma_desc.flags = flags;
1024 first->xfer_size = len;
1026 return &first->tx_dma_desc;
1029 static struct dma_async_tx_descriptor *
1030 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1031 size_t len, unsigned long flags)
1033 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1034 struct at_xdmac_desc *first = NULL, *prev = NULL;
1035 size_t remaining_size = len, xfer_size = 0, ublen;
1036 dma_addr_t src_addr = src, dst_addr = dest;
1039 * WARNING: We don't know the direction, it involves we can't
1040 * dynamically set the source and dest interface so we have to use the
1041 * same one. Only interface 0 allows EBI access. Hopefully we can
1042 * access DDR through both ports (at least on SAMA5D4x), so we can use
1043 * the same interface for source and dest, that solves the fact we
1044 * don't know the direction.
1046 u32 chan_cc = AT_XDMAC_CC_DAM_INCREMENTED_AM
1047 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1048 | AT_XDMAC_CC_DIF(0)
1049 | AT_XDMAC_CC_SIF(0)
1050 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1051 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1052 unsigned long irqflags;
1054 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1055 __func__, &src, &dest, len, flags);
1060 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
1062 /* Prepare descriptors. */
1063 while (remaining_size) {
1064 struct at_xdmac_desc *desc = NULL;
1066 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
1068 spin_lock_irqsave(&atchan->lock, irqflags);
1069 desc = at_xdmac_get_desc(atchan);
1070 spin_unlock_irqrestore(&atchan->lock, irqflags);
1072 dev_err(chan2dev(chan), "can't get descriptor\n");
1074 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1078 /* Update src and dest addresses. */
1079 src_addr += xfer_size;
1080 dst_addr += xfer_size;
1082 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1083 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1085 xfer_size = remaining_size;
1087 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
1089 /* Check remaining length and change data width if needed. */
1090 dwidth = at_xdmac_align_width(chan,
1091 src_addr | dst_addr | xfer_size);
1092 chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
1093 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1095 ublen = xfer_size >> dwidth;
1096 remaining_size -= xfer_size;
1098 desc->lld.mbr_sa = src_addr;
1099 desc->lld.mbr_da = dst_addr;
1100 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1101 | AT_XDMAC_MBR_UBC_NDEN
1102 | AT_XDMAC_MBR_UBC_NSEN
1104 desc->lld.mbr_cfg = chan_cc;
1106 dev_dbg(chan2dev(chan),
1107 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1108 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
1112 at_xdmac_queue_desc(chan, prev, desc);
1118 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1119 __func__, desc, first);
1120 list_add_tail(&desc->desc_node, &first->descs_list);
1123 first->tx_dma_desc.flags = flags;
1124 first->xfer_size = len;
1126 return &first->tx_dma_desc;
1129 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1130 struct at_xdmac_chan *atchan,
1131 dma_addr_t dst_addr,
1135 struct at_xdmac_desc *desc;
1136 unsigned long flags;
1140 * WARNING: The channel configuration is set here since there is no
1141 * dmaengine_slave_config call in this case. Moreover we don't know the
1142 * direction, it involves we can't dynamically set the source and dest
1143 * interface so we have to use the same one. Only interface 0 allows EBI
1144 * access. Hopefully we can access DDR through both ports (at least on
1145 * SAMA5D4x), so we can use the same interface for source and dest,
1146 * that solves the fact we don't know the direction.
1148 u32 chan_cc = AT_XDMAC_CC_DAM_UBS_AM
1149 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1150 | AT_XDMAC_CC_DIF(0)
1151 | AT_XDMAC_CC_SIF(0)
1152 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1153 | AT_XDMAC_CC_MEMSET_HW_MODE
1154 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1156 dwidth = at_xdmac_align_width(chan, dst_addr);
1158 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1159 dev_err(chan2dev(chan),
1160 "%s: Transfer too large, aborting...\n",
1165 spin_lock_irqsave(&atchan->lock, flags);
1166 desc = at_xdmac_get_desc(atchan);
1167 spin_unlock_irqrestore(&atchan->lock, flags);
1169 dev_err(chan2dev(chan), "can't get descriptor\n");
1173 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1175 ublen = len >> dwidth;
1177 desc->lld.mbr_da = dst_addr;
1178 desc->lld.mbr_ds = value;
1179 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1180 | AT_XDMAC_MBR_UBC_NDEN
1181 | AT_XDMAC_MBR_UBC_NSEN
1183 desc->lld.mbr_cfg = chan_cc;
1185 dev_dbg(chan2dev(chan),
1186 "%s: lld: mbr_da=%pad, mbr_ds=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1187 __func__, &desc->lld.mbr_da, &desc->lld.mbr_ds, desc->lld.mbr_ubc,
1193 struct dma_async_tx_descriptor *
1194 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1195 size_t len, unsigned long flags)
1197 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1198 struct at_xdmac_desc *desc;
1200 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1201 __func__, &dest, len, value, flags);
1206 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1207 list_add_tail(&desc->desc_node, &desc->descs_list);
1209 desc->tx_dma_desc.cookie = -EBUSY;
1210 desc->tx_dma_desc.flags = flags;
1211 desc->xfer_size = len;
1213 return &desc->tx_dma_desc;
1216 static struct dma_async_tx_descriptor *
1217 at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
1218 unsigned int sg_len, int value,
1219 unsigned long flags)
1221 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1222 struct at_xdmac_desc *desc, *pdesc = NULL,
1223 *ppdesc = NULL, *first = NULL;
1224 struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
1225 size_t stride = 0, pstride = 0, len = 0;
1231 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1232 __func__, sg_len, value, flags);
1234 /* Prepare descriptors. */
1235 for_each_sg(sgl, sg, sg_len, i) {
1236 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1237 __func__, &sg_dma_address(sg), sg_dma_len(sg),
1239 desc = at_xdmac_memset_create_desc(chan, atchan,
1244 list_splice_init(&first->descs_list,
1245 &atchan->free_descs_list);
1250 /* Update our strides */
1253 stride = sg_dma_address(sg) -
1254 (sg_dma_address(psg) + sg_dma_len(psg));
1257 * The scatterlist API gives us only the address and
1258 * length of each elements.
1260 * Unfortunately, we don't have the stride, which we
1261 * will need to compute.
1263 * That make us end up in a situation like this one:
1264 * len stride len stride len
1265 * +-------+ +-------+ +-------+
1266 * | N-2 | | N-1 | | N |
1267 * +-------+ +-------+ +-------+
1269 * We need all these three elements (N-2, N-1 and N)
1270 * to actually take the decision on whether we need to
1271 * queue N-1 or reuse N-2.
1273 * We will only consider N if it is the last element.
1275 if (ppdesc && pdesc) {
1276 if ((stride == pstride) &&
1277 (sg_dma_len(ppsg) == sg_dma_len(psg))) {
1278 dev_dbg(chan2dev(chan),
1279 "%s: desc 0x%p can be merged with desc 0x%p\n",
1280 __func__, pdesc, ppdesc);
1283 * Increment the block count of the
1286 at_xdmac_increment_block_count(chan, ppdesc);
1287 ppdesc->lld.mbr_dus = stride;
1290 * Put back the N-1 descriptor in the
1291 * free descriptor list
1293 list_add_tail(&pdesc->desc_node,
1294 &atchan->free_descs_list);
1297 * Make our N-1 descriptor pointer
1298 * point to the N-2 since they were
1304 * Rule out the case where we don't have
1305 * pstride computed yet (our second sg
1308 * We also want to catch the case where there
1309 * would be a negative stride,
1311 } else if (pstride ||
1312 sg_dma_address(sg) < sg_dma_address(psg)) {
1314 * Queue the N-1 descriptor after the
1317 at_xdmac_queue_desc(chan, ppdesc, pdesc);
1320 * Add the N-1 descriptor to the list
1321 * of the descriptors used for this
1324 list_add_tail(&desc->desc_node,
1325 &first->descs_list);
1326 dev_dbg(chan2dev(chan),
1327 "%s: add desc 0x%p to descs_list 0x%p\n",
1328 __func__, desc, first);
1333 * If we are the last element, just see if we have the
1334 * same size than the previous element.
1336 * If so, we can merge it with the previous descriptor
1337 * since we don't care about the stride anymore.
1339 if ((i == (sg_len - 1)) &&
1340 sg_dma_len(psg) == sg_dma_len(sg)) {
1341 dev_dbg(chan2dev(chan),
1342 "%s: desc 0x%p can be merged with desc 0x%p\n",
1343 __func__, desc, pdesc);
1346 * Increment the block count of the N-1
1349 at_xdmac_increment_block_count(chan, pdesc);
1350 pdesc->lld.mbr_dus = stride;
1353 * Put back the N descriptor in the free
1356 list_add_tail(&desc->desc_node,
1357 &atchan->free_descs_list);
1360 /* Update our descriptors */
1364 /* Update our scatter pointers */
1368 len += sg_dma_len(sg);
1371 first->tx_dma_desc.cookie = -EBUSY;
1372 first->tx_dma_desc.flags = flags;
1373 first->xfer_size = len;
1375 return &first->tx_dma_desc;
1378 static enum dma_status
1379 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1380 struct dma_tx_state *txstate)
1382 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1383 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1384 struct at_xdmac_desc *desc, *_desc;
1385 struct list_head *descs_list;
1386 enum dma_status ret;
1388 u32 cur_nda, check_nda, cur_ubc, mask, value;
1390 unsigned long flags;
1393 ret = dma_cookie_status(chan, cookie, txstate);
1394 if (ret == DMA_COMPLETE)
1400 spin_lock_irqsave(&atchan->lock, flags);
1402 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1405 * If the transfer has not been started yet, don't need to compute the
1406 * residue, it's the transfer length.
1408 if (!desc->active_xfer) {
1409 dma_set_residue(txstate, desc->xfer_size);
1413 residue = desc->xfer_size;
1415 * Flush FIFO: only relevant when the transfer is source peripheral
1416 * synchronized. Flush is needed before reading CUBC because data in
1417 * the FIFO are not reported by CUBC. Reporting a residue of the
1418 * transfer length while we have data in FIFO can cause issue.
1419 * Usecase: atmel USART has a timeout which means I have received
1420 * characters but there is no more character received for a while. On
1421 * timeout, it requests the residue. If the data are in the DMA FIFO,
1422 * we will return a residue of the transfer length. It means no data
1423 * received. If an application is waiting for these data, it will hang
1424 * since we won't have another USART timeout without receiving new
1427 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1428 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
1429 if ((desc->lld.mbr_cfg & mask) == value) {
1430 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1431 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1436 * The easiest way to compute the residue should be to pause the DMA
1437 * but doing this can lead to miss some data as some devices don't
1439 * We need to read several registers because:
1440 * - DMA is running therefore a descriptor change is possible while
1441 * reading these registers
1442 * - When the block transfer is done, the value of the CUBC register
1443 * is set to its initial value until the fetch of the next descriptor.
1444 * This value will corrupt the residue calculation so we have to skip
1447 * INITD -------- ------------
1448 * |____________________|
1449 * _______________________ _______________
1450 * NDA @desc2 \/ @desc3
1451 * _______________________/\_______________
1452 * __________ ___________ _______________
1453 * CUBC 0 \/ MAX desc1 \/ MAX desc2
1454 * __________/\___________/\_______________
1456 * Since descriptors are aligned on 64 bits, we can assume that
1457 * the update of NDA and CUBC is atomic.
1458 * Memory barriers are used to ensure the read order of the registers.
1459 * A max number of retries is set because unlikely it could never ends.
1461 for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
1462 check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1464 initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
1466 cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
1468 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1471 if ((check_nda == cur_nda) && initd)
1475 if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) {
1481 * Flush FIFO: only relevant when the transfer is source peripheral
1482 * synchronized. Another flush is needed here because CUBC is updated
1483 * when the controller sends the data write command. It can lead to
1484 * report data that are not written in the memory or the device. The
1485 * FIFO flush ensures that data are really written.
1487 if ((desc->lld.mbr_cfg & mask) == value) {
1488 at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
1489 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1494 * Remove size of all microblocks already transferred and the current
1495 * one. Then add the remaining size to transfer of the current
1498 descs_list = &desc->descs_list;
1499 list_for_each_entry_safe(desc, _desc, descs_list, desc_node) {
1500 dwidth = at_xdmac_get_dwidth(desc->lld.mbr_cfg);
1501 residue -= (desc->lld.mbr_ubc & 0xffffff) << dwidth;
1502 if ((desc->lld.mbr_nda & 0xfffffffc) == cur_nda)
1505 residue += cur_ubc << dwidth;
1507 dma_set_residue(txstate, residue);
1509 dev_dbg(chan2dev(chan),
1510 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1511 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
1514 spin_unlock_irqrestore(&atchan->lock, flags);
1518 /* Call must be protected by lock. */
1519 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1520 struct at_xdmac_desc *desc)
1522 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1525 * Remove the transfer from the transfer list then move the transfer
1526 * descriptors into the free descriptors list.
1528 list_del(&desc->xfer_node);
1529 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1532 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1534 struct at_xdmac_desc *desc;
1535 unsigned long flags;
1537 spin_lock_irqsave(&atchan->lock, flags);
1540 * If channel is enabled, do nothing, advance_work will be triggered
1541 * after the interruption.
1543 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1544 desc = list_first_entry(&atchan->xfers_list,
1545 struct at_xdmac_desc,
1547 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1548 if (!desc->active_xfer)
1549 at_xdmac_start_xfer(atchan, desc);
1552 spin_unlock_irqrestore(&atchan->lock, flags);
1555 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1557 struct at_xdmac_desc *desc;
1558 struct dma_async_tx_descriptor *txd;
1560 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1561 txd = &desc->tx_dma_desc;
1563 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1564 txd->callback(txd->callback_param);
1567 static void at_xdmac_tasklet(unsigned long data)
1569 struct at_xdmac_chan *atchan = (struct at_xdmac_chan *)data;
1570 struct at_xdmac_desc *desc;
1573 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08lx\n",
1574 __func__, atchan->status);
1576 error_mask = AT_XDMAC_CIS_RBEIS
1577 | AT_XDMAC_CIS_WBEIS
1578 | AT_XDMAC_CIS_ROIS;
1580 if (at_xdmac_chan_is_cyclic(atchan)) {
1581 at_xdmac_handle_cyclic(atchan);
1582 } else if ((atchan->status & AT_XDMAC_CIS_LIS)
1583 || (atchan->status & error_mask)) {
1584 struct dma_async_tx_descriptor *txd;
1586 if (atchan->status & AT_XDMAC_CIS_RBEIS)
1587 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1588 if (atchan->status & AT_XDMAC_CIS_WBEIS)
1589 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1590 if (atchan->status & AT_XDMAC_CIS_ROIS)
1591 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1593 spin_lock_bh(&atchan->lock);
1594 desc = list_first_entry(&atchan->xfers_list,
1595 struct at_xdmac_desc,
1597 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1598 BUG_ON(!desc->active_xfer);
1600 txd = &desc->tx_dma_desc;
1602 at_xdmac_remove_xfer(atchan, desc);
1603 spin_unlock_bh(&atchan->lock);
1605 if (!at_xdmac_chan_is_cyclic(atchan)) {
1606 dma_cookie_complete(txd);
1607 if (txd->callback && (txd->flags & DMA_PREP_INTERRUPT))
1608 txd->callback(txd->callback_param);
1611 dma_run_dependencies(txd);
1613 at_xdmac_advance_work(atchan);
1617 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1619 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1620 struct at_xdmac_chan *atchan;
1621 u32 imr, status, pending;
1622 u32 chan_imr, chan_status;
1623 int i, ret = IRQ_NONE;
1626 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1627 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1628 pending = status & imr;
1630 dev_vdbg(atxdmac->dma.dev,
1631 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1632 __func__, status, imr, pending);
1637 /* We have to find which channel has generated the interrupt. */
1638 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1639 if (!((1 << i) & pending))
1642 atchan = &atxdmac->chan[i];
1643 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1644 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1645 atchan->status = chan_status & chan_imr;
1646 dev_vdbg(atxdmac->dma.dev,
1647 "%s: chan%d: imr=0x%x, status=0x%x\n",
1648 __func__, i, chan_imr, chan_status);
1649 dev_vdbg(chan2dev(&atchan->chan),
1650 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1652 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1653 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1654 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1655 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1656 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1657 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1659 if (atchan->status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1660 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1662 tasklet_schedule(&atchan->tasklet);
1671 static void at_xdmac_issue_pending(struct dma_chan *chan)
1673 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1675 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1677 if (!at_xdmac_chan_is_cyclic(atchan))
1678 at_xdmac_advance_work(atchan);
1683 static int at_xdmac_device_config(struct dma_chan *chan,
1684 struct dma_slave_config *config)
1686 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1688 unsigned long flags;
1690 dev_dbg(chan2dev(chan), "%s\n", __func__);
1692 spin_lock_irqsave(&atchan->lock, flags);
1693 ret = at_xdmac_set_slave_config(chan, config);
1694 spin_unlock_irqrestore(&atchan->lock, flags);
1699 static int at_xdmac_device_pause(struct dma_chan *chan)
1701 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1702 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1703 unsigned long flags;
1705 dev_dbg(chan2dev(chan), "%s\n", __func__);
1707 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1710 spin_lock_irqsave(&atchan->lock, flags);
1711 at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
1712 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1713 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1715 spin_unlock_irqrestore(&atchan->lock, flags);
1720 static int at_xdmac_device_resume(struct dma_chan *chan)
1722 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1723 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1724 unsigned long flags;
1726 dev_dbg(chan2dev(chan), "%s\n", __func__);
1728 spin_lock_irqsave(&atchan->lock, flags);
1729 if (!at_xdmac_chan_is_paused(atchan)) {
1730 spin_unlock_irqrestore(&atchan->lock, flags);
1734 at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
1735 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1736 spin_unlock_irqrestore(&atchan->lock, flags);
1741 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1743 struct at_xdmac_desc *desc, *_desc;
1744 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1745 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1746 unsigned long flags;
1748 dev_dbg(chan2dev(chan), "%s\n", __func__);
1750 spin_lock_irqsave(&atchan->lock, flags);
1751 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1752 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1755 /* Cancel all pending transfers. */
1756 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1757 at_xdmac_remove_xfer(atchan, desc);
1759 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1760 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1761 spin_unlock_irqrestore(&atchan->lock, flags);
1766 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1768 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1769 struct at_xdmac_desc *desc;
1771 unsigned long flags;
1773 spin_lock_irqsave(&atchan->lock, flags);
1775 if (at_xdmac_chan_is_enabled(atchan)) {
1776 dev_err(chan2dev(chan),
1777 "can't allocate channel resources (channel enabled)\n");
1782 if (!list_empty(&atchan->free_descs_list)) {
1783 dev_err(chan2dev(chan),
1784 "can't allocate channel resources (channel not free from a previous use)\n");
1789 for (i = 0; i < init_nr_desc_per_channel; i++) {
1790 desc = at_xdmac_alloc_desc(chan, GFP_ATOMIC);
1792 dev_warn(chan2dev(chan),
1793 "only %d descriptors have been allocated\n", i);
1796 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1799 dma_cookie_init(chan);
1801 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1804 spin_unlock_irqrestore(&atchan->lock, flags);
1808 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1810 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1811 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1812 struct at_xdmac_desc *desc, *_desc;
1814 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1815 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1816 list_del(&desc->desc_node);
1817 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1824 static int atmel_xdmac_prepare(struct device *dev)
1826 struct platform_device *pdev = to_platform_device(dev);
1827 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1828 struct dma_chan *chan, *_chan;
1830 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1831 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1833 /* Wait for transfer completion, except in cyclic case. */
1834 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1840 # define atmel_xdmac_prepare NULL
1843 #ifdef CONFIG_PM_SLEEP
1844 static int atmel_xdmac_suspend(struct device *dev)
1846 struct platform_device *pdev = to_platform_device(dev);
1847 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1848 struct dma_chan *chan, *_chan;
1850 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1851 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1853 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1854 if (at_xdmac_chan_is_cyclic(atchan)) {
1855 if (!at_xdmac_chan_is_paused(atchan))
1856 at_xdmac_device_pause(chan);
1857 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1858 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1859 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1862 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1864 at_xdmac_off(atxdmac);
1865 clk_disable_unprepare(atxdmac->clk);
1869 static int atmel_xdmac_resume(struct device *dev)
1871 struct platform_device *pdev = to_platform_device(dev);
1872 struct at_xdmac *atxdmac = platform_get_drvdata(pdev);
1873 struct at_xdmac_chan *atchan;
1874 struct dma_chan *chan, *_chan;
1877 clk_prepare_enable(atxdmac->clk);
1879 /* Clear pending interrupts. */
1880 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1881 atchan = &atxdmac->chan[i];
1882 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
1886 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
1887 at_xdmac_write(atxdmac, AT_XDMAC_GE, atxdmac->save_gs);
1888 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1889 atchan = to_at_xdmac_chan(chan);
1890 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
1891 if (at_xdmac_chan_is_cyclic(atchan)) {
1892 if (at_xdmac_chan_is_paused(atchan))
1893 at_xdmac_device_resume(chan);
1894 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
1895 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
1896 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
1898 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
1903 #endif /* CONFIG_PM_SLEEP */
1905 static int at_xdmac_probe(struct platform_device *pdev)
1907 struct resource *res;
1908 struct at_xdmac *atxdmac;
1909 int irq, size, nr_channels, i, ret;
1913 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1917 irq = platform_get_irq(pdev, 0);
1921 base = devm_ioremap_resource(&pdev->dev, res);
1923 return PTR_ERR(base);
1926 * Read number of xdmac channels, read helper function can't be used
1927 * since atxdmac is not yet allocated and we need to know the number
1928 * of channels to do the allocation.
1930 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
1931 nr_channels = AT_XDMAC_NB_CH(reg);
1932 if (nr_channels > AT_XDMAC_MAX_CHAN) {
1933 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
1938 size = sizeof(*atxdmac);
1939 size += nr_channels * sizeof(struct at_xdmac_chan);
1940 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
1942 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
1946 atxdmac->regs = base;
1949 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
1950 if (IS_ERR(atxdmac->clk)) {
1951 dev_err(&pdev->dev, "can't get dma_clk\n");
1952 return PTR_ERR(atxdmac->clk);
1955 /* Do not use dev res to prevent races with tasklet */
1956 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
1958 dev_err(&pdev->dev, "can't request irq\n");
1962 ret = clk_prepare_enable(atxdmac->clk);
1964 dev_err(&pdev->dev, "can't prepare or enable clock\n");
1968 atxdmac->at_xdmac_desc_pool =
1969 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
1970 sizeof(struct at_xdmac_desc), 4, 0);
1971 if (!atxdmac->at_xdmac_desc_pool) {
1972 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
1974 goto err_clk_disable;
1977 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
1978 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
1979 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
1980 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
1981 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
1982 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
1984 * Without DMA_PRIVATE the driver is not able to allocate more than
1985 * one channel, second allocation fails in private_candidate.
1987 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
1988 atxdmac->dma.dev = &pdev->dev;
1989 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
1990 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
1991 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
1992 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
1993 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
1994 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
1995 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
1996 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
1997 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
1998 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
1999 atxdmac->dma.device_config = at_xdmac_device_config;
2000 atxdmac->dma.device_pause = at_xdmac_device_pause;
2001 atxdmac->dma.device_resume = at_xdmac_device_resume;
2002 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
2003 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2004 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2005 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2006 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2008 /* Disable all chans and interrupts. */
2009 at_xdmac_off(atxdmac);
2011 /* Init channels. */
2012 INIT_LIST_HEAD(&atxdmac->dma.channels);
2013 for (i = 0; i < nr_channels; i++) {
2014 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2016 atchan->chan.device = &atxdmac->dma;
2017 list_add_tail(&atchan->chan.device_node,
2018 &atxdmac->dma.channels);
2020 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
2021 atchan->mask = 1 << i;
2023 spin_lock_init(&atchan->lock);
2024 INIT_LIST_HEAD(&atchan->xfers_list);
2025 INIT_LIST_HEAD(&atchan->free_descs_list);
2026 tasklet_init(&atchan->tasklet, at_xdmac_tasklet,
2027 (unsigned long)atchan);
2029 /* Clear pending interrupts. */
2030 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2033 platform_set_drvdata(pdev, atxdmac);
2035 ret = dma_async_device_register(&atxdmac->dma);
2037 dev_err(&pdev->dev, "fail to register DMA engine device\n");
2038 goto err_clk_disable;
2041 ret = of_dma_controller_register(pdev->dev.of_node,
2042 at_xdmac_xlate, atxdmac);
2044 dev_err(&pdev->dev, "could not register of dma controller\n");
2045 goto err_dma_unregister;
2048 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
2049 nr_channels, atxdmac->regs);
2054 dma_async_device_unregister(&atxdmac->dma);
2056 clk_disable_unprepare(atxdmac->clk);
2058 free_irq(atxdmac->irq, atxdmac->dma.dev);
2062 static int at_xdmac_remove(struct platform_device *pdev)
2064 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
2067 at_xdmac_off(atxdmac);
2068 of_dma_controller_free(pdev->dev.of_node);
2069 dma_async_device_unregister(&atxdmac->dma);
2070 clk_disable_unprepare(atxdmac->clk);
2072 synchronize_irq(atxdmac->irq);
2074 free_irq(atxdmac->irq, atxdmac->dma.dev);
2076 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2077 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2079 tasklet_kill(&atchan->tasklet);
2080 at_xdmac_free_chan_resources(&atchan->chan);
2086 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
2087 .prepare = atmel_xdmac_prepare,
2088 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2091 static const struct of_device_id atmel_xdmac_dt_ids[] = {
2093 .compatible = "atmel,sama5d4-dma",
2098 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
2100 static struct platform_driver at_xdmac_driver = {
2101 .probe = at_xdmac_probe,
2102 .remove = at_xdmac_remove,
2105 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
2106 .pm = &atmel_xdmac_dev_pm_ops,
2110 static int __init at_xdmac_init(void)
2112 return platform_driver_probe(&at_xdmac_driver, at_xdmac_probe);
2114 subsys_initcall(at_xdmac_init);
2116 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2117 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2118 MODULE_LICENSE("GPL");