drivers/devfreq/rk3399_dmc.c

   1 /*
   2  * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
   3  * Author: Lin Huang <hl@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/arm-smccc.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/devfreq.h>
  19 #include <linux/devfreq-event.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_opp.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/rwsem.h>
  27 #include <linux/slab.h>
  28 #include <linux/suspend.h>
  29
  30 #include <soc/rockchip/rkfb_dmc.h>
  31 #include <soc/rockchip/rockchip_sip.h>
  32
  33 struct dram_timing {
  34         unsigned int ddr3_speed_bin;
  35         unsigned int pd_idle;
  36         unsigned int sr_idle;
  37         unsigned int sr_mc_gate_idle;
  38         unsigned int srpd_lite_idle;
  39         unsigned int standby_idle;
  40         unsigned int dram_dll_dis_freq;
  41         unsigned int phy_dll_dis_freq;
  42         unsigned int ddr3_odt_dis_freq;
  43         unsigned int ddr3_drv;
  44         unsigned int ddr3_odt;
  45         unsigned int phy_ddr3_ca_drv;
  46         unsigned int phy_ddr3_dq_drv;
  47         unsigned int phy_ddr3_odt;
  48         unsigned int lpddr3_odt_dis_freq;
  49         unsigned int lpddr3_drv;
  50         unsigned int lpddr3_odt;
  51         unsigned int phy_lpddr3_ca_drv;
  52         unsigned int phy_lpddr3_dq_drv;
  53         unsigned int phy_lpddr3_odt;
  54         unsigned int lpddr4_odt_dis_freq;
  55         unsigned int lpddr4_drv;
  56         unsigned int lpddr4_dq_odt;
  57         unsigned int lpddr4_ca_odt;
  58         unsigned int phy_lpddr4_ca_drv;
  59         unsigned int phy_lpddr4_ck_cs_drv;
  60         unsigned int phy_lpddr4_dq_drv;
  61         unsigned int phy_lpddr4_odt;
  62 };
  63
  64 struct rk3399_dmcfreq {
  65         struct device *dev;
  66         struct devfreq *devfreq;
  67         struct devfreq_simple_ondemand_data ondemand_data;
  68         struct clk *dmc_clk;
  69         struct devfreq_event_dev *edev;
  70         struct mutex lock;
  71         struct dram_timing *timing;
  72
  73         /*
  74          * DDR Converser of Frequency (DCF) is used to implement DDR frequency
  75          * conversion without the participation of CPU, we will implement and
  76          * control it in arm trust firmware.
  77          */
  78         wait_queue_head_t       wait_dcf_queue;
  79         int irq;
  80         int wait_dcf_flag;
  81         struct regulator *vdd_center;
  82         unsigned long rate, target_rate;
  83         unsigned long volt, target_volt;
  84         struct dev_pm_opp *curr_opp;
  85 };
  86
  87 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
  88                                  u32 flags)
  89 {
  90         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
  91         struct dev_pm_opp *opp;
  92         unsigned long old_clk_rate = dmcfreq->rate;
  93         unsigned long target_volt, target_rate;
  94         int err;
  95
  96         rcu_read_lock();
  97         opp = devfreq_recommended_opp(dev, freq, flags);
  98         if (IS_ERR(opp)) {
  99                 rcu_read_unlock();
 100                 return PTR_ERR(opp);
 101         }
 102
 103         target_rate = dev_pm_opp_get_freq(opp);
 104         target_volt = dev_pm_opp_get_voltage(opp);
 105
 106         dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
 107         dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
 108
 109         rcu_read_unlock();
 110
 111         if (dmcfreq->rate == target_rate)
 112                 return 0;
 113
 114         mutex_lock(&dmcfreq->lock);
 115
 116         /*
 117          * If frequency scaling from low to high, adjust voltage first.
 118          * If frequency scaling from high to low, adjust frequency first.
 119          */
 120         if (old_clk_rate < target_rate) {
 121                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 122                                             target_volt);
 123                 if (err) {
 124                         dev_err(dev, "Cannot to set voltage %lu uV\n",
 125                                 target_volt);
 126                         goto out;
 127                 }
 128         }
 129         dmcfreq->wait_dcf_flag = 1;
 130
 131         err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
 132         if (err) {
 133                 dev_err(dev, "Cannot to set frequency %lu (%d)\n",
 134                         target_rate, err);
 135                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 136                                       dmcfreq->volt);
 137                 goto out;
 138         }
 139
 140         /*
 141          * Wait until bcf irq happen, it means freq scaling finish in
 142          * arm trust firmware, use 100ms as timeout time.
 143          */
 144         if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
 145                                 !dmcfreq->wait_dcf_flag, HZ / 10))
 146                 dev_warn(dev, "Timeout waiting for dcf interrupt\n");
 147
 148         /*
 149          * Check the dpll rate,
 150          * There only two result we will get,
 151          * 1. Ddr frequency scaling fail, we still get the old rate.
 152          * 2. Ddr frequency scaling sucessful, we get the rate we set.
 153          */
 154         dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
 155
 156         /* If get the incorrect rate, set voltage to old value. */
 157         if (dmcfreq->rate != target_rate) {
 158                 dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
 159                         Current frequency %lu\n", target_rate, dmcfreq->rate);
 160                 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
 161                                       dmcfreq->volt);
 162                 goto out;
 163         } else if (old_clk_rate > target_rate)
 164                 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
 165                                             target_volt);
 166         if (err)
 167                 dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
 168
 169         dmcfreq->curr_opp = opp;
 170 out:
 171         mutex_unlock(&dmcfreq->lock);
 172         return err;
 173 }
 174
 175 static int rk3399_dmcfreq_get_dev_status(struct device *dev,
 176                                          struct devfreq_dev_status *stat)
 177 {
 178         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 179         struct devfreq_event_data edata;
 180         int ret = 0;
 181
 182         ret = devfreq_event_get_event(dmcfreq->edev, &edata);
 183         if (ret < 0)
 184                 return ret;
 185
 186         stat->current_frequency = dmcfreq->rate;
 187         stat->busy_time = edata.load_count;
 188         stat->total_time = edata.total_count;
 189
 190         return ret;
 191 }
 192
 193 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
 194 {
 195         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 196
 197         *freq = dmcfreq->rate;
 198
 199         return 0;
 200 }
 201
 202 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
 203         .polling_ms     = 200,
 204         .target         = rk3399_dmcfreq_target,
 205         .get_dev_status = rk3399_dmcfreq_get_dev_status,
 206         .get_cur_freq   = rk3399_dmcfreq_get_cur_freq,
 207 };
 208
 209 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
 210 {
 211         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 212         int ret = 0;
 213
 214         ret = devfreq_event_disable_edev(dmcfreq->edev);
 215         if (ret < 0) {
 216                 dev_err(dev, "failed to disable the devfreq-event devices\n");
 217                 return ret;
 218         }
 219
 220         ret = devfreq_suspend_device(dmcfreq->devfreq);
 221         if (ret < 0) {
 222                 dev_err(dev, "failed to suspend the devfreq devices\n");
 223                 return ret;
 224         }
 225
 226         return 0;
 227 }
 228
 229 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
 230 {
 231         struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
 232         int ret = 0;
 233
 234         ret = devfreq_event_enable_edev(dmcfreq->edev);
 235         if (ret < 0) {
 236                 dev_err(dev, "failed to enable the devfreq-event devices\n");
 237                 return ret;
 238         }
 239
 240         ret = devfreq_resume_device(dmcfreq->devfreq);
 241         if (ret < 0) {
 242                 dev_err(dev, "failed to resume the devfreq devices\n");
 243                 return ret;
 244         }
 245         return ret;
 246 }
 247
 248 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
 249                          rk3399_dmcfreq_resume);
 250
 251 static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
 252 {
 253         struct rk3399_dmcfreq *dmcfreq = dev_id;
 254         struct arm_smccc_res res;
 255
 256         dmcfreq->wait_dcf_flag = 0;
 257         wake_up(&dmcfreq->wait_dcf_queue);
 258
 259         /* Clear the DCF interrupt */
 260         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 261                       ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
 262                       0, 0, 0, 0, &res);
 263
 264         return IRQ_HANDLED;
 265 }
 266
 267 static struct dram_timing *of_get_ddr_timings(struct device *dev,
 268                                               struct device_node *np)
 269 {
 270         struct dram_timing      *timing = NULL;
 271         struct device_node      *np_tim;
 272         int ret;
 273
 274         np_tim = of_parse_phandle(np, "ddr_timing", 0);
 275         if (np_tim) {
 276                 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
 277                 if (!timing)
 278                         goto err;
 279
 280                 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
 281                                            &timing->ddr3_speed_bin);
 282                 ret |= of_property_read_u32(np_tim, "pd_idle",
 283                                             &timing->pd_idle);
 284                 ret |= of_property_read_u32(np_tim, "sr_idle",
 285                                             &timing->sr_idle);
 286                 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
 287                                             &timing->sr_mc_gate_idle);
 288                 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
 289                                             &timing->srpd_lite_idle);
 290                 ret |= of_property_read_u32(np_tim, "standby_idle",
 291                                             &timing->standby_idle);
 292                 ret |= of_property_read_u32(np_tim, "dram_dll_dis_freq",
 293                                             &timing->dram_dll_dis_freq);
 294                 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
 295                                             &timing->phy_dll_dis_freq);
 296                 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
 297                                             &timing->ddr3_odt_dis_freq);
 298                 ret |= of_property_read_u32(np_tim, "ddr3_drv",
 299                                             &timing->ddr3_drv);
 300                 ret |= of_property_read_u32(np_tim, "ddr3_odt",
 301                                             &timing->ddr3_odt);
 302                 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
 303                                             &timing->phy_ddr3_ca_drv);
 304                 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
 305                                             &timing->phy_ddr3_dq_drv);
 306                 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
 307                                             &timing->phy_ddr3_odt);
 308                 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
 309                                             &timing->lpddr3_odt_dis_freq);
 310                 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
 311                                             &timing->lpddr3_drv);
 312                 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
 313                                             &timing->lpddr3_odt);
 314                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
 315                                             &timing->phy_lpddr3_ca_drv);
 316                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
 317                                             &timing->phy_lpddr3_dq_drv);
 318                 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
 319                                             &timing->phy_lpddr3_odt);
 320                 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
 321                                             &timing->lpddr4_odt_dis_freq);
 322                 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
 323                                             &timing->lpddr4_drv);
 324                 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
 325                                             &timing->lpddr4_dq_odt);
 326                 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
 327                                             &timing->lpddr4_ca_odt);
 328                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
 329                                             &timing->phy_lpddr4_ca_drv);
 330                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
 331                                             &timing->phy_lpddr4_ck_cs_drv);
 332                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
 333                                             &timing->phy_lpddr4_dq_drv);
 334                 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
 335                                             &timing->phy_lpddr4_odt);
 336                 if (ret) {
 337                         devm_kfree(dev, timing);
 338                         goto err;
 339                 }
 340                 of_node_put(np_tim);
 341                 return timing;
 342         }
 343
 344 err:
 345         if (timing) {
 346                 devm_kfree(dev, timing);
 347                 timing = NULL;
 348         }
 349         of_node_put(np_tim);
 350         return timing;
 351 }
 352
 353 static int of_get_opp_table(struct device *dev,
 354                             struct devfreq_dev_profile *devp)
 355 {
 356         int count;
 357         int i = 0;
 358         unsigned long freq = 0;
 359         struct dev_pm_opp *opp;
 360
 361         rcu_read_lock();
 362         count = dev_pm_opp_get_opp_count(dev);
 363         if (count < 0) {
 364                 rcu_read_unlock();
 365                 return count;
 366         }
 367         rcu_read_unlock();
 368
 369         devp->freq_table = kmalloc_array(count, sizeof(devp->freq_table[0]),
 370                                 GFP_KERNEL);
 371         if (!devp->freq_table)
 372                 return -ENOMEM;
 373
 374         rcu_read_lock();
 375         for (i = 0; i < count; i++, freq++) {
 376                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
 377                 if (IS_ERR(opp))
 378                         break;
 379
 380                 devp->freq_table[i] = freq;
 381         }
 382         rcu_read_unlock();
 383
 384         if (count != i)
 385                 dev_warn(dev, "Unable to enumerate all OPPs (%d!=%d)\n",
 386                          count, i);
 387
 388         devp->max_state = i;
 389         return 0;
 390 }
 391
 392 static int rk3399_dmcfreq_probe(struct platform_device *pdev)
 393 {
 394         struct arm_smccc_res res;
 395         struct device *dev = &pdev->dev;
 396         struct device_node *np = pdev->dev.of_node;
 397         struct rk3399_dmcfreq *data;
 398         int ret, irq, index, size;
 399         uint32_t *timing;
 400         struct dev_pm_opp *opp;
 401         struct devfreq_dev_profile *devp = &rk3399_devfreq_dmc_profile;
 402
 403         irq = platform_get_irq(pdev, 0);
 404         if (irq < 0) {
 405                 dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
 406                 return -EINVAL;
 407         }
 408         data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
 409         if (!data)
 410                 return -ENOMEM;
 411
 412         mutex_init(&data->lock);
 413
 414         data->vdd_center = devm_regulator_get(dev, "center");
 415         if (IS_ERR(data->vdd_center)) {
 416                 dev_err(dev, "Cannot get the regulator \"center\"\n");
 417                 return PTR_ERR(data->vdd_center);
 418         }
 419
 420         data->dmc_clk = devm_clk_get(dev, "dmc_clk");
 421         if (IS_ERR(data->dmc_clk)) {
 422                 dev_err(dev, "Cannot get the clk dmc_clk\n");
 423                 return PTR_ERR(data->dmc_clk);
 424         };
 425
 426         data->irq = irq;
 427         ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
 428                                dev_name(dev), data);
 429         if (ret) {
 430                 dev_err(dev, "Failed to request dmc irq: %d\n", ret);
 431                 return ret;
 432         }
 433
 434         init_waitqueue_head(&data->wait_dcf_queue);
 435         data->wait_dcf_flag = 0;
 436
 437         data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
 438         if (IS_ERR(data->edev))
 439                 return -EPROBE_DEFER;
 440
 441         ret = devfreq_event_enable_edev(data->edev);
 442         if (ret < 0) {
 443                 dev_err(dev, "failed to enable devfreq-event devices\n");
 444                 return ret;
 445         }
 446
 447         /*
 448          * Get dram timing and pass it to arm trust firmware,
 449          * the dram drvier in arm trust firmware will get these
 450          * timing and to do dram initial.
 451          */
 452         data->timing = of_get_ddr_timings(dev, np);
 453         if (data->timing) {
 454                 timing = (uint32_t *)data->timing;
 455                 size = sizeof(struct dram_timing) / 4;
 456                 for (index = 0; index < size; index++) {
 457                         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
 458                                       ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
 459                                       0, 0, 0, 0, &res);
 460                         if (res.a0) {
 461                                 dev_err(dev, "Failed to set dram param: %ld\n",
 462                                         res.a0);
 463                                 return -EINVAL;
 464                         }
 465                 }
 466         }
 467
 468         arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
 469                       ROCKCHIP_SIP_CONFIG_DRAM_INIT,
 470                       0, 0, 0, 0, &res);
 471
 472         /*
 473          * We add a devfreq driver to our parent since it has a device tree node
 474          * with operating points.
 475          */
 476         if (dev_pm_opp_of_add_table(dev)) {
 477                 dev_err(dev, "Invalid operating-points in device tree.\n");
 478                 rcu_read_unlock();
 479                 return -EINVAL;
 480         }
 481
 482         if (of_get_opp_table(dev, devp))
 483                 return -EFAULT;
 484
 485         of_property_read_u32(np, "upthreshold",
 486                              &data->ondemand_data.upthreshold);
 487         of_property_read_u32(np, "downdifferential",
 488                              &data->ondemand_data.downdifferential);
 489
 490         data->rate = clk_get_rate(data->dmc_clk);
 491
 492         rcu_read_lock();
 493         opp = devfreq_recommended_opp(dev, &data->rate, 0);
 494         if (IS_ERR(opp)) {
 495                 rcu_read_unlock();
 496                 return PTR_ERR(opp);
 497         }
 498         rcu_read_unlock();
 499
 500         data->curr_opp = opp;
 501         devp->initial_freq = data->rate;
 502         data->devfreq = devfreq_add_device(dev, devp,
 503                                            "simple_ondemand",
 504                                            &data->ondemand_data);
 505         if (IS_ERR(data->devfreq))
 506                 return PTR_ERR(data->devfreq);
 507         devm_devfreq_register_opp_notifier(dev, data->devfreq);
 508
 509         data->dev = dev;
 510         platform_set_drvdata(pdev, data);
 511
 512         if (vop_register_dmc())
 513                 dev_err(dev, "fail to register notify to vop.\n");
 514
 515         return 0;
 516 }
 517
 518 static int rk3399_dmcfreq_remove(struct platform_device *pdev)
 519 {
 520         struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);
 521
 522         regulator_put(dmcfreq->vdd_center);
 523
 524         return 0;
 525 }
 526
 527 static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
 528         { .compatible = "rockchip,rk3399-dmc" },
 529         { },
 530 };
 531
 532 static struct platform_driver rk3399_dmcfreq_driver = {
 533         .probe  = rk3399_dmcfreq_probe,
 534         .remove = rk3399_dmcfreq_remove,
 535         .driver = {
 536                 .name   = "rk3399-dmc-freq",
 537                 .pm     = &rk3399_dmcfreq_pm,
 538                 .of_match_table = rk3399dmc_devfreq_of_match,
 539         },
 540 };
 541 module_platform_driver(rk3399_dmcfreq_driver);
 542
 543 MODULE_LICENSE("GPL v2");
 544 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
 545 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");