3 * Support for Nomadik hardware crypto engine.
5 * Copyright (C) ST-Ericsson SA 2010
6 * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson
7 * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
8 * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
9 * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
10 * Author: Andreas Westin <andreas.westin@stericsson.com> for ST-Ericsson.
11 * License terms: GNU General Public License (GPL) version 2
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/init.h>
19 #include <linux/klist.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/crypto.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/dmaengine.h>
27 #include <linux/bitops.h>
29 #include <crypto/internal/hash.h>
30 #include <crypto/sha.h>
31 #include <crypto/scatterwalk.h>
32 #include <crypto/algapi.h>
34 #include <linux/platform_data/crypto-ux500.h>
38 #define DEV_DBG_NAME "hashX hashX:"
41 module_param(hash_mode, int, 0);
42 MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1");
45 * Pre-calculated empty message digests.
47 static u8 zero_message_hash_sha1[SHA1_DIGEST_SIZE] = {
48 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d,
49 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90,
50 0xaf, 0xd8, 0x07, 0x09
53 static u8 zero_message_hash_sha256[SHA256_DIGEST_SIZE] = {
54 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
55 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
56 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
57 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55
60 /* HMAC-SHA1, no key */
61 static u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = {
62 0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08,
63 0x32, 0x4b, 0x7d, 0x64, 0xb7, 0x1f, 0xb7, 0x63,
64 0x70, 0x69, 0x0e, 0x1d
67 /* HMAC-SHA256, no key */
68 static u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = {
69 0xb6, 0x13, 0x67, 0x9a, 0x08, 0x14, 0xd9, 0xec,
70 0x77, 0x2f, 0x95, 0xd7, 0x78, 0xc3, 0x5f, 0xc5,
71 0xff, 0x16, 0x97, 0xc4, 0x93, 0x71, 0x56, 0x53,
72 0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad
76 * struct hash_driver_data - data specific to the driver.
78 * @device_list: A list of registered devices to choose from.
79 * @device_allocation: A semaphore initialized with number of devices.
81 struct hash_driver_data {
82 struct klist device_list;
83 struct semaphore device_allocation;
86 static struct hash_driver_data driver_data;
88 /* Declaration of functions */
90 * hash_messagepad - Pads a message and write the nblw bits.
91 * @device_data: Structure for the hash device.
92 * @message: Last word of a message
93 * @index_bytes: The number of bytes in the last message
95 * This function manages the final part of the digest calculation, when less
96 * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
99 static void hash_messagepad(struct hash_device_data *device_data,
100 const u32 *message, u8 index_bytes);
103 * release_hash_device - Releases a previously allocated hash device.
104 * @device_data: Structure for the hash device.
107 static void release_hash_device(struct hash_device_data *device_data)
109 spin_lock(&device_data->ctx_lock);
110 device_data->current_ctx->device = NULL;
111 device_data->current_ctx = NULL;
112 spin_unlock(&device_data->ctx_lock);
115 * The down_interruptible part for this semaphore is called in
116 * cryp_get_device_data.
118 up(&driver_data.device_allocation);
121 static void hash_dma_setup_channel(struct hash_device_data *device_data,
124 struct hash_platform_data *platform_data = dev->platform_data;
125 dma_cap_zero(device_data->dma.mask);
126 dma_cap_set(DMA_SLAVE, device_data->dma.mask);
128 device_data->dma.cfg_mem2hash = platform_data->mem_to_engine;
129 device_data->dma.chan_mem2hash =
130 dma_request_channel(device_data->dma.mask,
131 platform_data->dma_filter,
132 device_data->dma.cfg_mem2hash);
134 init_completion(&device_data->dma.complete);
137 static void hash_dma_callback(void *data)
139 struct hash_ctx *ctx = (struct hash_ctx *) data;
141 complete(&ctx->device->dma.complete);
144 static int hash_set_dma_transfer(struct hash_ctx *ctx, struct scatterlist *sg,
145 int len, enum dma_data_direction direction)
147 struct dma_async_tx_descriptor *desc = NULL;
148 struct dma_chan *channel = NULL;
151 if (direction != DMA_TO_DEVICE) {
152 dev_err(ctx->device->dev, "[%s] Invalid DMA direction",
157 sg->length = ALIGN(sg->length, HASH_DMA_ALIGN_SIZE);
159 channel = ctx->device->dma.chan_mem2hash;
160 ctx->device->dma.sg = sg;
161 ctx->device->dma.sg_len = dma_map_sg(channel->device->dev,
162 ctx->device->dma.sg, ctx->device->dma.nents,
165 if (!ctx->device->dma.sg_len) {
166 dev_err(ctx->device->dev,
167 "[%s]: Could not map the sg list (TO_DEVICE)",
172 dev_dbg(ctx->device->dev, "[%s]: Setting up DMA for buffer "
173 "(TO_DEVICE)", __func__);
174 desc = channel->device->device_prep_slave_sg(channel,
175 ctx->device->dma.sg, ctx->device->dma.sg_len,
176 direction, DMA_CTRL_ACK | DMA_PREP_INTERRUPT, NULL);
178 dev_err(ctx->device->dev,
179 "[%s]: device_prep_slave_sg() failed!", __func__);
183 desc->callback = hash_dma_callback;
184 desc->callback_param = ctx;
186 cookie = desc->tx_submit(desc);
187 dma_async_issue_pending(channel);
192 static void hash_dma_done(struct hash_ctx *ctx)
194 struct dma_chan *chan;
196 chan = ctx->device->dma.chan_mem2hash;
197 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
198 dma_unmap_sg(chan->device->dev, ctx->device->dma.sg,
199 ctx->device->dma.sg_len, DMA_TO_DEVICE);
203 static int hash_dma_write(struct hash_ctx *ctx,
204 struct scatterlist *sg, int len)
206 int error = hash_set_dma_transfer(ctx, sg, len, DMA_TO_DEVICE);
208 dev_dbg(ctx->device->dev, "[%s]: hash_set_dma_transfer() "
217 * get_empty_message_digest - Returns a pre-calculated digest for
219 * @device_data: Structure for the hash device.
220 * @zero_hash: Buffer to return the empty message digest.
221 * @zero_hash_size: Hash size of the empty message digest.
222 * @zero_digest: True if zero_digest returned.
224 static int get_empty_message_digest(
225 struct hash_device_data *device_data,
226 u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest)
229 struct hash_ctx *ctx = device_data->current_ctx;
230 *zero_digest = false;
233 * Caller responsible for ctx != NULL.
236 if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) {
237 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
238 memcpy(zero_hash, &zero_message_hash_sha1[0],
240 *zero_hash_size = SHA1_DIGEST_SIZE;
242 } else if (HASH_ALGO_SHA256 ==
243 ctx->config.algorithm) {
244 memcpy(zero_hash, &zero_message_hash_sha256[0],
246 *zero_hash_size = SHA256_DIGEST_SIZE;
249 dev_err(device_data->dev, "[%s] "
250 "Incorrect algorithm!"
255 } else if (HASH_OPER_MODE_HMAC == ctx->config.oper_mode) {
257 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
258 memcpy(zero_hash, &zero_message_hmac_sha1[0],
260 *zero_hash_size = SHA1_DIGEST_SIZE;
262 } else if (HASH_ALGO_SHA256 == ctx->config.algorithm) {
263 memcpy(zero_hash, &zero_message_hmac_sha256[0],
265 *zero_hash_size = SHA256_DIGEST_SIZE;
268 dev_err(device_data->dev, "[%s] "
269 "Incorrect algorithm!"
275 dev_dbg(device_data->dev, "[%s] Continue hash "
276 "calculation, since hmac key avalable",
286 * hash_disable_power - Request to disable power and clock.
287 * @device_data: Structure for the hash device.
288 * @save_device_state: If true, saves the current hw state.
290 * This function request for disabling power (regulator) and clock,
291 * and could also save current hw state.
293 static int hash_disable_power(
294 struct hash_device_data *device_data,
295 bool save_device_state)
298 struct device *dev = device_data->dev;
300 spin_lock(&device_data->power_state_lock);
301 if (!device_data->power_state)
304 if (save_device_state) {
305 hash_save_state(device_data,
306 &device_data->state);
307 device_data->restore_dev_state = true;
310 clk_disable(device_data->clk);
311 ret = regulator_disable(device_data->regulator);
313 dev_err(dev, "[%s] regulator_disable() failed!", __func__);
315 device_data->power_state = false;
318 spin_unlock(&device_data->power_state_lock);
324 * hash_enable_power - Request to enable power and clock.
325 * @device_data: Structure for the hash device.
326 * @restore_device_state: If true, restores a previous saved hw state.
328 * This function request for enabling power (regulator) and clock,
329 * and could also restore a previously saved hw state.
331 static int hash_enable_power(
332 struct hash_device_data *device_data,
333 bool restore_device_state)
336 struct device *dev = device_data->dev;
338 spin_lock(&device_data->power_state_lock);
339 if (!device_data->power_state) {
340 ret = regulator_enable(device_data->regulator);
342 dev_err(dev, "[%s]: regulator_enable() failed!",
346 ret = clk_enable(device_data->clk);
348 dev_err(dev, "[%s]: clk_enable() failed!",
350 ret = regulator_disable(
351 device_data->regulator);
354 device_data->power_state = true;
357 if (device_data->restore_dev_state) {
358 if (restore_device_state) {
359 device_data->restore_dev_state = false;
360 hash_resume_state(device_data,
361 &device_data->state);
365 spin_unlock(&device_data->power_state_lock);
371 * hash_get_device_data - Checks for an available hash device and return it.
372 * @hash_ctx: Structure for the hash context.
373 * @device_data: Structure for the hash device.
375 * This function check for an available hash device and return it to
377 * Note! Caller need to release the device, calling up().
379 static int hash_get_device_data(struct hash_ctx *ctx,
380 struct hash_device_data **device_data)
383 struct klist_iter device_iterator;
384 struct klist_node *device_node;
385 struct hash_device_data *local_device_data = NULL;
387 /* Wait until a device is available */
388 ret = down_interruptible(&driver_data.device_allocation);
390 return ret; /* Interrupted */
392 /* Select a device */
393 klist_iter_init(&driver_data.device_list, &device_iterator);
394 device_node = klist_next(&device_iterator);
395 while (device_node) {
396 local_device_data = container_of(device_node,
397 struct hash_device_data, list_node);
398 spin_lock(&local_device_data->ctx_lock);
399 /* current_ctx allocates a device, NULL = unallocated */
400 if (local_device_data->current_ctx) {
401 device_node = klist_next(&device_iterator);
403 local_device_data->current_ctx = ctx;
404 ctx->device = local_device_data;
405 spin_unlock(&local_device_data->ctx_lock);
408 spin_unlock(&local_device_data->ctx_lock);
410 klist_iter_exit(&device_iterator);
414 * No free device found.
415 * Since we allocated a device with down_interruptible, this
416 * should not be able to happen.
417 * Number of available devices, which are contained in
418 * device_allocation, is therefore decremented by not doing
419 * an up(device_allocation).
424 *device_data = local_device_data;
430 * hash_hw_write_key - Writes the key to the hardware registries.
432 * @device_data: Structure for the hash device.
433 * @key: Key to be written.
434 * @keylen: The lengt of the key.
436 * Note! This function DOES NOT write to the NBLW registry, even though
437 * specified in the the hw design spec. Either due to incorrect info in the
438 * spec or due to a bug in the hw.
440 static void hash_hw_write_key(struct hash_device_data *device_data,
441 const u8 *key, unsigned int keylen)
446 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
448 while (keylen >= 4) {
449 u32 *key_word = (u32 *)key;
451 HASH_SET_DIN(key_word, nwords);
456 /* Take care of the remaining bytes in the last word */
460 word |= (key[keylen - 1] << (8 * (keylen - 1)));
464 HASH_SET_DIN(&word, nwords);
467 while (device_data->base->str & HASH_STR_DCAL_MASK)
472 while (device_data->base->str & HASH_STR_DCAL_MASK)
477 * init_hash_hw - Initialise the hash hardware for a new calculation.
478 * @device_data: Structure for the hash device.
479 * @ctx: The hash context.
481 * This function will enable the bits needed to clear and start a new
484 static int init_hash_hw(struct hash_device_data *device_data,
485 struct hash_ctx *ctx)
489 ret = hash_setconfiguration(device_data, &ctx->config);
491 dev_err(device_data->dev, "[%s] hash_setconfiguration() "
492 "failed!", __func__);
496 hash_begin(device_data, ctx);
498 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
499 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
505 * hash_get_nents - Return number of entries (nents) in scatterlist (sg).
508 * @size: Size in bytes.
509 * @aligned: True if sg data aligned to work in DMA mode.
512 static int hash_get_nents(struct scatterlist *sg, int size, bool *aligned)
515 bool aligned_data = true;
517 while (size > 0 && sg) {
521 /* hash_set_dma_transfer will align last nent */
522 if ((aligned && !IS_ALIGNED(sg->offset, HASH_DMA_ALIGN_SIZE))
523 || (!IS_ALIGNED(sg->length, HASH_DMA_ALIGN_SIZE) &&
525 aligned_data = false;
531 *aligned = aligned_data;
540 * hash_dma_valid_data - checks for dma valid sg data.
542 * @datasize: Datasize in bytes.
544 * NOTE! This function checks for dma valid sg data, since dma
545 * only accept datasizes of even wordsize.
547 static bool hash_dma_valid_data(struct scatterlist *sg, int datasize)
551 /* Need to include at least one nent, else error */
552 if (hash_get_nents(sg, datasize, &aligned) < 1)
559 * hash_init - Common hash init function for SHA1/SHA2 (SHA256).
560 * @req: The hash request for the job.
562 * Initialize structures.
564 static int hash_init(struct ahash_request *req)
566 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
567 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
568 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
573 memset(&req_ctx->state, 0, sizeof(struct hash_state));
574 req_ctx->updated = 0;
575 if (hash_mode == HASH_MODE_DMA) {
576 if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
577 req_ctx->dma_mode = false; /* Don't use DMA */
579 pr_debug(DEV_DBG_NAME " [%s] DMA mode, but direct "
580 "to CPU mode for data size < %d",
581 __func__, HASH_DMA_ALIGN_SIZE);
583 if (req->nbytes >= HASH_DMA_PERFORMANCE_MIN_SIZE &&
584 hash_dma_valid_data(req->src,
586 req_ctx->dma_mode = true;
588 req_ctx->dma_mode = false;
589 pr_debug(DEV_DBG_NAME " [%s] DMA mode, but use"
590 " CPU mode for datalength < %d"
591 " or non-aligned data, except "
592 "in last nent", __func__,
593 HASH_DMA_PERFORMANCE_MIN_SIZE);
601 * hash_processblock - This function processes a single block of 512 bits (64
602 * bytes), word aligned, starting at message.
603 * @device_data: Structure for the hash device.
604 * @message: Block (512 bits) of message to be written to
608 static void hash_processblock(
609 struct hash_device_data *device_data,
610 const u32 *message, int length)
612 int len = length / HASH_BYTES_PER_WORD;
614 * NBLW bits. Reset the number of bits in last word (NBLW).
616 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
619 * Write message data to the HASH_DIN register.
621 HASH_SET_DIN(message, len);
625 * hash_messagepad - Pads a message and write the nblw bits.
626 * @device_data: Structure for the hash device.
627 * @message: Last word of a message.
628 * @index_bytes: The number of bytes in the last message.
630 * This function manages the final part of the digest calculation, when less
631 * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
634 static void hash_messagepad(struct hash_device_data *device_data,
635 const u32 *message, u8 index_bytes)
640 * Clear hash str register, only clear NBLW
641 * since DCAL will be reset by hardware.
643 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
646 while (index_bytes >= 4) {
647 HASH_SET_DIN(message, nwords);
653 HASH_SET_DIN(message, nwords);
655 while (device_data->base->str & HASH_STR_DCAL_MASK)
658 /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */
659 HASH_SET_NBLW(index_bytes * 8);
660 dev_dbg(device_data->dev, "[%s] DIN=0x%08x NBLW=%d", __func__,
661 readl_relaxed(&device_data->base->din),
662 (int)(readl_relaxed(&device_data->base->str) &
663 HASH_STR_NBLW_MASK));
665 dev_dbg(device_data->dev, "[%s] after dcal -> DIN=0x%08x NBLW=%d",
666 __func__, readl_relaxed(&device_data->base->din),
667 (int)(readl_relaxed(&device_data->base->str) &
668 HASH_STR_NBLW_MASK));
670 while (device_data->base->str & HASH_STR_DCAL_MASK)
675 * hash_incrementlength - Increments the length of the current message.
677 * @incr: Length of message processed already
679 * Overflow cannot occur, because conditions for overflow are checked in
682 static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
684 ctx->state.length.low_word += incr;
686 /* Check for wrap-around */
687 if (ctx->state.length.low_word < incr)
688 ctx->state.length.high_word++;
692 * hash_setconfiguration - Sets the required configuration for the hash
694 * @device_data: Structure for the hash device.
695 * @config: Pointer to a configuration structure.
697 int hash_setconfiguration(struct hash_device_data *device_data,
698 struct hash_config *config)
702 if (config->algorithm != HASH_ALGO_SHA1 &&
703 config->algorithm != HASH_ALGO_SHA256)
707 * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data
708 * to be written to HASH_DIN is considered as 32 bits.
710 HASH_SET_DATA_FORMAT(config->data_format);
713 * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256
715 switch (config->algorithm) {
717 HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
720 case HASH_ALGO_SHA256:
721 HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
725 dev_err(device_data->dev, "[%s] Incorrect algorithm.",
731 * MODE bit. This bit selects between HASH or HMAC mode for the
732 * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
734 if (HASH_OPER_MODE_HASH == config->oper_mode)
735 HASH_CLEAR_BITS(&device_data->base->cr,
737 else if (HASH_OPER_MODE_HMAC == config->oper_mode) {
738 HASH_SET_BITS(&device_data->base->cr,
740 if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) {
741 /* Truncate key to blocksize */
742 dev_dbg(device_data->dev, "[%s] LKEY set", __func__);
743 HASH_SET_BITS(&device_data->base->cr,
746 dev_dbg(device_data->dev, "[%s] LKEY cleared",
748 HASH_CLEAR_BITS(&device_data->base->cr,
751 } else { /* Wrong hash mode */
753 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
760 * hash_begin - This routine resets some globals and initializes the hash
762 * @device_data: Structure for the hash device.
763 * @ctx: Hash context.
765 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx)
767 /* HW and SW initializations */
768 /* Note: there is no need to initialize buffer and digest members */
770 while (device_data->base->str & HASH_STR_DCAL_MASK)
774 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
775 * prepare the initialize the HASH accelerator to compute the message
776 * digest of a new message.
781 * NBLW bits. Reset the number of bits in last word (NBLW).
783 HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
786 int hash_process_data(
787 struct hash_device_data *device_data,
788 struct hash_ctx *ctx, struct hash_req_ctx *req_ctx,
789 int msg_length, u8 *data_buffer, u8 *buffer, u8 *index)
795 if ((*index + msg_length) < HASH_BLOCK_SIZE) {
796 for (count = 0; count < msg_length; count++) {
797 buffer[*index + count] =
798 *(data_buffer + count);
800 *index += msg_length;
803 if (req_ctx->updated) {
805 ret = hash_resume_state(device_data,
806 &device_data->state);
807 memmove(req_ctx->state.buffer,
808 device_data->state.buffer,
809 HASH_BLOCK_SIZE / sizeof(u32));
811 dev_err(device_data->dev, "[%s] "
812 "hash_resume_state()"
813 " failed!", __func__);
817 ret = init_hash_hw(device_data, ctx);
819 dev_err(device_data->dev, "[%s] "
821 " failed!", __func__);
824 req_ctx->updated = 1;
827 * If 'data_buffer' is four byte aligned and
828 * local buffer does not have any data, we can
829 * write data directly from 'data_buffer' to
830 * HW peripheral, otherwise we first copy data
833 if ((0 == (((u32)data_buffer) % 4))
835 hash_processblock(device_data,
837 data_buffer, HASH_BLOCK_SIZE);
839 for (count = 0; count <
840 (u32)(HASH_BLOCK_SIZE -
843 buffer[*index + count] =
844 *(data_buffer + count);
846 hash_processblock(device_data,
850 hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
851 data_buffer += (HASH_BLOCK_SIZE - *index);
853 msg_length -= (HASH_BLOCK_SIZE - *index);
856 ret = hash_save_state(device_data,
857 &device_data->state);
859 memmove(device_data->state.buffer,
860 req_ctx->state.buffer,
861 HASH_BLOCK_SIZE / sizeof(u32));
863 dev_err(device_data->dev, "[%s] "
865 " failed!", __func__);
869 } while (msg_length != 0);
876 * hash_dma_final - The hash dma final function for SHA1/SHA256.
877 * @req: The hash request for the job.
879 static int hash_dma_final(struct ahash_request *req)
882 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
883 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
884 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
885 struct hash_device_data *device_data;
886 u8 digest[SHA256_DIGEST_SIZE];
887 int bytes_written = 0;
889 ret = hash_get_device_data(ctx, &device_data);
893 dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
895 if (req_ctx->updated) {
896 ret = hash_resume_state(device_data, &device_data->state);
899 dev_err(device_data->dev, "[%s] hash_resume_state() "
900 "failed!", __func__);
906 if (!req_ctx->updated) {
907 ret = hash_setconfiguration(device_data, &ctx->config);
909 dev_err(device_data->dev, "[%s] "
910 "hash_setconfiguration() failed!",
915 /* Enable DMA input */
916 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) {
917 HASH_CLEAR_BITS(&device_data->base->cr,
920 HASH_SET_BITS(&device_data->base->cr,
922 HASH_SET_BITS(&device_data->base->cr,
928 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
929 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
931 /* Number of bits in last word = (nbytes * 8) % 32 */
932 HASH_SET_NBLW((req->nbytes * 8) % 32);
933 req_ctx->updated = 1;
936 /* Store the nents in the dma struct. */
937 ctx->device->dma.nents = hash_get_nents(req->src, req->nbytes, NULL);
938 if (!ctx->device->dma.nents) {
939 dev_err(device_data->dev, "[%s] "
940 "ctx->device->dma.nents = 0", __func__);
941 ret = ctx->device->dma.nents;
945 bytes_written = hash_dma_write(ctx, req->src, req->nbytes);
946 if (bytes_written != req->nbytes) {
947 dev_err(device_data->dev, "[%s] "
948 "hash_dma_write() failed!", __func__);
953 wait_for_completion(&ctx->device->dma.complete);
956 while (device_data->base->str & HASH_STR_DCAL_MASK)
959 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
960 unsigned int keylen = ctx->keylen;
963 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
965 hash_hw_write_key(device_data, key, keylen);
968 hash_get_digest(device_data, digest, ctx->config.algorithm);
969 memcpy(req->result, digest, ctx->digestsize);
972 release_hash_device(device_data);
975 * Allocated in setkey, and only used in HMAC.
983 * hash_hw_final - The final hash calculation function
984 * @req: The hash request for the job.
986 int hash_hw_final(struct ahash_request *req)
989 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
990 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
991 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
992 struct hash_device_data *device_data;
993 u8 digest[SHA256_DIGEST_SIZE];
995 ret = hash_get_device_data(ctx, &device_data);
999 dev_dbg(device_data->dev, "[%s] (ctx=0x%x)!", __func__, (u32) ctx);
1001 if (req_ctx->updated) {
1002 ret = hash_resume_state(device_data, &device_data->state);
1005 dev_err(device_data->dev, "[%s] hash_resume_state() "
1006 "failed!", __func__);
1009 } else if (req->nbytes == 0 && ctx->keylen == 0) {
1010 u8 zero_hash[SHA256_DIGEST_SIZE];
1011 u32 zero_hash_size = 0;
1012 bool zero_digest = false;
1014 * Use a pre-calculated empty message digest
1015 * (workaround since hw return zeroes, hw bug!?)
1017 ret = get_empty_message_digest(device_data, &zero_hash[0],
1018 &zero_hash_size, &zero_digest);
1019 if (!ret && likely(zero_hash_size == ctx->digestsize) &&
1021 memcpy(req->result, &zero_hash[0], ctx->digestsize);
1023 } else if (!ret && !zero_digest) {
1024 dev_dbg(device_data->dev, "[%s] HMAC zero msg with "
1025 "key, continue...", __func__);
1027 dev_err(device_data->dev, "[%s] ret=%d, or wrong "
1028 "digest size? %s", __func__, ret,
1029 (zero_hash_size == ctx->digestsize) ?
1034 } else if (req->nbytes == 0 && ctx->keylen > 0) {
1035 dev_err(device_data->dev, "[%s] Empty message with "
1036 "keylength > 0, NOT supported.", __func__);
1040 if (!req_ctx->updated) {
1041 ret = init_hash_hw(device_data, ctx);
1043 dev_err(device_data->dev, "[%s] init_hash_hw() "
1044 "failed!", __func__);
1049 if (req_ctx->state.index) {
1050 hash_messagepad(device_data, req_ctx->state.buffer,
1051 req_ctx->state.index);
1054 while (device_data->base->str & HASH_STR_DCAL_MASK)
1058 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
1059 unsigned int keylen = ctx->keylen;
1062 dev_dbg(device_data->dev, "[%s] keylen: %d", __func__,
1064 hash_hw_write_key(device_data, key, keylen);
1067 hash_get_digest(device_data, digest, ctx->config.algorithm);
1068 memcpy(req->result, digest, ctx->digestsize);
1071 release_hash_device(device_data);
1074 * Allocated in setkey, and only used in HMAC.
1082 * hash_hw_update - Updates current HASH computation hashing another part of
1084 * @req: Byte array containing the message to be hashed (caller
1087 int hash_hw_update(struct ahash_request *req)
1092 struct hash_device_data *device_data;
1094 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1095 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1096 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1097 struct crypto_hash_walk walk;
1098 int msg_length = crypto_hash_walk_first(req, &walk);
1100 /* Empty message ("") is correct indata */
1101 if (msg_length == 0)
1104 index = req_ctx->state.index;
1105 buffer = (u8 *)req_ctx->state.buffer;
1107 /* Check if ctx->state.length + msg_length
1109 if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
1110 HASH_HIGH_WORD_MAX_VAL ==
1111 req_ctx->state.length.high_word) {
1112 pr_err(DEV_DBG_NAME " [%s] HASH_MSG_LENGTH_OVERFLOW!",
1117 ret = hash_get_device_data(ctx, &device_data);
1122 while (0 != msg_length) {
1123 data_buffer = walk.data;
1124 ret = hash_process_data(device_data, ctx, req_ctx, msg_length,
1125 data_buffer, buffer, &index);
1128 dev_err(device_data->dev, "[%s] hash_internal_hw_"
1129 "update() failed!", __func__);
1133 msg_length = crypto_hash_walk_done(&walk, 0);
1136 req_ctx->state.index = index;
1137 dev_dbg(device_data->dev, "[%s] indata length=%d, bin=%d))",
1138 __func__, req_ctx->state.index,
1139 req_ctx->state.bit_index);
1142 release_hash_device(device_data);
1148 * hash_resume_state - Function that resumes the state of an calculation.
1149 * @device_data: Pointer to the device structure.
1150 * @device_state: The state to be restored in the hash hardware
1152 int hash_resume_state(struct hash_device_data *device_data,
1153 const struct hash_state *device_state)
1157 int hash_mode = HASH_OPER_MODE_HASH;
1159 if (NULL == device_state) {
1160 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1165 /* Check correctness of index and length members */
1166 if (device_state->index > HASH_BLOCK_SIZE
1167 || (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) {
1168 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1174 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
1175 * prepare the initialize the HASH accelerator to compute the message
1176 * digest of a new message.
1180 temp_cr = device_state->temp_cr;
1181 writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
1183 if (device_data->base->cr & HASH_CR_MODE_MASK)
1184 hash_mode = HASH_OPER_MODE_HMAC;
1186 hash_mode = HASH_OPER_MODE_HASH;
1188 for (count = 0; count < HASH_CSR_COUNT; count++) {
1189 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1192 writel_relaxed(device_state->csr[count],
1193 &device_data->base->csrx[count]);
1196 writel_relaxed(device_state->csfull, &device_data->base->csfull);
1197 writel_relaxed(device_state->csdatain, &device_data->base->csdatain);
1199 writel_relaxed(device_state->str_reg, &device_data->base->str);
1200 writel_relaxed(temp_cr, &device_data->base->cr);
1206 * hash_save_state - Function that saves the state of hardware.
1207 * @device_data: Pointer to the device structure.
1208 * @device_state: The strucure where the hardware state should be saved.
1210 int hash_save_state(struct hash_device_data *device_data,
1211 struct hash_state *device_state)
1215 int hash_mode = HASH_OPER_MODE_HASH;
1217 if (NULL == device_state) {
1218 dev_err(device_data->dev, "[%s] HASH_INVALID_PARAMETER!",
1223 /* Write dummy value to force digest intermediate calculation. This
1224 * actually makes sure that there isn't any ongoing calculation in the
1227 while (device_data->base->str & HASH_STR_DCAL_MASK)
1230 temp_cr = readl_relaxed(&device_data->base->cr);
1232 device_state->str_reg = readl_relaxed(&device_data->base->str);
1234 device_state->din_reg = readl_relaxed(&device_data->base->din);
1236 if (device_data->base->cr & HASH_CR_MODE_MASK)
1237 hash_mode = HASH_OPER_MODE_HMAC;
1239 hash_mode = HASH_OPER_MODE_HASH;
1241 for (count = 0; count < HASH_CSR_COUNT; count++) {
1242 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1245 device_state->csr[count] =
1246 readl_relaxed(&device_data->base->csrx[count]);
1249 device_state->csfull = readl_relaxed(&device_data->base->csfull);
1250 device_state->csdatain = readl_relaxed(&device_data->base->csdatain);
1252 device_state->temp_cr = temp_cr;
1258 * hash_check_hw - This routine checks for peripheral Ids and PCell Ids.
1262 int hash_check_hw(struct hash_device_data *device_data)
1264 /* Checking Peripheral Ids */
1265 if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0)
1266 && HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1)
1267 && HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2)
1268 && HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3)
1269 && HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0)
1270 && HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1)
1271 && HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2)
1272 && HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)
1277 dev_err(device_data->dev, "[%s] HASH_UNSUPPORTED_HW!",
1283 * hash_get_digest - Gets the digest.
1284 * @device_data: Pointer to the device structure.
1285 * @digest: User allocated byte array for the calculated digest.
1286 * @algorithm: The algorithm in use.
1288 void hash_get_digest(struct hash_device_data *device_data,
1289 u8 *digest, int algorithm)
1291 u32 temp_hx_val, count;
1294 if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) {
1295 dev_err(device_data->dev, "[%s] Incorrect algorithm %d",
1296 __func__, algorithm);
1300 if (algorithm == HASH_ALGO_SHA1)
1301 loop_ctr = SHA1_DIGEST_SIZE / sizeof(u32);
1303 loop_ctr = SHA256_DIGEST_SIZE / sizeof(u32);
1305 dev_dbg(device_data->dev, "[%s] digest array:(0x%x)",
1306 __func__, (u32) digest);
1308 /* Copy result into digest array */
1309 for (count = 0; count < loop_ctr; count++) {
1310 temp_hx_val = readl_relaxed(&device_data->base->hx[count]);
1311 digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF);
1312 digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF);
1313 digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF);
1314 digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF);
1319 * hash_update - The hash update function for SHA1/SHA2 (SHA256).
1320 * @req: The hash request for the job.
1322 static int ahash_update(struct ahash_request *req)
1325 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1327 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode)
1328 ret = hash_hw_update(req);
1329 /* Skip update for DMA, all data will be passed to DMA in final */
1332 pr_err(DEV_DBG_NAME " [%s] hash_hw_update() failed!",
1340 * hash_final - The hash final function for SHA1/SHA2 (SHA256).
1341 * @req: The hash request for the job.
1343 static int ahash_final(struct ahash_request *req)
1346 struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1348 pr_debug(DEV_DBG_NAME " [%s] data size: %d", __func__, req->nbytes);
1350 if ((hash_mode == HASH_MODE_DMA) && req_ctx->dma_mode)
1351 ret = hash_dma_final(req);
1353 ret = hash_hw_final(req);
1356 pr_err(DEV_DBG_NAME " [%s] hash_hw/dma_final() failed",
1363 static int hash_setkey(struct crypto_ahash *tfm,
1364 const u8 *key, unsigned int keylen, int alg)
1367 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1372 ctx->key = kmemdup(key, keylen, GFP_KERNEL);
1374 pr_err(DEV_DBG_NAME " [%s] Failed to allocate ctx->key "
1375 "for %d\n", __func__, alg);
1378 ctx->keylen = keylen;
1383 static int ahash_sha1_init(struct ahash_request *req)
1385 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1386 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1388 ctx->config.data_format = HASH_DATA_8_BITS;
1389 ctx->config.algorithm = HASH_ALGO_SHA1;
1390 ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1391 ctx->digestsize = SHA1_DIGEST_SIZE;
1393 return hash_init(req);
1396 static int ahash_sha256_init(struct ahash_request *req)
1398 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1399 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1401 ctx->config.data_format = HASH_DATA_8_BITS;
1402 ctx->config.algorithm = HASH_ALGO_SHA256;
1403 ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1404 ctx->digestsize = SHA256_DIGEST_SIZE;
1406 return hash_init(req);
1409 static int ahash_sha1_digest(struct ahash_request *req)
1413 ret1 = ahash_sha1_init(req);
1417 ret1 = ahash_update(req);
1418 ret2 = ahash_final(req);
1421 return ret1 ? ret1 : ret2;
1424 static int ahash_sha256_digest(struct ahash_request *req)
1428 ret1 = ahash_sha256_init(req);
1432 ret1 = ahash_update(req);
1433 ret2 = ahash_final(req);
1436 return ret1 ? ret1 : ret2;
1439 static int hmac_sha1_init(struct ahash_request *req)
1441 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1442 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1444 ctx->config.data_format = HASH_DATA_8_BITS;
1445 ctx->config.algorithm = HASH_ALGO_SHA1;
1446 ctx->config.oper_mode = HASH_OPER_MODE_HMAC;
1447 ctx->digestsize = SHA1_DIGEST_SIZE;
1449 return hash_init(req);
1452 static int hmac_sha256_init(struct ahash_request *req)
1454 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1455 struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1457 ctx->config.data_format = HASH_DATA_8_BITS;
1458 ctx->config.algorithm = HASH_ALGO_SHA256;
1459 ctx->config.oper_mode = HASH_OPER_MODE_HMAC;
1460 ctx->digestsize = SHA256_DIGEST_SIZE;
1462 return hash_init(req);
1465 static int hmac_sha1_digest(struct ahash_request *req)
1469 ret1 = hmac_sha1_init(req);
1473 ret1 = ahash_update(req);
1474 ret2 = ahash_final(req);
1477 return ret1 ? ret1 : ret2;
1480 static int hmac_sha256_digest(struct ahash_request *req)
1484 ret1 = hmac_sha256_init(req);
1488 ret1 = ahash_update(req);
1489 ret2 = ahash_final(req);
1492 return ret1 ? ret1 : ret2;
1495 static int hmac_sha1_setkey(struct crypto_ahash *tfm,
1496 const u8 *key, unsigned int keylen)
1498 return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA1);
1501 static int hmac_sha256_setkey(struct crypto_ahash *tfm,
1502 const u8 *key, unsigned int keylen)
1504 return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA256);
1507 struct hash_algo_template {
1508 struct hash_config conf;
1509 struct ahash_alg hash;
1512 static int hash_cra_init(struct crypto_tfm *tfm)
1514 struct hash_ctx *ctx = crypto_tfm_ctx(tfm);
1515 struct crypto_alg *alg = tfm->__crt_alg;
1516 struct hash_algo_template *hash_alg;
1518 hash_alg = container_of(__crypto_ahash_alg(alg),
1519 struct hash_algo_template,
1522 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1523 sizeof(struct hash_req_ctx));
1525 ctx->config.data_format = HASH_DATA_8_BITS;
1526 ctx->config.algorithm = hash_alg->conf.algorithm;
1527 ctx->config.oper_mode = hash_alg->conf.oper_mode;
1529 ctx->digestsize = hash_alg->hash.halg.digestsize;
1534 static struct hash_algo_template hash_algs[] = {
1536 .conf.algorithm = HASH_ALGO_SHA1,
1537 .conf.oper_mode = HASH_OPER_MODE_HASH,
1540 .update = ahash_update,
1541 .final = ahash_final,
1542 .digest = ahash_sha1_digest,
1543 .halg.digestsize = SHA1_DIGEST_SIZE,
1544 .halg.statesize = sizeof(struct hash_ctx),
1547 .cra_driver_name = "sha1-ux500",
1548 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1550 .cra_blocksize = SHA1_BLOCK_SIZE,
1551 .cra_ctxsize = sizeof(struct hash_ctx),
1552 .cra_init = hash_cra_init,
1553 .cra_module = THIS_MODULE,
1558 .conf.algorithm = HASH_ALGO_SHA256,
1559 .conf.oper_mode = HASH_OPER_MODE_HASH,
1562 .update = ahash_update,
1563 .final = ahash_final,
1564 .digest = ahash_sha256_digest,
1565 .halg.digestsize = SHA256_DIGEST_SIZE,
1566 .halg.statesize = sizeof(struct hash_ctx),
1568 .cra_name = "sha256",
1569 .cra_driver_name = "sha256-ux500",
1570 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1572 .cra_blocksize = SHA256_BLOCK_SIZE,
1573 .cra_ctxsize = sizeof(struct hash_ctx),
1574 .cra_type = &crypto_ahash_type,
1575 .cra_init = hash_cra_init,
1576 .cra_module = THIS_MODULE,
1582 .conf.algorithm = HASH_ALGO_SHA1,
1583 .conf.oper_mode = HASH_OPER_MODE_HMAC,
1586 .update = ahash_update,
1587 .final = ahash_final,
1588 .digest = hmac_sha1_digest,
1589 .setkey = hmac_sha1_setkey,
1590 .halg.digestsize = SHA1_DIGEST_SIZE,
1591 .halg.statesize = sizeof(struct hash_ctx),
1593 .cra_name = "hmac(sha1)",
1594 .cra_driver_name = "hmac-sha1-ux500",
1595 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1597 .cra_blocksize = SHA1_BLOCK_SIZE,
1598 .cra_ctxsize = sizeof(struct hash_ctx),
1599 .cra_type = &crypto_ahash_type,
1600 .cra_init = hash_cra_init,
1601 .cra_module = THIS_MODULE,
1606 .conf.algorithm = HASH_ALGO_SHA256,
1607 .conf.oper_mode = HASH_OPER_MODE_HMAC,
1610 .update = ahash_update,
1611 .final = ahash_final,
1612 .digest = hmac_sha256_digest,
1613 .setkey = hmac_sha256_setkey,
1614 .halg.digestsize = SHA256_DIGEST_SIZE,
1615 .halg.statesize = sizeof(struct hash_ctx),
1617 .cra_name = "hmac(sha256)",
1618 .cra_driver_name = "hmac-sha256-ux500",
1619 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1621 .cra_blocksize = SHA256_BLOCK_SIZE,
1622 .cra_ctxsize = sizeof(struct hash_ctx),
1623 .cra_type = &crypto_ahash_type,
1624 .cra_init = hash_cra_init,
1625 .cra_module = THIS_MODULE,
1632 * hash_algs_register_all -
1634 static int ahash_algs_register_all(struct hash_device_data *device_data)
1640 for (i = 0; i < ARRAY_SIZE(hash_algs); i++) {
1641 ret = crypto_register_ahash(&hash_algs[i].hash);
1644 dev_err(device_data->dev, "[%s] alg registration failed",
1645 hash_algs[i].hash.halg.base.cra_driver_name);
1651 for (i = 0; i < count; i++)
1652 crypto_unregister_ahash(&hash_algs[i].hash);
1657 * hash_algs_unregister_all -
1659 static void ahash_algs_unregister_all(struct hash_device_data *device_data)
1663 for (i = 0; i < ARRAY_SIZE(hash_algs); i++)
1664 crypto_unregister_ahash(&hash_algs[i].hash);
1668 * ux500_hash_probe - Function that probes the hash hardware.
1669 * @pdev: The platform device.
1671 static int ux500_hash_probe(struct platform_device *pdev)
1674 struct resource *res = NULL;
1675 struct hash_device_data *device_data;
1676 struct device *dev = &pdev->dev;
1678 device_data = kzalloc(sizeof(struct hash_device_data), GFP_ATOMIC);
1680 dev_dbg(dev, "[%s] kzalloc() failed!", __func__);
1685 device_data->dev = dev;
1686 device_data->current_ctx = NULL;
1688 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1690 dev_dbg(dev, "[%s] platform_get_resource() failed!", __func__);
1695 res = request_mem_region(res->start, resource_size(res), pdev->name);
1697 dev_dbg(dev, "[%s] request_mem_region() failed!", __func__);
1702 device_data->base = ioremap(res->start, resource_size(res));
1703 if (!device_data->base) {
1704 dev_err(dev, "[%s] ioremap() failed!",
1709 spin_lock_init(&device_data->ctx_lock);
1710 spin_lock_init(&device_data->power_state_lock);
1712 /* Enable power for HASH1 hardware block */
1713 device_data->regulator = regulator_get(dev, "v-ape");
1714 if (IS_ERR(device_data->regulator)) {
1715 dev_err(dev, "[%s] regulator_get() failed!", __func__);
1716 ret = PTR_ERR(device_data->regulator);
1717 device_data->regulator = NULL;
1721 /* Enable the clock for HASH1 hardware block */
1722 device_data->clk = clk_get(dev, NULL);
1723 if (IS_ERR(device_data->clk)) {
1724 dev_err(dev, "[%s] clk_get() failed!", __func__);
1725 ret = PTR_ERR(device_data->clk);
1729 /* Enable device power (and clock) */
1730 ret = hash_enable_power(device_data, false);
1732 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1736 ret = hash_check_hw(device_data);
1738 dev_err(dev, "[%s] hash_check_hw() failed!", __func__);
1742 if (hash_mode == HASH_MODE_DMA)
1743 hash_dma_setup_channel(device_data, dev);
1745 platform_set_drvdata(pdev, device_data);
1747 /* Put the new device into the device list... */
1748 klist_add_tail(&device_data->list_node, &driver_data.device_list);
1749 /* ... and signal that a new device is available. */
1750 up(&driver_data.device_allocation);
1752 ret = ahash_algs_register_all(device_data);
1754 dev_err(dev, "[%s] ahash_algs_register_all() "
1755 "failed!", __func__);
1759 dev_info(dev, "[%s] successfully probed\n", __func__);
1763 hash_disable_power(device_data, false);
1766 clk_put(device_data->clk);
1769 regulator_put(device_data->regulator);
1772 iounmap(device_data->base);
1775 release_mem_region(res->start, resource_size(res));
1784 * ux500_hash_remove - Function that removes the hash device from the platform.
1785 * @pdev: The platform device.
1787 static int ux500_hash_remove(struct platform_device *pdev)
1789 struct resource *res;
1790 struct hash_device_data *device_data;
1791 struct device *dev = &pdev->dev;
1793 device_data = platform_get_drvdata(pdev);
1795 dev_err(dev, "[%s]: platform_get_drvdata() failed!",
1800 /* Try to decrease the number of available devices. */
1801 if (down_trylock(&driver_data.device_allocation))
1804 /* Check that the device is free */
1805 spin_lock(&device_data->ctx_lock);
1806 /* current_ctx allocates a device, NULL = unallocated */
1807 if (device_data->current_ctx) {
1808 /* The device is busy */
1809 spin_unlock(&device_data->ctx_lock);
1810 /* Return the device to the pool. */
1811 up(&driver_data.device_allocation);
1815 spin_unlock(&device_data->ctx_lock);
1817 /* Remove the device from the list */
1818 if (klist_node_attached(&device_data->list_node))
1819 klist_remove(&device_data->list_node);
1821 /* If this was the last device, remove the services */
1822 if (list_empty(&driver_data.device_list.k_list))
1823 ahash_algs_unregister_all(device_data);
1825 if (hash_disable_power(device_data, false))
1826 dev_err(dev, "[%s]: hash_disable_power() failed",
1829 clk_put(device_data->clk);
1830 regulator_put(device_data->regulator);
1832 iounmap(device_data->base);
1834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1836 release_mem_region(res->start, resource_size(res));
1844 * ux500_hash_shutdown - Function that shutdown the hash device.
1845 * @pdev: The platform device
1847 static void ux500_hash_shutdown(struct platform_device *pdev)
1849 struct resource *res = NULL;
1850 struct hash_device_data *device_data;
1852 device_data = platform_get_drvdata(pdev);
1854 dev_err(&pdev->dev, "[%s] platform_get_drvdata() failed!",
1859 /* Check that the device is free */
1860 spin_lock(&device_data->ctx_lock);
1861 /* current_ctx allocates a device, NULL = unallocated */
1862 if (!device_data->current_ctx) {
1863 if (down_trylock(&driver_data.device_allocation))
1864 dev_dbg(&pdev->dev, "[%s]: Cryp still in use!"
1865 "Shutting down anyway...", __func__);
1867 * (Allocate the device)
1868 * Need to set this to non-null (dummy) value,
1869 * to avoid usage if context switching.
1871 device_data->current_ctx++;
1873 spin_unlock(&device_data->ctx_lock);
1875 /* Remove the device from the list */
1876 if (klist_node_attached(&device_data->list_node))
1877 klist_remove(&device_data->list_node);
1879 /* If this was the last device, remove the services */
1880 if (list_empty(&driver_data.device_list.k_list))
1881 ahash_algs_unregister_all(device_data);
1883 iounmap(device_data->base);
1885 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1887 release_mem_region(res->start, resource_size(res));
1889 if (hash_disable_power(device_data, false))
1890 dev_err(&pdev->dev, "[%s] hash_disable_power() failed",
1895 * ux500_hash_suspend - Function that suspends the hash device.
1896 * @dev: Device to suspend.
1898 static int ux500_hash_suspend(struct device *dev)
1901 struct hash_device_data *device_data;
1902 struct hash_ctx *temp_ctx = NULL;
1904 device_data = dev_get_drvdata(dev);
1906 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1910 spin_lock(&device_data->ctx_lock);
1911 if (!device_data->current_ctx)
1912 device_data->current_ctx++;
1913 spin_unlock(&device_data->ctx_lock);
1915 if (device_data->current_ctx == ++temp_ctx) {
1916 if (down_interruptible(&driver_data.device_allocation))
1917 dev_dbg(dev, "[%s]: down_interruptible() failed",
1919 ret = hash_disable_power(device_data, false);
1922 ret = hash_disable_power(device_data, true);
1925 dev_err(dev, "[%s]: hash_disable_power()", __func__);
1931 * ux500_hash_resume - Function that resume the hash device.
1932 * @dev: Device to resume.
1934 static int ux500_hash_resume(struct device *dev)
1937 struct hash_device_data *device_data;
1938 struct hash_ctx *temp_ctx = NULL;
1940 device_data = dev_get_drvdata(dev);
1942 dev_err(dev, "[%s] platform_get_drvdata() failed!", __func__);
1946 spin_lock(&device_data->ctx_lock);
1947 if (device_data->current_ctx == ++temp_ctx)
1948 device_data->current_ctx = NULL;
1949 spin_unlock(&device_data->ctx_lock);
1951 if (!device_data->current_ctx)
1952 up(&driver_data.device_allocation);
1954 ret = hash_enable_power(device_data, true);
1957 dev_err(dev, "[%s]: hash_enable_power() failed!", __func__);
1962 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
1964 static struct platform_driver hash_driver = {
1965 .probe = ux500_hash_probe,
1966 .remove = ux500_hash_remove,
1967 .shutdown = ux500_hash_shutdown,
1969 .owner = THIS_MODULE,
1971 .pm = &ux500_hash_pm,
1976 * ux500_hash_mod_init - The kernel module init function.
1978 static int __init ux500_hash_mod_init(void)
1980 klist_init(&driver_data.device_list, NULL, NULL);
1981 /* Initialize the semaphore to 0 devices (locked state) */
1982 sema_init(&driver_data.device_allocation, 0);
1984 return platform_driver_register(&hash_driver);
1988 * ux500_hash_mod_fini - The kernel module exit function.
1990 static void __exit ux500_hash_mod_fini(void)
1992 platform_driver_unregister(&hash_driver);
1995 module_init(ux500_hash_mod_init);
1996 module_exit(ux500_hash_mod_fini);
1998 MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
1999 MODULE_LICENSE("GPL");
2001 MODULE_ALIAS("sha1-all");
2002 MODULE_ALIAS("sha256-all");
2003 MODULE_ALIAS("hmac-sha1-all");
2004 MODULE_ALIAS("hmac-sha256-all");