2 * talitos - Freescale Integrated Security Engine (SEC) device driver
4 * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
6 * Scatterlist Crypto API glue code copied from files with the following:
7 * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
9 * Crypto algorithm registration code copied from hifn driver:
10 * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11 * All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
33 #include <linux/crypto.h>
34 #include <linux/hw_random.h>
35 #include <linux/of_platform.h>
36 #include <linux/dma-mapping.h>
38 #include <linux/spinlock.h>
39 #include <linux/rtnetlink.h>
40 #include <linux/slab.h>
42 #include <crypto/algapi.h>
43 #include <crypto/aes.h>
44 #include <crypto/des.h>
45 #include <crypto/sha.h>
46 #include <crypto/md5.h>
47 #include <crypto/aead.h>
48 #include <crypto/authenc.h>
49 #include <crypto/skcipher.h>
50 #include <crypto/hash.h>
51 #include <crypto/internal/hash.h>
52 #include <crypto/scatterwalk.h>
56 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
58 talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
59 talitos_ptr->eptr = upper_32_bits(dma_addr);
63 * map virtual single (contiguous) pointer to h/w descriptor pointer
65 static void map_single_talitos_ptr(struct device *dev,
66 struct talitos_ptr *talitos_ptr,
67 unsigned short len, void *data,
69 enum dma_data_direction dir)
71 dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
73 talitos_ptr->len = cpu_to_be16(len);
74 to_talitos_ptr(talitos_ptr, dma_addr);
75 talitos_ptr->j_extent = extent;
79 * unmap bus single (contiguous) h/w descriptor pointer
81 static void unmap_single_talitos_ptr(struct device *dev,
82 struct talitos_ptr *talitos_ptr,
83 enum dma_data_direction dir)
85 dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
86 be16_to_cpu(talitos_ptr->len), dir);
89 static int reset_channel(struct device *dev, int ch)
91 struct talitos_private *priv = dev_get_drvdata(dev);
92 unsigned int timeout = TALITOS_TIMEOUT;
94 setbits32(priv->chan[ch].reg + TALITOS_CCCR, TALITOS_CCCR_RESET);
96 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) & TALITOS_CCCR_RESET)
101 dev_err(dev, "failed to reset channel %d\n", ch);
105 /* set 36-bit addressing, done writeback enable and done IRQ enable */
106 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
107 TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
109 /* and ICCR writeback, if available */
110 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
111 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
112 TALITOS_CCCR_LO_IWSE);
117 static int reset_device(struct device *dev)
119 struct talitos_private *priv = dev_get_drvdata(dev);
120 unsigned int timeout = TALITOS_TIMEOUT;
121 u32 mcr = TALITOS_MCR_SWR;
123 setbits32(priv->reg + TALITOS_MCR, mcr);
125 while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
130 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
131 setbits32(priv->reg + TALITOS_MCR, mcr);
135 dev_err(dev, "failed to reset device\n");
143 * Reset and initialize the device
145 static int init_device(struct device *dev)
147 struct talitos_private *priv = dev_get_drvdata(dev);
152 * errata documentation: warning: certain SEC interrupts
153 * are not fully cleared by writing the MCR:SWR bit,
154 * set bit twice to completely reset
156 err = reset_device(dev);
160 err = reset_device(dev);
165 for (ch = 0; ch < priv->num_channels; ch++) {
166 err = reset_channel(dev, ch);
171 /* enable channel done and error interrupts */
172 setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
173 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
175 /* disable integrity check error interrupts (use writeback instead) */
176 if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
177 setbits32(priv->reg + TALITOS_MDEUICR_LO,
178 TALITOS_MDEUICR_LO_ICE);
184 * talitos_submit - submits a descriptor to the device for processing
185 * @dev: the SEC device to be used
186 * @ch: the SEC device channel to be used
187 * @desc: the descriptor to be processed by the device
188 * @callback: whom to call when processing is complete
189 * @context: a handle for use by caller (optional)
191 * desc must contain valid dma-mapped (bus physical) address pointers.
192 * callback must check err and feedback in descriptor header
193 * for device processing status.
195 int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
196 void (*callback)(struct device *dev,
197 struct talitos_desc *desc,
198 void *context, int error),
201 struct talitos_private *priv = dev_get_drvdata(dev);
202 struct talitos_request *request;
206 spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
208 if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
209 /* h/w fifo is full */
210 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
214 head = priv->chan[ch].head;
215 request = &priv->chan[ch].fifo[head];
217 /* map descriptor and save caller data */
218 request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
220 request->callback = callback;
221 request->context = context;
223 /* increment fifo head */
224 priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
227 request->desc = desc;
231 out_be32(priv->chan[ch].reg + TALITOS_FF,
232 upper_32_bits(request->dma_desc));
233 out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
234 lower_32_bits(request->dma_desc));
236 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
240 EXPORT_SYMBOL(talitos_submit);
243 * process what was done, notify callback of error if not
245 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
247 struct talitos_private *priv = dev_get_drvdata(dev);
248 struct talitos_request *request, saved_req;
252 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
254 tail = priv->chan[ch].tail;
255 while (priv->chan[ch].fifo[tail].desc) {
256 request = &priv->chan[ch].fifo[tail];
258 /* descriptors with their done bits set don't get the error */
260 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
268 dma_unmap_single(dev, request->dma_desc,
269 sizeof(struct talitos_desc),
272 /* copy entries so we can call callback outside lock */
273 saved_req.desc = request->desc;
274 saved_req.callback = request->callback;
275 saved_req.context = request->context;
277 /* release request entry in fifo */
279 request->desc = NULL;
281 /* increment fifo tail */
282 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
284 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
286 atomic_dec(&priv->chan[ch].submit_count);
288 saved_req.callback(dev, saved_req.desc, saved_req.context,
290 /* channel may resume processing in single desc error case */
291 if (error && !reset_ch && status == error)
293 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
294 tail = priv->chan[ch].tail;
297 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
301 * process completed requests for channels that have done status
303 #define DEF_TALITOS_DONE(name, ch_done_mask) \
304 static void talitos_done_##name(unsigned long data) \
306 struct device *dev = (struct device *)data; \
307 struct talitos_private *priv = dev_get_drvdata(dev); \
308 unsigned long flags; \
310 if (ch_done_mask & 1) \
311 flush_channel(dev, 0, 0, 0); \
312 if (priv->num_channels == 1) \
314 if (ch_done_mask & (1 << 2)) \
315 flush_channel(dev, 1, 0, 0); \
316 if (ch_done_mask & (1 << 4)) \
317 flush_channel(dev, 2, 0, 0); \
318 if (ch_done_mask & (1 << 6)) \
319 flush_channel(dev, 3, 0, 0); \
322 /* At this point, all completed channels have been processed */ \
323 /* Unmask done interrupts for channels completed later on. */ \
324 spin_lock_irqsave(&priv->reg_lock, flags); \
325 setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
326 setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT); \
327 spin_unlock_irqrestore(&priv->reg_lock, flags); \
329 DEF_TALITOS_DONE(4ch, TALITOS_ISR_4CHDONE)
330 DEF_TALITOS_DONE(ch0_2, TALITOS_ISR_CH_0_2_DONE)
331 DEF_TALITOS_DONE(ch1_3, TALITOS_ISR_CH_1_3_DONE)
334 * locate current (offending) descriptor
336 static u32 current_desc_hdr(struct device *dev, int ch)
338 struct talitos_private *priv = dev_get_drvdata(dev);
339 int tail = priv->chan[ch].tail;
342 cur_desc = in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
344 while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
345 tail = (tail + 1) & (priv->fifo_len - 1);
346 if (tail == priv->chan[ch].tail) {
347 dev_err(dev, "couldn't locate current descriptor\n");
352 return priv->chan[ch].fifo[tail].desc->hdr;
356 * user diagnostics; report root cause of error based on execution unit status
358 static void report_eu_error(struct device *dev, int ch, u32 desc_hdr)
360 struct talitos_private *priv = dev_get_drvdata(dev);
364 desc_hdr = in_be32(priv->chan[ch].reg + TALITOS_DESCBUF);
366 switch (desc_hdr & DESC_HDR_SEL0_MASK) {
367 case DESC_HDR_SEL0_AFEU:
368 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
369 in_be32(priv->reg + TALITOS_AFEUISR),
370 in_be32(priv->reg + TALITOS_AFEUISR_LO));
372 case DESC_HDR_SEL0_DEU:
373 dev_err(dev, "DEUISR 0x%08x_%08x\n",
374 in_be32(priv->reg + TALITOS_DEUISR),
375 in_be32(priv->reg + TALITOS_DEUISR_LO));
377 case DESC_HDR_SEL0_MDEUA:
378 case DESC_HDR_SEL0_MDEUB:
379 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
380 in_be32(priv->reg + TALITOS_MDEUISR),
381 in_be32(priv->reg + TALITOS_MDEUISR_LO));
383 case DESC_HDR_SEL0_RNG:
384 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
385 in_be32(priv->reg + TALITOS_RNGUISR),
386 in_be32(priv->reg + TALITOS_RNGUISR_LO));
388 case DESC_HDR_SEL0_PKEU:
389 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
390 in_be32(priv->reg + TALITOS_PKEUISR),
391 in_be32(priv->reg + TALITOS_PKEUISR_LO));
393 case DESC_HDR_SEL0_AESU:
394 dev_err(dev, "AESUISR 0x%08x_%08x\n",
395 in_be32(priv->reg + TALITOS_AESUISR),
396 in_be32(priv->reg + TALITOS_AESUISR_LO));
398 case DESC_HDR_SEL0_CRCU:
399 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
400 in_be32(priv->reg + TALITOS_CRCUISR),
401 in_be32(priv->reg + TALITOS_CRCUISR_LO));
403 case DESC_HDR_SEL0_KEU:
404 dev_err(dev, "KEUISR 0x%08x_%08x\n",
405 in_be32(priv->reg + TALITOS_KEUISR),
406 in_be32(priv->reg + TALITOS_KEUISR_LO));
410 switch (desc_hdr & DESC_HDR_SEL1_MASK) {
411 case DESC_HDR_SEL1_MDEUA:
412 case DESC_HDR_SEL1_MDEUB:
413 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
414 in_be32(priv->reg + TALITOS_MDEUISR),
415 in_be32(priv->reg + TALITOS_MDEUISR_LO));
417 case DESC_HDR_SEL1_CRCU:
418 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
419 in_be32(priv->reg + TALITOS_CRCUISR),
420 in_be32(priv->reg + TALITOS_CRCUISR_LO));
424 for (i = 0; i < 8; i++)
425 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
426 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
427 in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
431 * recover from error interrupts
433 static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
435 struct talitos_private *priv = dev_get_drvdata(dev);
436 unsigned int timeout = TALITOS_TIMEOUT;
437 int ch, error, reset_dev = 0, reset_ch = 0;
440 for (ch = 0; ch < priv->num_channels; ch++) {
441 /* skip channels without errors */
442 if (!(isr & (1 << (ch * 2 + 1))))
447 v = in_be32(priv->chan[ch].reg + TALITOS_CCPSR);
448 v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
450 if (v_lo & TALITOS_CCPSR_LO_DOF) {
451 dev_err(dev, "double fetch fifo overflow error\n");
455 if (v_lo & TALITOS_CCPSR_LO_SOF) {
456 /* h/w dropped descriptor */
457 dev_err(dev, "single fetch fifo overflow error\n");
460 if (v_lo & TALITOS_CCPSR_LO_MDTE)
461 dev_err(dev, "master data transfer error\n");
462 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
463 dev_err(dev, "s/g data length zero error\n");
464 if (v_lo & TALITOS_CCPSR_LO_FPZ)
465 dev_err(dev, "fetch pointer zero error\n");
466 if (v_lo & TALITOS_CCPSR_LO_IDH)
467 dev_err(dev, "illegal descriptor header error\n");
468 if (v_lo & TALITOS_CCPSR_LO_IEU)
469 dev_err(dev, "invalid execution unit error\n");
470 if (v_lo & TALITOS_CCPSR_LO_EU)
471 report_eu_error(dev, ch, current_desc_hdr(dev, ch));
472 if (v_lo & TALITOS_CCPSR_LO_GB)
473 dev_err(dev, "gather boundary error\n");
474 if (v_lo & TALITOS_CCPSR_LO_GRL)
475 dev_err(dev, "gather return/length error\n");
476 if (v_lo & TALITOS_CCPSR_LO_SB)
477 dev_err(dev, "scatter boundary error\n");
478 if (v_lo & TALITOS_CCPSR_LO_SRL)
479 dev_err(dev, "scatter return/length error\n");
481 flush_channel(dev, ch, error, reset_ch);
484 reset_channel(dev, ch);
486 setbits32(priv->chan[ch].reg + TALITOS_CCCR,
488 setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
489 while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
490 TALITOS_CCCR_CONT) && --timeout)
493 dev_err(dev, "failed to restart channel %d\n",
499 if (reset_dev || isr & ~TALITOS_ISR_4CHERR || isr_lo) {
500 dev_err(dev, "done overflow, internal time out, or rngu error: "
501 "ISR 0x%08x_%08x\n", isr, isr_lo);
503 /* purge request queues */
504 for (ch = 0; ch < priv->num_channels; ch++)
505 flush_channel(dev, ch, -EIO, 1);
507 /* reset and reinitialize the device */
512 #define DEF_TALITOS_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
513 static irqreturn_t talitos_interrupt_##name(int irq, void *data) \
515 struct device *dev = data; \
516 struct talitos_private *priv = dev_get_drvdata(dev); \
518 unsigned long flags; \
520 spin_lock_irqsave(&priv->reg_lock, flags); \
521 isr = in_be32(priv->reg + TALITOS_ISR); \
522 isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
523 /* Acknowledge interrupt */ \
524 out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
525 out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
527 if (unlikely(isr & ch_err_mask || isr_lo)) { \
528 spin_unlock_irqrestore(&priv->reg_lock, flags); \
529 talitos_error(dev, isr & ch_err_mask, isr_lo); \
532 if (likely(isr & ch_done_mask)) { \
533 /* mask further done interrupts. */ \
534 clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
535 /* done_task will unmask done interrupts at exit */ \
536 tasklet_schedule(&priv->done_task[tlet]); \
538 spin_unlock_irqrestore(&priv->reg_lock, flags); \
541 return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
544 DEF_TALITOS_INTERRUPT(4ch, TALITOS_ISR_4CHDONE, TALITOS_ISR_4CHERR, 0)
545 DEF_TALITOS_INTERRUPT(ch0_2, TALITOS_ISR_CH_0_2_DONE, TALITOS_ISR_CH_0_2_ERR, 0)
546 DEF_TALITOS_INTERRUPT(ch1_3, TALITOS_ISR_CH_1_3_DONE, TALITOS_ISR_CH_1_3_ERR, 1)
551 static int talitos_rng_data_present(struct hwrng *rng, int wait)
553 struct device *dev = (struct device *)rng->priv;
554 struct talitos_private *priv = dev_get_drvdata(dev);
558 for (i = 0; i < 20; i++) {
559 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
560 TALITOS_RNGUSR_LO_OFL;
569 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
571 struct device *dev = (struct device *)rng->priv;
572 struct talitos_private *priv = dev_get_drvdata(dev);
574 /* rng fifo requires 64-bit accesses */
575 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
576 *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
581 static int talitos_rng_init(struct hwrng *rng)
583 struct device *dev = (struct device *)rng->priv;
584 struct talitos_private *priv = dev_get_drvdata(dev);
585 unsigned int timeout = TALITOS_TIMEOUT;
587 setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
588 while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
592 dev_err(dev, "failed to reset rng hw\n");
596 /* start generating */
597 setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
602 static int talitos_register_rng(struct device *dev)
604 struct talitos_private *priv = dev_get_drvdata(dev);
606 priv->rng.name = dev_driver_string(dev),
607 priv->rng.init = talitos_rng_init,
608 priv->rng.data_present = talitos_rng_data_present,
609 priv->rng.data_read = talitos_rng_data_read,
610 priv->rng.priv = (unsigned long)dev;
612 return hwrng_register(&priv->rng);
615 static void talitos_unregister_rng(struct device *dev)
617 struct talitos_private *priv = dev_get_drvdata(dev);
619 hwrng_unregister(&priv->rng);
625 #define TALITOS_CRA_PRIORITY 3000
626 #define TALITOS_MAX_KEY_SIZE 96
627 #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
629 #define MD5_BLOCK_SIZE 64
634 __be32 desc_hdr_template;
635 u8 key[TALITOS_MAX_KEY_SIZE];
636 u8 iv[TALITOS_MAX_IV_LENGTH];
638 unsigned int enckeylen;
639 unsigned int authkeylen;
640 unsigned int authsize;
643 #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
644 #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
646 struct talitos_ahash_req_ctx {
647 u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
648 unsigned int hw_context_size;
649 u8 buf[HASH_MAX_BLOCK_SIZE];
650 u8 bufnext[HASH_MAX_BLOCK_SIZE];
654 unsigned int to_hash_later;
656 struct scatterlist bufsl[2];
657 struct scatterlist *psrc;
660 static int aead_setauthsize(struct crypto_aead *authenc,
661 unsigned int authsize)
663 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
665 ctx->authsize = authsize;
670 static int aead_setkey(struct crypto_aead *authenc,
671 const u8 *key, unsigned int keylen)
673 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
674 struct rtattr *rta = (void *)key;
675 struct crypto_authenc_key_param *param;
676 unsigned int authkeylen;
677 unsigned int enckeylen;
679 if (!RTA_OK(rta, keylen))
682 if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
685 if (RTA_PAYLOAD(rta) < sizeof(*param))
688 param = RTA_DATA(rta);
689 enckeylen = be32_to_cpu(param->enckeylen);
691 key += RTA_ALIGN(rta->rta_len);
692 keylen -= RTA_ALIGN(rta->rta_len);
694 if (keylen < enckeylen)
697 authkeylen = keylen - enckeylen;
699 if (keylen > TALITOS_MAX_KEY_SIZE)
702 memcpy(&ctx->key, key, keylen);
704 ctx->keylen = keylen;
705 ctx->enckeylen = enckeylen;
706 ctx->authkeylen = authkeylen;
711 crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
716 * talitos_edesc - s/w-extended descriptor
717 * @assoc_nents: number of segments in associated data scatterlist
718 * @src_nents: number of segments in input scatterlist
719 * @dst_nents: number of segments in output scatterlist
720 * @assoc_chained: whether assoc is chained or not
721 * @src_chained: whether src is chained or not
722 * @dst_chained: whether dst is chained or not
723 * @iv_dma: dma address of iv for checking continuity and link table
724 * @dma_len: length of dma mapped link_tbl space
725 * @dma_link_tbl: bus physical address of link_tbl
726 * @desc: h/w descriptor
727 * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
729 * if decrypting (with authcheck), or either one of src_nents or dst_nents
730 * is greater than 1, an integrity check value is concatenated to the end
733 struct talitos_edesc {
742 dma_addr_t dma_link_tbl;
743 struct talitos_desc desc;
744 struct talitos_ptr link_tbl[0];
747 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
748 unsigned int nents, enum dma_data_direction dir,
751 if (unlikely(chained))
753 dma_map_sg(dev, sg, 1, dir);
754 sg = scatterwalk_sg_next(sg);
757 dma_map_sg(dev, sg, nents, dir);
761 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
762 enum dma_data_direction dir)
765 dma_unmap_sg(dev, sg, 1, dir);
766 sg = scatterwalk_sg_next(sg);
770 static void talitos_sg_unmap(struct device *dev,
771 struct talitos_edesc *edesc,
772 struct scatterlist *src,
773 struct scatterlist *dst)
775 unsigned int src_nents = edesc->src_nents ? : 1;
776 unsigned int dst_nents = edesc->dst_nents ? : 1;
779 if (edesc->src_chained)
780 talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
782 dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
785 if (edesc->dst_chained)
786 talitos_unmap_sg_chain(dev, dst,
789 dma_unmap_sg(dev, dst, dst_nents,
793 if (edesc->src_chained)
794 talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
796 dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
799 static void ipsec_esp_unmap(struct device *dev,
800 struct talitos_edesc *edesc,
801 struct aead_request *areq)
803 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
804 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
805 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
806 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
808 if (edesc->assoc_chained)
809 talitos_unmap_sg_chain(dev, areq->assoc, DMA_TO_DEVICE);
811 /* assoc_nents counts also for IV in non-contiguous cases */
812 dma_unmap_sg(dev, areq->assoc,
813 edesc->assoc_nents ? edesc->assoc_nents - 1 : 1,
816 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
819 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
824 * ipsec_esp descriptor callbacks
826 static void ipsec_esp_encrypt_done(struct device *dev,
827 struct talitos_desc *desc, void *context,
830 struct aead_request *areq = context;
831 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
832 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
833 struct talitos_edesc *edesc;
834 struct scatterlist *sg;
837 edesc = container_of(desc, struct talitos_edesc, desc);
839 ipsec_esp_unmap(dev, edesc, areq);
841 /* copy the generated ICV to dst */
842 if (edesc->dst_nents) {
843 icvdata = &edesc->link_tbl[edesc->src_nents +
844 edesc->dst_nents + 2 +
846 sg = sg_last(areq->dst, edesc->dst_nents);
847 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
848 icvdata, ctx->authsize);
853 aead_request_complete(areq, err);
856 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
857 struct talitos_desc *desc,
858 void *context, int err)
860 struct aead_request *req = context;
861 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
862 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
863 struct talitos_edesc *edesc;
864 struct scatterlist *sg;
867 edesc = container_of(desc, struct talitos_edesc, desc);
869 ipsec_esp_unmap(dev, edesc, req);
874 icvdata = &edesc->link_tbl[edesc->src_nents +
875 edesc->dst_nents + 2 +
878 icvdata = &edesc->link_tbl[0];
880 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
881 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
882 ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
887 aead_request_complete(req, err);
890 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
891 struct talitos_desc *desc,
892 void *context, int err)
894 struct aead_request *req = context;
895 struct talitos_edesc *edesc;
897 edesc = container_of(desc, struct talitos_edesc, desc);
899 ipsec_esp_unmap(dev, edesc, req);
901 /* check ICV auth status */
902 if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
903 DESC_HDR_LO_ICCR1_PASS))
908 aead_request_complete(req, err);
912 * convert scatterlist to SEC h/w link table format
913 * stop at cryptlen bytes
915 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
916 int cryptlen, struct talitos_ptr *link_tbl_ptr)
921 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
922 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
923 link_tbl_ptr->j_extent = 0;
925 cryptlen -= sg_dma_len(sg);
926 sg = scatterwalk_sg_next(sg);
929 /* adjust (decrease) last one (or two) entry's len to cryptlen */
931 while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
932 /* Empty this entry, and move to previous one */
933 cryptlen += be16_to_cpu(link_tbl_ptr->len);
934 link_tbl_ptr->len = 0;
938 link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
941 /* tag end of link table */
942 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
948 * fill in and submit ipsec_esp descriptor
950 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
951 u64 seq, void (*callback) (struct device *dev,
952 struct talitos_desc *desc,
953 void *context, int error))
955 struct crypto_aead *aead = crypto_aead_reqtfm(areq);
956 struct talitos_ctx *ctx = crypto_aead_ctx(aead);
957 struct device *dev = ctx->dev;
958 struct talitos_desc *desc = &edesc->desc;
959 unsigned int cryptlen = areq->cryptlen;
960 unsigned int authsize = ctx->authsize;
961 unsigned int ivsize = crypto_aead_ivsize(aead);
966 map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
970 desc->ptr[1].len = cpu_to_be16(areq->assoclen + ivsize);
971 if (edesc->assoc_nents) {
972 int tbl_off = edesc->src_nents + edesc->dst_nents + 2;
973 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
975 to_talitos_ptr(&desc->ptr[1], edesc->dma_link_tbl + tbl_off *
976 sizeof(struct talitos_ptr));
977 desc->ptr[1].j_extent = DESC_PTR_LNKTBL_JUMP;
979 /* assoc_nents - 1 entries for assoc, 1 for IV */
980 sg_count = sg_to_link_tbl(areq->assoc, edesc->assoc_nents - 1,
981 areq->assoclen, tbl_ptr);
983 /* add IV to link table */
984 tbl_ptr += sg_count - 1;
985 tbl_ptr->j_extent = 0;
987 to_talitos_ptr(tbl_ptr, edesc->iv_dma);
988 tbl_ptr->len = cpu_to_be16(ivsize);
989 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
991 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
992 edesc->dma_len, DMA_BIDIRECTIONAL);
994 to_talitos_ptr(&desc->ptr[1], sg_dma_address(areq->assoc));
995 desc->ptr[1].j_extent = 0;
999 to_talitos_ptr(&desc->ptr[2], edesc->iv_dma);
1000 desc->ptr[2].len = cpu_to_be16(ivsize);
1001 desc->ptr[2].j_extent = 0;
1002 /* Sync needed for the aead_givencrypt case */
1003 dma_sync_single_for_device(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
1006 map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1007 (char *)&ctx->key + ctx->authkeylen, 0,
1012 * map and adjust cipher len to aead request cryptlen.
1013 * extent is bytes of HMAC postpended to ciphertext,
1014 * typically 12 for ipsec
1016 desc->ptr[4].len = cpu_to_be16(cryptlen);
1017 desc->ptr[4].j_extent = authsize;
1019 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1020 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1022 edesc->src_chained);
1024 if (sg_count == 1) {
1025 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1027 sg_link_tbl_len = cryptlen;
1029 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1030 sg_link_tbl_len = cryptlen + authsize;
1032 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1033 &edesc->link_tbl[0]);
1035 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1036 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1037 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1041 /* Only one segment now, so no link tbl needed */
1042 to_talitos_ptr(&desc->ptr[4],
1043 sg_dma_address(areq->src));
1048 desc->ptr[5].len = cpu_to_be16(cryptlen);
1049 desc->ptr[5].j_extent = authsize;
1051 if (areq->src != areq->dst)
1052 sg_count = talitos_map_sg(dev, areq->dst,
1053 edesc->dst_nents ? : 1,
1054 DMA_FROM_DEVICE, edesc->dst_chained);
1056 if (sg_count == 1) {
1057 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1059 int tbl_off = edesc->src_nents + 1;
1060 struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
1062 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1063 tbl_off * sizeof(struct talitos_ptr));
1064 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1067 /* Add an entry to the link table for ICV data */
1068 tbl_ptr += sg_count - 1;
1069 tbl_ptr->j_extent = 0;
1071 tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1072 tbl_ptr->len = cpu_to_be16(authsize);
1074 /* icv data follows link tables */
1075 to_talitos_ptr(tbl_ptr, edesc->dma_link_tbl +
1076 (tbl_off + edesc->dst_nents + 1 +
1077 edesc->assoc_nents) *
1078 sizeof(struct talitos_ptr));
1079 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1080 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1081 edesc->dma_len, DMA_BIDIRECTIONAL);
1085 map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1088 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1089 if (ret != -EINPROGRESS) {
1090 ipsec_esp_unmap(dev, edesc, areq);
1097 * derive number of elements in scatterlist
1099 static int sg_count(struct scatterlist *sg_list, int nbytes, bool *chained)
1101 struct scatterlist *sg = sg_list;
1105 while (nbytes > 0) {
1107 nbytes -= sg->length;
1108 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1110 sg = scatterwalk_sg_next(sg);
1117 * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1119 * @nents: Number of SG entries
1120 * @buf: Where to copy to
1121 * @buflen: The number of bytes to copy
1122 * @skip: The number of bytes to skip before copying.
1123 * Note: skip + buflen should equal SG total size.
1125 * Returns the number of copied bytes.
1128 static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1129 void *buf, size_t buflen, unsigned int skip)
1131 unsigned int offset = 0;
1132 unsigned int boffset = 0;
1133 struct sg_mapping_iter miter;
1134 unsigned long flags;
1135 unsigned int sg_flags = SG_MITER_ATOMIC;
1136 size_t total_buffer = buflen + skip;
1138 sg_flags |= SG_MITER_FROM_SG;
1140 sg_miter_start(&miter, sgl, nents, sg_flags);
1142 local_irq_save(flags);
1144 while (sg_miter_next(&miter) && offset < total_buffer) {
1146 unsigned int ignore;
1148 if ((offset + miter.length) > skip) {
1149 if (offset < skip) {
1150 /* Copy part of this segment */
1151 ignore = skip - offset;
1152 len = miter.length - ignore;
1153 if (boffset + len > buflen)
1154 len = buflen - boffset;
1155 memcpy(buf + boffset, miter.addr + ignore, len);
1157 /* Copy all of this segment (up to buflen) */
1159 if (boffset + len > buflen)
1160 len = buflen - boffset;
1161 memcpy(buf + boffset, miter.addr, len);
1165 offset += miter.length;
1168 sg_miter_stop(&miter);
1170 local_irq_restore(flags);
1175 * allocate and map the extended descriptor
1177 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1178 struct scatterlist *assoc,
1179 struct scatterlist *src,
1180 struct scatterlist *dst,
1182 unsigned int assoclen,
1183 unsigned int cryptlen,
1184 unsigned int authsize,
1185 unsigned int ivsize,
1189 struct talitos_edesc *edesc;
1190 int assoc_nents = 0, src_nents, dst_nents, alloc_len, dma_len;
1191 bool assoc_chained = false, src_chained = false, dst_chained = false;
1192 dma_addr_t iv_dma = 0;
1193 gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1196 if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1197 dev_err(dev, "length exceeds h/w max limit\n");
1198 return ERR_PTR(-EINVAL);
1202 iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
1206 * Currently it is assumed that iv is provided whenever assoc
1211 assoc_nents = sg_count(assoc, assoclen, &assoc_chained);
1212 talitos_map_sg(dev, assoc, assoc_nents, DMA_TO_DEVICE,
1214 assoc_nents = (assoc_nents == 1) ? 0 : assoc_nents;
1216 if (assoc_nents || sg_dma_address(assoc) + assoclen != iv_dma)
1217 assoc_nents = assoc_nents ? assoc_nents + 1 : 2;
1220 src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1221 src_nents = (src_nents == 1) ? 0 : src_nents;
1227 dst_nents = src_nents;
1229 dst_nents = sg_count(dst, cryptlen + authsize,
1231 dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1236 * allocate space for base edesc plus the link tables,
1237 * allowing for two separate entries for ICV and generated ICV (+ 2),
1238 * and the ICV data itself
1240 alloc_len = sizeof(struct talitos_edesc);
1241 if (assoc_nents || src_nents || dst_nents) {
1242 dma_len = (src_nents + dst_nents + 2 + assoc_nents) *
1243 sizeof(struct talitos_ptr) + authsize;
1244 alloc_len += dma_len;
1247 alloc_len += icv_stashing ? authsize : 0;
1250 edesc = kmalloc(alloc_len, GFP_DMA | flags);
1252 talitos_unmap_sg_chain(dev, assoc, DMA_TO_DEVICE);
1254 dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
1255 dev_err(dev, "could not allocate edescriptor\n");
1256 return ERR_PTR(-ENOMEM);
1259 edesc->assoc_nents = assoc_nents;
1260 edesc->src_nents = src_nents;
1261 edesc->dst_nents = dst_nents;
1262 edesc->assoc_chained = assoc_chained;
1263 edesc->src_chained = src_chained;
1264 edesc->dst_chained = dst_chained;
1265 edesc->iv_dma = iv_dma;
1266 edesc->dma_len = dma_len;
1268 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1275 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
1278 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1279 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1280 unsigned int ivsize = crypto_aead_ivsize(authenc);
1282 return talitos_edesc_alloc(ctx->dev, areq->assoc, areq->src, areq->dst,
1283 iv, areq->assoclen, areq->cryptlen,
1284 ctx->authsize, ivsize, icv_stashing,
1288 static int aead_encrypt(struct aead_request *req)
1290 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1291 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1292 struct talitos_edesc *edesc;
1294 /* allocate extended descriptor */
1295 edesc = aead_edesc_alloc(req, req->iv, 0);
1297 return PTR_ERR(edesc);
1300 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1302 return ipsec_esp(edesc, req, 0, ipsec_esp_encrypt_done);
1305 static int aead_decrypt(struct aead_request *req)
1307 struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1308 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1309 unsigned int authsize = ctx->authsize;
1310 struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1311 struct talitos_edesc *edesc;
1312 struct scatterlist *sg;
1315 req->cryptlen -= authsize;
1317 /* allocate extended descriptor */
1318 edesc = aead_edesc_alloc(req, req->iv, 1);
1320 return PTR_ERR(edesc);
1322 if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1323 ((!edesc->src_nents && !edesc->dst_nents) ||
1324 priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1326 /* decrypt and check the ICV */
1327 edesc->desc.hdr = ctx->desc_hdr_template |
1328 DESC_HDR_DIR_INBOUND |
1329 DESC_HDR_MODE1_MDEU_CICV;
1331 /* reset integrity check result bits */
1332 edesc->desc.hdr_lo = 0;
1334 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_hwauth_done);
1337 /* Have to check the ICV with software */
1338 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1340 /* stash incoming ICV for later cmp with ICV generated by the h/w */
1342 icvdata = &edesc->link_tbl[edesc->src_nents +
1343 edesc->dst_nents + 2 +
1344 edesc->assoc_nents];
1346 icvdata = &edesc->link_tbl[0];
1348 sg = sg_last(req->src, edesc->src_nents ? : 1);
1350 memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1353 return ipsec_esp(edesc, req, 0, ipsec_esp_decrypt_swauth_done);
1356 static int aead_givencrypt(struct aead_givcrypt_request *req)
1358 struct aead_request *areq = &req->areq;
1359 struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1360 struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1361 struct talitos_edesc *edesc;
1363 /* allocate extended descriptor */
1364 edesc = aead_edesc_alloc(areq, req->giv, 0);
1366 return PTR_ERR(edesc);
1369 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1371 memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1372 /* avoid consecutive packets going out with same IV */
1373 *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1375 return ipsec_esp(edesc, areq, req->seq, ipsec_esp_encrypt_done);
1378 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1379 const u8 *key, unsigned int keylen)
1381 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1383 memcpy(&ctx->key, key, keylen);
1384 ctx->keylen = keylen;
1389 static void common_nonsnoop_unmap(struct device *dev,
1390 struct talitos_edesc *edesc,
1391 struct ablkcipher_request *areq)
1393 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1394 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1395 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1397 talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1400 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1404 static void ablkcipher_done(struct device *dev,
1405 struct talitos_desc *desc, void *context,
1408 struct ablkcipher_request *areq = context;
1409 struct talitos_edesc *edesc;
1411 edesc = container_of(desc, struct talitos_edesc, desc);
1413 common_nonsnoop_unmap(dev, edesc, areq);
1417 areq->base.complete(&areq->base, err);
1420 static int common_nonsnoop(struct talitos_edesc *edesc,
1421 struct ablkcipher_request *areq,
1422 void (*callback) (struct device *dev,
1423 struct talitos_desc *desc,
1424 void *context, int error))
1426 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1427 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1428 struct device *dev = ctx->dev;
1429 struct talitos_desc *desc = &edesc->desc;
1430 unsigned int cryptlen = areq->nbytes;
1431 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1434 /* first DWORD empty */
1435 desc->ptr[0].len = 0;
1436 to_talitos_ptr(&desc->ptr[0], 0);
1437 desc->ptr[0].j_extent = 0;
1440 to_talitos_ptr(&desc->ptr[1], edesc->iv_dma);
1441 desc->ptr[1].len = cpu_to_be16(ivsize);
1442 desc->ptr[1].j_extent = 0;
1445 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1446 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1451 desc->ptr[3].len = cpu_to_be16(cryptlen);
1452 desc->ptr[3].j_extent = 0;
1454 sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1455 (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1457 edesc->src_chained);
1459 if (sg_count == 1) {
1460 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1462 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1463 &edesc->link_tbl[0]);
1465 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1466 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1467 dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1471 /* Only one segment now, so no link tbl needed */
1472 to_talitos_ptr(&desc->ptr[3],
1473 sg_dma_address(areq->src));
1478 desc->ptr[4].len = cpu_to_be16(cryptlen);
1479 desc->ptr[4].j_extent = 0;
1481 if (areq->src != areq->dst)
1482 sg_count = talitos_map_sg(dev, areq->dst,
1483 edesc->dst_nents ? : 1,
1484 DMA_FROM_DEVICE, edesc->dst_chained);
1486 if (sg_count == 1) {
1487 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1489 struct talitos_ptr *link_tbl_ptr =
1490 &edesc->link_tbl[edesc->src_nents + 1];
1492 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1493 (edesc->src_nents + 1) *
1494 sizeof(struct talitos_ptr));
1495 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1496 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1498 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1499 edesc->dma_len, DMA_BIDIRECTIONAL);
1503 map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1506 /* last DWORD empty */
1507 desc->ptr[6].len = 0;
1508 to_talitos_ptr(&desc->ptr[6], 0);
1509 desc->ptr[6].j_extent = 0;
1511 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1512 if (ret != -EINPROGRESS) {
1513 common_nonsnoop_unmap(dev, edesc, areq);
1519 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1522 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1523 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1524 unsigned int ivsize = crypto_ablkcipher_ivsize(cipher);
1526 return talitos_edesc_alloc(ctx->dev, NULL, areq->src, areq->dst,
1527 areq->info, 0, areq->nbytes, 0, ivsize, 0,
1531 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1533 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1534 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1535 struct talitos_edesc *edesc;
1537 /* allocate extended descriptor */
1538 edesc = ablkcipher_edesc_alloc(areq);
1540 return PTR_ERR(edesc);
1543 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1545 return common_nonsnoop(edesc, areq, ablkcipher_done);
1548 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1550 struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1551 struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1552 struct talitos_edesc *edesc;
1554 /* allocate extended descriptor */
1555 edesc = ablkcipher_edesc_alloc(areq);
1557 return PTR_ERR(edesc);
1559 edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1561 return common_nonsnoop(edesc, areq, ablkcipher_done);
1564 static void common_nonsnoop_hash_unmap(struct device *dev,
1565 struct talitos_edesc *edesc,
1566 struct ahash_request *areq)
1568 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1570 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1572 /* When using hashctx-in, must unmap it. */
1573 if (edesc->desc.ptr[1].len)
1574 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1577 if (edesc->desc.ptr[2].len)
1578 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1581 talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1584 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1589 static void ahash_done(struct device *dev,
1590 struct talitos_desc *desc, void *context,
1593 struct ahash_request *areq = context;
1594 struct talitos_edesc *edesc =
1595 container_of(desc, struct talitos_edesc, desc);
1596 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1598 if (!req_ctx->last && req_ctx->to_hash_later) {
1599 /* Position any partial block for next update/final/finup */
1600 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1601 req_ctx->nbuf = req_ctx->to_hash_later;
1603 common_nonsnoop_hash_unmap(dev, edesc, areq);
1607 areq->base.complete(&areq->base, err);
1610 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1611 struct ahash_request *areq, unsigned int length,
1612 void (*callback) (struct device *dev,
1613 struct talitos_desc *desc,
1614 void *context, int error))
1616 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1617 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1618 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1619 struct device *dev = ctx->dev;
1620 struct talitos_desc *desc = &edesc->desc;
1623 /* first DWORD empty */
1624 desc->ptr[0] = zero_entry;
1626 /* hash context in */
1627 if (!req_ctx->first || req_ctx->swinit) {
1628 map_single_talitos_ptr(dev, &desc->ptr[1],
1629 req_ctx->hw_context_size,
1630 (char *)req_ctx->hw_context, 0,
1632 req_ctx->swinit = 0;
1634 desc->ptr[1] = zero_entry;
1635 /* Indicate next op is not the first. */
1641 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1642 (char *)&ctx->key, 0, DMA_TO_DEVICE);
1644 desc->ptr[2] = zero_entry;
1649 desc->ptr[3].len = cpu_to_be16(length);
1650 desc->ptr[3].j_extent = 0;
1652 sg_count = talitos_map_sg(dev, req_ctx->psrc,
1653 edesc->src_nents ? : 1,
1654 DMA_TO_DEVICE, edesc->src_chained);
1656 if (sg_count == 1) {
1657 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1659 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1660 &edesc->link_tbl[0]);
1662 desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1663 to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1664 dma_sync_single_for_device(ctx->dev,
1665 edesc->dma_link_tbl,
1669 /* Only one segment now, so no link tbl needed */
1670 to_talitos_ptr(&desc->ptr[3],
1671 sg_dma_address(req_ctx->psrc));
1675 /* fifth DWORD empty */
1676 desc->ptr[4] = zero_entry;
1678 /* hash/HMAC out -or- hash context out */
1680 map_single_talitos_ptr(dev, &desc->ptr[5],
1681 crypto_ahash_digestsize(tfm),
1682 areq->result, 0, DMA_FROM_DEVICE);
1684 map_single_talitos_ptr(dev, &desc->ptr[5],
1685 req_ctx->hw_context_size,
1686 req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1688 /* last DWORD empty */
1689 desc->ptr[6] = zero_entry;
1691 ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
1692 if (ret != -EINPROGRESS) {
1693 common_nonsnoop_hash_unmap(dev, edesc, areq);
1699 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1700 unsigned int nbytes)
1702 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1703 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1704 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1706 return talitos_edesc_alloc(ctx->dev, NULL, req_ctx->psrc, NULL, NULL, 0,
1707 nbytes, 0, 0, 0, areq->base.flags);
1710 static int ahash_init(struct ahash_request *areq)
1712 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1713 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1715 /* Initialize the context */
1717 req_ctx->first = 1; /* first indicates h/w must init its context */
1718 req_ctx->swinit = 0; /* assume h/w init of context */
1719 req_ctx->hw_context_size =
1720 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1721 ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1722 : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1728 * on h/w without explicit sha224 support, we initialize h/w context
1729 * manually with sha224 constants, and tell it to run sha256.
1731 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1733 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1736 req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1738 req_ctx->hw_context[0] = SHA224_H0;
1739 req_ctx->hw_context[1] = SHA224_H1;
1740 req_ctx->hw_context[2] = SHA224_H2;
1741 req_ctx->hw_context[3] = SHA224_H3;
1742 req_ctx->hw_context[4] = SHA224_H4;
1743 req_ctx->hw_context[5] = SHA224_H5;
1744 req_ctx->hw_context[6] = SHA224_H6;
1745 req_ctx->hw_context[7] = SHA224_H7;
1747 /* init 64-bit count */
1748 req_ctx->hw_context[8] = 0;
1749 req_ctx->hw_context[9] = 0;
1754 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1756 struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1757 struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1758 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1759 struct talitos_edesc *edesc;
1760 unsigned int blocksize =
1761 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1762 unsigned int nbytes_to_hash;
1763 unsigned int to_hash_later;
1767 if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1768 /* Buffer up to one whole block */
1769 sg_copy_to_buffer(areq->src,
1770 sg_count(areq->src, nbytes, &chained),
1771 req_ctx->buf + req_ctx->nbuf, nbytes);
1772 req_ctx->nbuf += nbytes;
1776 /* At least (blocksize + 1) bytes are available to hash */
1777 nbytes_to_hash = nbytes + req_ctx->nbuf;
1778 to_hash_later = nbytes_to_hash & (blocksize - 1);
1782 else if (to_hash_later)
1783 /* There is a partial block. Hash the full block(s) now */
1784 nbytes_to_hash -= to_hash_later;
1786 /* Keep one block buffered */
1787 nbytes_to_hash -= blocksize;
1788 to_hash_later = blocksize;
1791 /* Chain in any previously buffered data */
1792 if (req_ctx->nbuf) {
1793 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1794 sg_init_table(req_ctx->bufsl, nsg);
1795 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1797 scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1798 req_ctx->psrc = req_ctx->bufsl;
1800 req_ctx->psrc = areq->src;
1802 if (to_hash_later) {
1803 int nents = sg_count(areq->src, nbytes, &chained);
1804 sg_copy_end_to_buffer(areq->src, nents,
1807 nbytes - to_hash_later);
1809 req_ctx->to_hash_later = to_hash_later;
1811 /* Allocate extended descriptor */
1812 edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1814 return PTR_ERR(edesc);
1816 edesc->desc.hdr = ctx->desc_hdr_template;
1818 /* On last one, request SEC to pad; otherwise continue */
1820 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1822 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1824 /* request SEC to INIT hash. */
1825 if (req_ctx->first && !req_ctx->swinit)
1826 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1828 /* When the tfm context has a keylen, it's an HMAC.
1829 * A first or last (ie. not middle) descriptor must request HMAC.
1831 if (ctx->keylen && (req_ctx->first || req_ctx->last))
1832 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1834 return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1838 static int ahash_update(struct ahash_request *areq)
1840 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1844 return ahash_process_req(areq, areq->nbytes);
1847 static int ahash_final(struct ahash_request *areq)
1849 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1853 return ahash_process_req(areq, 0);
1856 static int ahash_finup(struct ahash_request *areq)
1858 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1862 return ahash_process_req(areq, areq->nbytes);
1865 static int ahash_digest(struct ahash_request *areq)
1867 struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1868 struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1873 return ahash_process_req(areq, areq->nbytes);
1876 struct keyhash_result {
1877 struct completion completion;
1881 static void keyhash_complete(struct crypto_async_request *req, int err)
1883 struct keyhash_result *res = req->data;
1885 if (err == -EINPROGRESS)
1889 complete(&res->completion);
1892 static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
1895 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1897 struct scatterlist sg[1];
1898 struct ahash_request *req;
1899 struct keyhash_result hresult;
1902 init_completion(&hresult.completion);
1904 req = ahash_request_alloc(tfm, GFP_KERNEL);
1908 /* Keep tfm keylen == 0 during hash of the long key */
1910 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1911 keyhash_complete, &hresult);
1913 sg_init_one(&sg[0], key, keylen);
1915 ahash_request_set_crypt(req, sg, hash, keylen);
1916 ret = crypto_ahash_digest(req);
1922 ret = wait_for_completion_interruptible(
1923 &hresult.completion);
1930 ahash_request_free(req);
1935 static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
1936 unsigned int keylen)
1938 struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1939 unsigned int blocksize =
1940 crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1941 unsigned int digestsize = crypto_ahash_digestsize(tfm);
1942 unsigned int keysize = keylen;
1943 u8 hash[SHA512_DIGEST_SIZE];
1946 if (keylen <= blocksize)
1947 memcpy(ctx->key, key, keysize);
1949 /* Must get the hash of the long key */
1950 ret = keyhash(tfm, key, keylen, hash);
1953 crypto_ahash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1957 keysize = digestsize;
1958 memcpy(ctx->key, hash, digestsize);
1961 ctx->keylen = keysize;
1967 struct talitos_alg_template {
1970 struct crypto_alg crypto;
1971 struct ahash_alg hash;
1973 __be32 desc_hdr_template;
1976 static struct talitos_alg_template driver_algs[] = {
1977 /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
1978 { .type = CRYPTO_ALG_TYPE_AEAD,
1980 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1981 .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1982 .cra_blocksize = AES_BLOCK_SIZE,
1983 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1985 .ivsize = AES_BLOCK_SIZE,
1986 .maxauthsize = SHA1_DIGEST_SIZE,
1989 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1990 DESC_HDR_SEL0_AESU |
1991 DESC_HDR_MODE0_AESU_CBC |
1992 DESC_HDR_SEL1_MDEUA |
1993 DESC_HDR_MODE1_MDEU_INIT |
1994 DESC_HDR_MODE1_MDEU_PAD |
1995 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1997 { .type = CRYPTO_ALG_TYPE_AEAD,
1999 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
2000 .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
2001 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2002 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2004 .ivsize = DES3_EDE_BLOCK_SIZE,
2005 .maxauthsize = SHA1_DIGEST_SIZE,
2008 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2010 DESC_HDR_MODE0_DEU_CBC |
2011 DESC_HDR_MODE0_DEU_3DES |
2012 DESC_HDR_SEL1_MDEUA |
2013 DESC_HDR_MODE1_MDEU_INIT |
2014 DESC_HDR_MODE1_MDEU_PAD |
2015 DESC_HDR_MODE1_MDEU_SHA1_HMAC,
2017 { .type = CRYPTO_ALG_TYPE_AEAD,
2019 .cra_name = "authenc(hmac(sha224),cbc(aes))",
2020 .cra_driver_name = "authenc-hmac-sha224-cbc-aes-talitos",
2021 .cra_blocksize = AES_BLOCK_SIZE,
2022 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2024 .ivsize = AES_BLOCK_SIZE,
2025 .maxauthsize = SHA224_DIGEST_SIZE,
2028 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2029 DESC_HDR_SEL0_AESU |
2030 DESC_HDR_MODE0_AESU_CBC |
2031 DESC_HDR_SEL1_MDEUA |
2032 DESC_HDR_MODE1_MDEU_INIT |
2033 DESC_HDR_MODE1_MDEU_PAD |
2034 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2036 { .type = CRYPTO_ALG_TYPE_AEAD,
2038 .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
2039 .cra_driver_name = "authenc-hmac-sha224-cbc-3des-talitos",
2040 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2041 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2043 .ivsize = DES3_EDE_BLOCK_SIZE,
2044 .maxauthsize = SHA224_DIGEST_SIZE,
2047 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2049 DESC_HDR_MODE0_DEU_CBC |
2050 DESC_HDR_MODE0_DEU_3DES |
2051 DESC_HDR_SEL1_MDEUA |
2052 DESC_HDR_MODE1_MDEU_INIT |
2053 DESC_HDR_MODE1_MDEU_PAD |
2054 DESC_HDR_MODE1_MDEU_SHA224_HMAC,
2056 { .type = CRYPTO_ALG_TYPE_AEAD,
2058 .cra_name = "authenc(hmac(sha256),cbc(aes))",
2059 .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
2060 .cra_blocksize = AES_BLOCK_SIZE,
2061 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2063 .ivsize = AES_BLOCK_SIZE,
2064 .maxauthsize = SHA256_DIGEST_SIZE,
2067 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2068 DESC_HDR_SEL0_AESU |
2069 DESC_HDR_MODE0_AESU_CBC |
2070 DESC_HDR_SEL1_MDEUA |
2071 DESC_HDR_MODE1_MDEU_INIT |
2072 DESC_HDR_MODE1_MDEU_PAD |
2073 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2075 { .type = CRYPTO_ALG_TYPE_AEAD,
2077 .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
2078 .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
2079 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2080 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2082 .ivsize = DES3_EDE_BLOCK_SIZE,
2083 .maxauthsize = SHA256_DIGEST_SIZE,
2086 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2088 DESC_HDR_MODE0_DEU_CBC |
2089 DESC_HDR_MODE0_DEU_3DES |
2090 DESC_HDR_SEL1_MDEUA |
2091 DESC_HDR_MODE1_MDEU_INIT |
2092 DESC_HDR_MODE1_MDEU_PAD |
2093 DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2095 { .type = CRYPTO_ALG_TYPE_AEAD,
2097 .cra_name = "authenc(hmac(sha384),cbc(aes))",
2098 .cra_driver_name = "authenc-hmac-sha384-cbc-aes-talitos",
2099 .cra_blocksize = AES_BLOCK_SIZE,
2100 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2102 .ivsize = AES_BLOCK_SIZE,
2103 .maxauthsize = SHA384_DIGEST_SIZE,
2106 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2107 DESC_HDR_SEL0_AESU |
2108 DESC_HDR_MODE0_AESU_CBC |
2109 DESC_HDR_SEL1_MDEUB |
2110 DESC_HDR_MODE1_MDEU_INIT |
2111 DESC_HDR_MODE1_MDEU_PAD |
2112 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2114 { .type = CRYPTO_ALG_TYPE_AEAD,
2116 .cra_name = "authenc(hmac(sha384),cbc(des3_ede))",
2117 .cra_driver_name = "authenc-hmac-sha384-cbc-3des-talitos",
2118 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2119 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2121 .ivsize = DES3_EDE_BLOCK_SIZE,
2122 .maxauthsize = SHA384_DIGEST_SIZE,
2125 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2127 DESC_HDR_MODE0_DEU_CBC |
2128 DESC_HDR_MODE0_DEU_3DES |
2129 DESC_HDR_SEL1_MDEUB |
2130 DESC_HDR_MODE1_MDEU_INIT |
2131 DESC_HDR_MODE1_MDEU_PAD |
2132 DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
2134 { .type = CRYPTO_ALG_TYPE_AEAD,
2136 .cra_name = "authenc(hmac(sha512),cbc(aes))",
2137 .cra_driver_name = "authenc-hmac-sha512-cbc-aes-talitos",
2138 .cra_blocksize = AES_BLOCK_SIZE,
2139 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2141 .ivsize = AES_BLOCK_SIZE,
2142 .maxauthsize = SHA512_DIGEST_SIZE,
2145 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2146 DESC_HDR_SEL0_AESU |
2147 DESC_HDR_MODE0_AESU_CBC |
2148 DESC_HDR_SEL1_MDEUB |
2149 DESC_HDR_MODE1_MDEU_INIT |
2150 DESC_HDR_MODE1_MDEU_PAD |
2151 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2153 { .type = CRYPTO_ALG_TYPE_AEAD,
2155 .cra_name = "authenc(hmac(sha512),cbc(des3_ede))",
2156 .cra_driver_name = "authenc-hmac-sha512-cbc-3des-talitos",
2157 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2158 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2160 .ivsize = DES3_EDE_BLOCK_SIZE,
2161 .maxauthsize = SHA512_DIGEST_SIZE,
2164 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2166 DESC_HDR_MODE0_DEU_CBC |
2167 DESC_HDR_MODE0_DEU_3DES |
2168 DESC_HDR_SEL1_MDEUB |
2169 DESC_HDR_MODE1_MDEU_INIT |
2170 DESC_HDR_MODE1_MDEU_PAD |
2171 DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
2173 { .type = CRYPTO_ALG_TYPE_AEAD,
2175 .cra_name = "authenc(hmac(md5),cbc(aes))",
2176 .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2177 .cra_blocksize = AES_BLOCK_SIZE,
2178 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2180 .ivsize = AES_BLOCK_SIZE,
2181 .maxauthsize = MD5_DIGEST_SIZE,
2184 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2185 DESC_HDR_SEL0_AESU |
2186 DESC_HDR_MODE0_AESU_CBC |
2187 DESC_HDR_SEL1_MDEUA |
2188 DESC_HDR_MODE1_MDEU_INIT |
2189 DESC_HDR_MODE1_MDEU_PAD |
2190 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2192 { .type = CRYPTO_ALG_TYPE_AEAD,
2194 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2195 .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2196 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2197 .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2199 .ivsize = DES3_EDE_BLOCK_SIZE,
2200 .maxauthsize = MD5_DIGEST_SIZE,
2203 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2205 DESC_HDR_MODE0_DEU_CBC |
2206 DESC_HDR_MODE0_DEU_3DES |
2207 DESC_HDR_SEL1_MDEUA |
2208 DESC_HDR_MODE1_MDEU_INIT |
2209 DESC_HDR_MODE1_MDEU_PAD |
2210 DESC_HDR_MODE1_MDEU_MD5_HMAC,
2212 /* ABLKCIPHER algorithms. */
2213 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2215 .cra_name = "cbc(aes)",
2216 .cra_driver_name = "cbc-aes-talitos",
2217 .cra_blocksize = AES_BLOCK_SIZE,
2218 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2221 .min_keysize = AES_MIN_KEY_SIZE,
2222 .max_keysize = AES_MAX_KEY_SIZE,
2223 .ivsize = AES_BLOCK_SIZE,
2226 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2227 DESC_HDR_SEL0_AESU |
2228 DESC_HDR_MODE0_AESU_CBC,
2230 { .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2232 .cra_name = "cbc(des3_ede)",
2233 .cra_driver_name = "cbc-3des-talitos",
2234 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2235 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2238 .min_keysize = DES3_EDE_KEY_SIZE,
2239 .max_keysize = DES3_EDE_KEY_SIZE,
2240 .ivsize = DES3_EDE_BLOCK_SIZE,
2243 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2245 DESC_HDR_MODE0_DEU_CBC |
2246 DESC_HDR_MODE0_DEU_3DES,
2248 /* AHASH algorithms. */
2249 { .type = CRYPTO_ALG_TYPE_AHASH,
2251 .halg.digestsize = MD5_DIGEST_SIZE,
2254 .cra_driver_name = "md5-talitos",
2255 .cra_blocksize = MD5_BLOCK_SIZE,
2256 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2260 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2261 DESC_HDR_SEL0_MDEUA |
2262 DESC_HDR_MODE0_MDEU_MD5,
2264 { .type = CRYPTO_ALG_TYPE_AHASH,
2266 .halg.digestsize = SHA1_DIGEST_SIZE,
2269 .cra_driver_name = "sha1-talitos",
2270 .cra_blocksize = SHA1_BLOCK_SIZE,
2271 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2275 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2276 DESC_HDR_SEL0_MDEUA |
2277 DESC_HDR_MODE0_MDEU_SHA1,
2279 { .type = CRYPTO_ALG_TYPE_AHASH,
2281 .halg.digestsize = SHA224_DIGEST_SIZE,
2283 .cra_name = "sha224",
2284 .cra_driver_name = "sha224-talitos",
2285 .cra_blocksize = SHA224_BLOCK_SIZE,
2286 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2290 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2291 DESC_HDR_SEL0_MDEUA |
2292 DESC_HDR_MODE0_MDEU_SHA224,
2294 { .type = CRYPTO_ALG_TYPE_AHASH,
2296 .halg.digestsize = SHA256_DIGEST_SIZE,
2298 .cra_name = "sha256",
2299 .cra_driver_name = "sha256-talitos",
2300 .cra_blocksize = SHA256_BLOCK_SIZE,
2301 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2305 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2306 DESC_HDR_SEL0_MDEUA |
2307 DESC_HDR_MODE0_MDEU_SHA256,
2309 { .type = CRYPTO_ALG_TYPE_AHASH,
2311 .halg.digestsize = SHA384_DIGEST_SIZE,
2313 .cra_name = "sha384",
2314 .cra_driver_name = "sha384-talitos",
2315 .cra_blocksize = SHA384_BLOCK_SIZE,
2316 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2320 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2321 DESC_HDR_SEL0_MDEUB |
2322 DESC_HDR_MODE0_MDEUB_SHA384,
2324 { .type = CRYPTO_ALG_TYPE_AHASH,
2326 .halg.digestsize = SHA512_DIGEST_SIZE,
2328 .cra_name = "sha512",
2329 .cra_driver_name = "sha512-talitos",
2330 .cra_blocksize = SHA512_BLOCK_SIZE,
2331 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2335 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2336 DESC_HDR_SEL0_MDEUB |
2337 DESC_HDR_MODE0_MDEUB_SHA512,
2339 { .type = CRYPTO_ALG_TYPE_AHASH,
2341 .halg.digestsize = MD5_DIGEST_SIZE,
2343 .cra_name = "hmac(md5)",
2344 .cra_driver_name = "hmac-md5-talitos",
2345 .cra_blocksize = MD5_BLOCK_SIZE,
2346 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2350 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2351 DESC_HDR_SEL0_MDEUA |
2352 DESC_HDR_MODE0_MDEU_MD5,
2354 { .type = CRYPTO_ALG_TYPE_AHASH,
2356 .halg.digestsize = SHA1_DIGEST_SIZE,
2358 .cra_name = "hmac(sha1)",
2359 .cra_driver_name = "hmac-sha1-talitos",
2360 .cra_blocksize = SHA1_BLOCK_SIZE,
2361 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2365 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2366 DESC_HDR_SEL0_MDEUA |
2367 DESC_HDR_MODE0_MDEU_SHA1,
2369 { .type = CRYPTO_ALG_TYPE_AHASH,
2371 .halg.digestsize = SHA224_DIGEST_SIZE,
2373 .cra_name = "hmac(sha224)",
2374 .cra_driver_name = "hmac-sha224-talitos",
2375 .cra_blocksize = SHA224_BLOCK_SIZE,
2376 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2380 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2381 DESC_HDR_SEL0_MDEUA |
2382 DESC_HDR_MODE0_MDEU_SHA224,
2384 { .type = CRYPTO_ALG_TYPE_AHASH,
2386 .halg.digestsize = SHA256_DIGEST_SIZE,
2388 .cra_name = "hmac(sha256)",
2389 .cra_driver_name = "hmac-sha256-talitos",
2390 .cra_blocksize = SHA256_BLOCK_SIZE,
2391 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2395 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2396 DESC_HDR_SEL0_MDEUA |
2397 DESC_HDR_MODE0_MDEU_SHA256,
2399 { .type = CRYPTO_ALG_TYPE_AHASH,
2401 .halg.digestsize = SHA384_DIGEST_SIZE,
2403 .cra_name = "hmac(sha384)",
2404 .cra_driver_name = "hmac-sha384-talitos",
2405 .cra_blocksize = SHA384_BLOCK_SIZE,
2406 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2410 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2411 DESC_HDR_SEL0_MDEUB |
2412 DESC_HDR_MODE0_MDEUB_SHA384,
2414 { .type = CRYPTO_ALG_TYPE_AHASH,
2416 .halg.digestsize = SHA512_DIGEST_SIZE,
2418 .cra_name = "hmac(sha512)",
2419 .cra_driver_name = "hmac-sha512-talitos",
2420 .cra_blocksize = SHA512_BLOCK_SIZE,
2421 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2425 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2426 DESC_HDR_SEL0_MDEUB |
2427 DESC_HDR_MODE0_MDEUB_SHA512,
2431 struct talitos_crypto_alg {
2432 struct list_head entry;
2434 struct talitos_alg_template algt;
2437 static int talitos_cra_init(struct crypto_tfm *tfm)
2439 struct crypto_alg *alg = tfm->__crt_alg;
2440 struct talitos_crypto_alg *talitos_alg;
2441 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2442 struct talitos_private *priv;
2444 if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2445 talitos_alg = container_of(__crypto_ahash_alg(alg),
2446 struct talitos_crypto_alg,
2449 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2452 /* update context with ptr to dev */
2453 ctx->dev = talitos_alg->dev;
2455 /* assign SEC channel to tfm in round-robin fashion */
2456 priv = dev_get_drvdata(ctx->dev);
2457 ctx->ch = atomic_inc_return(&priv->last_chan) &
2458 (priv->num_channels - 1);
2460 /* copy descriptor header template value */
2461 ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2463 /* select done notification */
2464 ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
2469 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2471 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2473 talitos_cra_init(tfm);
2475 /* random first IV */
2476 get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2481 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2483 struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2485 talitos_cra_init(tfm);
2488 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2489 sizeof(struct talitos_ahash_req_ctx));
2495 * given the alg's descriptor header template, determine whether descriptor
2496 * type and primary/secondary execution units required match the hw
2497 * capabilities description provided in the device tree node.
2499 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2501 struct talitos_private *priv = dev_get_drvdata(dev);
2504 ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2505 (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2507 if (SECONDARY_EU(desc_hdr_template))
2508 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2509 & priv->exec_units);
2514 static int talitos_remove(struct platform_device *ofdev)
2516 struct device *dev = &ofdev->dev;
2517 struct talitos_private *priv = dev_get_drvdata(dev);
2518 struct talitos_crypto_alg *t_alg, *n;
2521 list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2522 switch (t_alg->algt.type) {
2523 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2524 case CRYPTO_ALG_TYPE_AEAD:
2525 crypto_unregister_alg(&t_alg->algt.alg.crypto);
2527 case CRYPTO_ALG_TYPE_AHASH:
2528 crypto_unregister_ahash(&t_alg->algt.alg.hash);
2531 list_del(&t_alg->entry);
2535 if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2536 talitos_unregister_rng(dev);
2538 for (i = 0; i < priv->num_channels; i++)
2539 kfree(priv->chan[i].fifo);
2543 for (i = 0; i < 2; i++)
2545 free_irq(priv->irq[i], dev);
2546 irq_dispose_mapping(priv->irq[i]);
2549 tasklet_kill(&priv->done_task[0]);
2551 tasklet_kill(&priv->done_task[1]);
2555 dev_set_drvdata(dev, NULL);
2562 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2563 struct talitos_alg_template
2566 struct talitos_private *priv = dev_get_drvdata(dev);
2567 struct talitos_crypto_alg *t_alg;
2568 struct crypto_alg *alg;
2570 t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2572 return ERR_PTR(-ENOMEM);
2574 t_alg->algt = *template;
2576 switch (t_alg->algt.type) {
2577 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2578 alg = &t_alg->algt.alg.crypto;
2579 alg->cra_init = talitos_cra_init;
2580 alg->cra_type = &crypto_ablkcipher_type;
2581 alg->cra_ablkcipher.setkey = ablkcipher_setkey;
2582 alg->cra_ablkcipher.encrypt = ablkcipher_encrypt;
2583 alg->cra_ablkcipher.decrypt = ablkcipher_decrypt;
2584 alg->cra_ablkcipher.geniv = "eseqiv";
2586 case CRYPTO_ALG_TYPE_AEAD:
2587 alg = &t_alg->algt.alg.crypto;
2588 alg->cra_init = talitos_cra_init_aead;
2589 alg->cra_type = &crypto_aead_type;
2590 alg->cra_aead.setkey = aead_setkey;
2591 alg->cra_aead.setauthsize = aead_setauthsize;
2592 alg->cra_aead.encrypt = aead_encrypt;
2593 alg->cra_aead.decrypt = aead_decrypt;
2594 alg->cra_aead.givencrypt = aead_givencrypt;
2595 alg->cra_aead.geniv = "<built-in>";
2597 case CRYPTO_ALG_TYPE_AHASH:
2598 alg = &t_alg->algt.alg.hash.halg.base;
2599 alg->cra_init = talitos_cra_init_ahash;
2600 alg->cra_type = &crypto_ahash_type;
2601 t_alg->algt.alg.hash.init = ahash_init;
2602 t_alg->algt.alg.hash.update = ahash_update;
2603 t_alg->algt.alg.hash.final = ahash_final;
2604 t_alg->algt.alg.hash.finup = ahash_finup;
2605 t_alg->algt.alg.hash.digest = ahash_digest;
2606 t_alg->algt.alg.hash.setkey = ahash_setkey;
2608 if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
2609 !strncmp(alg->cra_name, "hmac", 4)) {
2611 return ERR_PTR(-ENOTSUPP);
2613 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2614 (!strcmp(alg->cra_name, "sha224") ||
2615 !strcmp(alg->cra_name, "hmac(sha224)"))) {
2616 t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2617 t_alg->algt.desc_hdr_template =
2618 DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2619 DESC_HDR_SEL0_MDEUA |
2620 DESC_HDR_MODE0_MDEU_SHA256;
2624 dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
2626 return ERR_PTR(-EINVAL);
2629 alg->cra_module = THIS_MODULE;
2630 alg->cra_priority = TALITOS_CRA_PRIORITY;
2631 alg->cra_alignmask = 0;
2632 alg->cra_ctxsize = sizeof(struct talitos_ctx);
2633 alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
2640 static int talitos_probe_irq(struct platform_device *ofdev)
2642 struct device *dev = &ofdev->dev;
2643 struct device_node *np = ofdev->dev.of_node;
2644 struct talitos_private *priv = dev_get_drvdata(dev);
2647 priv->irq[0] = irq_of_parse_and_map(np, 0);
2648 if (!priv->irq[0]) {
2649 dev_err(dev, "failed to map irq\n");
2653 priv->irq[1] = irq_of_parse_and_map(np, 1);
2655 /* get the primary irq line */
2656 if (!priv->irq[1]) {
2657 err = request_irq(priv->irq[0], talitos_interrupt_4ch, 0,
2658 dev_driver_string(dev), dev);
2662 err = request_irq(priv->irq[0], talitos_interrupt_ch0_2, 0,
2663 dev_driver_string(dev), dev);
2667 /* get the secondary irq line */
2668 err = request_irq(priv->irq[1], talitos_interrupt_ch1_3, 0,
2669 dev_driver_string(dev), dev);
2671 dev_err(dev, "failed to request secondary irq\n");
2672 irq_dispose_mapping(priv->irq[1]);
2680 dev_err(dev, "failed to request primary irq\n");
2681 irq_dispose_mapping(priv->irq[0]);
2688 static int talitos_probe(struct platform_device *ofdev)
2690 struct device *dev = &ofdev->dev;
2691 struct device_node *np = ofdev->dev.of_node;
2692 struct talitos_private *priv;
2693 const unsigned int *prop;
2696 priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2700 dev_set_drvdata(dev, priv);
2702 priv->ofdev = ofdev;
2704 spin_lock_init(&priv->reg_lock);
2706 err = talitos_probe_irq(ofdev);
2710 if (!priv->irq[1]) {
2711 tasklet_init(&priv->done_task[0], talitos_done_4ch,
2712 (unsigned long)dev);
2714 tasklet_init(&priv->done_task[0], talitos_done_ch0_2,
2715 (unsigned long)dev);
2716 tasklet_init(&priv->done_task[1], talitos_done_ch1_3,
2717 (unsigned long)dev);
2720 INIT_LIST_HEAD(&priv->alg_list);
2722 priv->reg = of_iomap(np, 0);
2724 dev_err(dev, "failed to of_iomap\n");
2729 /* get SEC version capabilities from device tree */
2730 prop = of_get_property(np, "fsl,num-channels", NULL);
2732 priv->num_channels = *prop;
2734 prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2736 priv->chfifo_len = *prop;
2738 prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2740 priv->exec_units = *prop;
2742 prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2744 priv->desc_types = *prop;
2746 if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2747 !priv->exec_units || !priv->desc_types) {
2748 dev_err(dev, "invalid property data in device tree node\n");
2753 if (of_device_is_compatible(np, "fsl,sec3.0"))
2754 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2756 if (of_device_is_compatible(np, "fsl,sec2.1"))
2757 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2758 TALITOS_FTR_SHA224_HWINIT |
2759 TALITOS_FTR_HMAC_OK;
2761 priv->chan = kzalloc(sizeof(struct talitos_channel) *
2762 priv->num_channels, GFP_KERNEL);
2764 dev_err(dev, "failed to allocate channel management space\n");
2769 for (i = 0; i < priv->num_channels; i++) {
2770 priv->chan[i].reg = priv->reg + TALITOS_CH_STRIDE * (i + 1);
2771 if (!priv->irq[1] || !(i & 1))
2772 priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
2775 for (i = 0; i < priv->num_channels; i++) {
2776 spin_lock_init(&priv->chan[i].head_lock);
2777 spin_lock_init(&priv->chan[i].tail_lock);
2780 priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2782 for (i = 0; i < priv->num_channels; i++) {
2783 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2784 priv->fifo_len, GFP_KERNEL);
2785 if (!priv->chan[i].fifo) {
2786 dev_err(dev, "failed to allocate request fifo %d\n", i);
2792 for (i = 0; i < priv->num_channels; i++)
2793 atomic_set(&priv->chan[i].submit_count,
2794 -(priv->chfifo_len - 1));
2796 dma_set_mask(dev, DMA_BIT_MASK(36));
2798 /* reset and initialize the h/w */
2799 err = init_device(dev);
2801 dev_err(dev, "failed to initialize device\n");
2805 /* register the RNG, if available */
2806 if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2807 err = talitos_register_rng(dev);
2809 dev_err(dev, "failed to register hwrng: %d\n", err);
2812 dev_info(dev, "hwrng\n");
2815 /* register crypto algorithms the device supports */
2816 for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2817 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2818 struct talitos_crypto_alg *t_alg;
2821 t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2822 if (IS_ERR(t_alg)) {
2823 err = PTR_ERR(t_alg);
2824 if (err == -ENOTSUPP)
2829 switch (t_alg->algt.type) {
2830 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2831 case CRYPTO_ALG_TYPE_AEAD:
2832 err = crypto_register_alg(
2833 &t_alg->algt.alg.crypto);
2834 name = t_alg->algt.alg.crypto.cra_driver_name;
2836 case CRYPTO_ALG_TYPE_AHASH:
2837 err = crypto_register_ahash(
2838 &t_alg->algt.alg.hash);
2840 t_alg->algt.alg.hash.halg.base.cra_driver_name;
2844 dev_err(dev, "%s alg registration failed\n",
2848 list_add_tail(&t_alg->entry, &priv->alg_list);
2851 if (!list_empty(&priv->alg_list))
2852 dev_info(dev, "%s algorithms registered in /proc/crypto\n",
2853 (char *)of_get_property(np, "compatible", NULL));
2858 talitos_remove(ofdev);
2863 static const struct of_device_id talitos_match[] = {
2865 .compatible = "fsl,sec2.0",
2869 MODULE_DEVICE_TABLE(of, talitos_match);
2871 static struct platform_driver talitos_driver = {
2874 .owner = THIS_MODULE,
2875 .of_match_table = talitos_match,
2877 .probe = talitos_probe,
2878 .remove = talitos_remove,
2881 module_platform_driver(talitos_driver);
2883 MODULE_LICENSE("GPL");
2884 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2885 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");