2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 #include <linux/kernel.h>
48 #include <linux/init.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/slab.h>
52 #include <linux/errno.h>
53 #include <linux/interrupt.h>
54 #include <adf_accel_devices.h>
55 #include <adf_common_drv.h>
57 #include <adf_cfg_strings.h>
58 #include <adf_cfg_common.h>
59 #include <adf_transport_access_macros.h>
60 #include <adf_transport_internal.h>
63 static int adf_enable_msix(struct adf_accel_dev *accel_dev)
65 struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
66 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
67 uint32_t msix_num_entries = hw_data->num_banks + 1;
70 for (i = 0; i < msix_num_entries; i++)
71 pci_dev_info->msix_entries.entries[i].entry = i;
73 if (pci_enable_msix_exact(pci_dev_info->pci_dev,
74 pci_dev_info->msix_entries.entries,
76 pr_err("QAT: Failed to enable MSIX IRQ\n");
82 static void adf_disable_msix(struct adf_accel_pci *pci_dev_info)
84 pci_disable_msix(pci_dev_info->pci_dev);
87 static irqreturn_t adf_msix_isr_bundle(int irq, void *bank_ptr)
89 struct adf_etr_bank_data *bank = bank_ptr;
91 WRITE_CSR_INT_FLAG_AND_COL(bank->csr_addr, bank->bank_number, 0);
92 tasklet_hi_schedule(&bank->resp_handler);
96 static irqreturn_t adf_msix_isr_ae(int irq, void *dev_ptr)
98 struct adf_accel_dev *accel_dev = dev_ptr;
100 pr_info("QAT: qat_dev%d spurious AE interrupt\n", accel_dev->accel_id);
104 static int adf_request_irqs(struct adf_accel_dev *accel_dev)
106 struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
107 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
108 struct msix_entry *msixe = pci_dev_info->msix_entries.entries;
109 struct adf_etr_data *etr_data = accel_dev->transport;
113 /* Request msix irq for all banks */
114 for (i = 0; i < hw_data->num_banks; i++) {
115 struct adf_etr_bank_data *bank = &etr_data->banks[i];
116 unsigned int cpu, cpus = num_online_cpus();
118 name = *(pci_dev_info->msix_entries.names + i);
119 snprintf(name, ADF_MAX_MSIX_VECTOR_NAME,
120 "qat%d-bundle%d", accel_dev->accel_id, i);
121 ret = request_irq(msixe[i].vector,
122 adf_msix_isr_bundle, 0, name, bank);
124 pr_err("QAT: failed to enable irq %d for %s\n",
125 msixe[i].vector, name);
129 cpu = ((accel_dev->accel_id * hw_data->num_banks) + i) % cpus;
130 irq_set_affinity_hint(msixe[i].vector, get_cpu_mask(cpu));
133 /* Request msix irq for AE */
134 name = *(pci_dev_info->msix_entries.names + i);
135 snprintf(name, ADF_MAX_MSIX_VECTOR_NAME,
136 "qat%d-ae-cluster", accel_dev->accel_id);
137 ret = request_irq(msixe[i].vector, adf_msix_isr_ae, 0, name, accel_dev);
139 pr_err("QAT: failed to enable irq %d, for %s\n",
140 msixe[i].vector, name);
146 static void adf_free_irqs(struct adf_accel_dev *accel_dev)
148 struct adf_accel_pci *pci_dev_info = &accel_dev->accel_pci_dev;
149 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
150 struct msix_entry *msixe = pci_dev_info->msix_entries.entries;
151 struct adf_etr_data *etr_data = accel_dev->transport;
154 for (i = 0; i < hw_data->num_banks; i++) {
155 irq_set_affinity_hint(msixe[i].vector, NULL);
156 free_irq(msixe[i].vector, &etr_data->banks[i]);
158 irq_set_affinity_hint(msixe[i].vector, NULL);
159 free_irq(msixe[i].vector, accel_dev);
162 static int adf_isr_alloc_msix_entry_table(struct adf_accel_dev *accel_dev)
166 struct msix_entry *entries;
167 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
168 uint32_t msix_num_entries = hw_data->num_banks + 1;
170 entries = kzalloc_node(msix_num_entries * sizeof(*entries),
171 GFP_KERNEL, dev_to_node(&GET_DEV(accel_dev)));
175 names = kcalloc(msix_num_entries, sizeof(char *), GFP_KERNEL);
180 for (i = 0; i < msix_num_entries; i++) {
181 *(names + i) = kzalloc(ADF_MAX_MSIX_VECTOR_NAME, GFP_KERNEL);
185 accel_dev->accel_pci_dev.msix_entries.entries = entries;
186 accel_dev->accel_pci_dev.msix_entries.names = names;
189 for (i = 0; i < msix_num_entries; i++)
196 static void adf_isr_free_msix_entry_table(struct adf_accel_dev *accel_dev)
198 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
199 uint32_t msix_num_entries = hw_data->num_banks + 1;
200 char **names = accel_dev->accel_pci_dev.msix_entries.names;
203 kfree(accel_dev->accel_pci_dev.msix_entries.entries);
204 for (i = 0; i < msix_num_entries; i++)
209 static int adf_setup_bh(struct adf_accel_dev *accel_dev)
211 struct adf_etr_data *priv_data = accel_dev->transport;
212 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
215 for (i = 0; i < hw_data->num_banks; i++)
216 tasklet_init(&priv_data->banks[i].resp_handler,
217 adf_response_handler,
218 (unsigned long)&priv_data->banks[i]);
222 static void adf_cleanup_bh(struct adf_accel_dev *accel_dev)
224 struct adf_etr_data *priv_data = accel_dev->transport;
225 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
228 for (i = 0; i < hw_data->num_banks; i++) {
229 tasklet_disable(&priv_data->banks[i].resp_handler);
230 tasklet_kill(&priv_data->banks[i].resp_handler);
234 void adf_isr_resource_free(struct adf_accel_dev *accel_dev)
236 adf_free_irqs(accel_dev);
237 adf_cleanup_bh(accel_dev);
238 adf_disable_msix(&accel_dev->accel_pci_dev);
239 adf_isr_free_msix_entry_table(accel_dev);
242 int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev)
246 ret = adf_isr_alloc_msix_entry_table(accel_dev);
249 if (adf_enable_msix(accel_dev))
252 if (adf_setup_bh(accel_dev))
255 if (adf_request_irqs(accel_dev))
260 adf_isr_resource_free(accel_dev);