2 * Hash algorithms supported by the CESA: MD5, SHA1 and SHA256.
4 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
5 * Author: Arnaud Ebalard <arno@natisbad.org>
7 * This work is based on an initial version written by
8 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #include <crypto/md5.h>
16 #include <crypto/sha.h>
20 struct mv_cesa_ahash_dma_iter {
21 struct mv_cesa_dma_iter base;
22 struct mv_cesa_sg_dma_iter src;
26 mv_cesa_ahash_req_iter_init(struct mv_cesa_ahash_dma_iter *iter,
27 struct ahash_request *req)
29 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
30 unsigned int len = req->nbytes;
33 len = (len + creq->cache_ptr) & ~CESA_HASH_BLOCK_SIZE_MSK;
35 mv_cesa_req_dma_iter_init(&iter->base, len);
36 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE);
37 iter->src.op_offset = creq->cache_ptr;
41 mv_cesa_ahash_req_iter_next_op(struct mv_cesa_ahash_dma_iter *iter)
43 iter->src.op_offset = 0;
45 return mv_cesa_req_dma_iter_next_op(&iter->base);
48 static inline int mv_cesa_ahash_dma_alloc_cache(struct mv_cesa_ahash_req *creq,
51 struct mv_cesa_ahash_dma_req *dreq = &creq->req.dma;
53 creq->cache = dma_pool_alloc(cesa_dev->dma->cache_pool, flags,
61 static inline int mv_cesa_ahash_std_alloc_cache(struct mv_cesa_ahash_req *creq,
64 creq->cache = kzalloc(CESA_MAX_HASH_BLOCK_SIZE, flags);
71 static int mv_cesa_ahash_alloc_cache(struct ahash_request *req)
73 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
74 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
75 GFP_KERNEL : GFP_ATOMIC;
81 if (creq->req.base.type == CESA_DMA_REQ)
82 ret = mv_cesa_ahash_dma_alloc_cache(creq, flags);
84 ret = mv_cesa_ahash_std_alloc_cache(creq, flags);
89 static inline void mv_cesa_ahash_dma_free_cache(struct mv_cesa_ahash_req *creq)
91 dma_pool_free(cesa_dev->dma->cache_pool, creq->cache,
92 creq->req.dma.cache_dma);
95 static inline void mv_cesa_ahash_std_free_cache(struct mv_cesa_ahash_req *creq)
100 static void mv_cesa_ahash_free_cache(struct mv_cesa_ahash_req *creq)
105 if (creq->req.base.type == CESA_DMA_REQ)
106 mv_cesa_ahash_dma_free_cache(creq);
108 mv_cesa_ahash_std_free_cache(creq);
113 static int mv_cesa_ahash_dma_alloc_padding(struct mv_cesa_ahash_dma_req *req,
119 req->padding = dma_pool_alloc(cesa_dev->dma->padding_pool, flags,
127 static void mv_cesa_ahash_dma_free_padding(struct mv_cesa_ahash_dma_req *req)
132 dma_pool_free(cesa_dev->dma->padding_pool, req->padding,
137 static inline void mv_cesa_ahash_dma_last_cleanup(struct ahash_request *req)
139 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
141 mv_cesa_ahash_dma_free_padding(&creq->req.dma);
144 static inline void mv_cesa_ahash_dma_cleanup(struct ahash_request *req)
146 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
148 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
149 mv_cesa_dma_cleanup(&creq->req.dma.base);
152 static inline void mv_cesa_ahash_cleanup(struct ahash_request *req)
154 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
156 if (creq->req.base.type == CESA_DMA_REQ)
157 mv_cesa_ahash_dma_cleanup(req);
160 static void mv_cesa_ahash_last_cleanup(struct ahash_request *req)
162 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
164 mv_cesa_ahash_free_cache(creq);
166 if (creq->req.base.type == CESA_DMA_REQ)
167 mv_cesa_ahash_dma_last_cleanup(req);
170 static int mv_cesa_ahash_pad_len(struct mv_cesa_ahash_req *creq)
172 unsigned int index, padlen;
174 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
175 padlen = (index < 56) ? (56 - index) : (64 + 56 - index);
180 static int mv_cesa_ahash_pad_req(struct mv_cesa_ahash_req *creq, u8 *buf)
182 unsigned int index, padlen;
185 /* Pad out to 56 mod 64 */
186 index = creq->len & CESA_HASH_BLOCK_SIZE_MSK;
187 padlen = mv_cesa_ahash_pad_len(creq);
188 memset(buf + 1, 0, padlen - 1);
191 __le64 bits = cpu_to_le64(creq->len << 3);
192 memcpy(buf + padlen, &bits, sizeof(bits));
194 __be64 bits = cpu_to_be64(creq->len << 3);
195 memcpy(buf + padlen, &bits, sizeof(bits));
201 static void mv_cesa_ahash_std_step(struct ahash_request *req)
203 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
204 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
205 struct mv_cesa_engine *engine = sreq->base.engine;
206 struct mv_cesa_op_ctx *op;
207 unsigned int new_cache_ptr = 0;
212 memcpy(engine->sram + CESA_SA_DATA_SRAM_OFFSET, creq->cache,
215 len = min_t(size_t, req->nbytes + creq->cache_ptr - sreq->offset,
216 CESA_SA_SRAM_PAYLOAD_SIZE);
218 if (!creq->last_req) {
219 new_cache_ptr = len & CESA_HASH_BLOCK_SIZE_MSK;
220 len &= ~CESA_HASH_BLOCK_SIZE_MSK;
223 if (len - creq->cache_ptr)
224 sreq->offset += sg_pcopy_to_buffer(req->src, creq->src_nents,
226 CESA_SA_DATA_SRAM_OFFSET +
228 len - creq->cache_ptr,
233 frag_mode = mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK;
235 if (creq->last_req && sreq->offset == req->nbytes &&
236 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
237 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
238 frag_mode = CESA_SA_DESC_CFG_NOT_FRAG;
239 else if (frag_mode == CESA_SA_DESC_CFG_MID_FRAG)
240 frag_mode = CESA_SA_DESC_CFG_LAST_FRAG;
243 if (frag_mode == CESA_SA_DESC_CFG_NOT_FRAG ||
244 frag_mode == CESA_SA_DESC_CFG_LAST_FRAG) {
246 creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
247 mv_cesa_set_mac_op_total_len(op, creq->len);
249 int trailerlen = mv_cesa_ahash_pad_len(creq) + 8;
251 if (len + trailerlen > CESA_SA_SRAM_PAYLOAD_SIZE) {
252 len &= CESA_HASH_BLOCK_SIZE_MSK;
253 new_cache_ptr = 64 - trailerlen;
256 CESA_SA_DATA_SRAM_OFFSET + len,
259 len += mv_cesa_ahash_pad_req(creq,
261 CESA_SA_DATA_SRAM_OFFSET);
264 if (frag_mode == CESA_SA_DESC_CFG_LAST_FRAG)
265 frag_mode = CESA_SA_DESC_CFG_MID_FRAG;
267 frag_mode = CESA_SA_DESC_CFG_FIRST_FRAG;
271 mv_cesa_set_mac_op_frag_len(op, len);
272 mv_cesa_update_op_cfg(op, frag_mode, CESA_SA_DESC_CFG_FRAG_MSK);
274 /* FIXME: only update enc_len field */
275 memcpy(engine->sram, op, sizeof(*op));
277 if (frag_mode == CESA_SA_DESC_CFG_FIRST_FRAG)
278 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
279 CESA_SA_DESC_CFG_FRAG_MSK);
281 creq->cache_ptr = new_cache_ptr;
283 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACCEL0_DONE);
284 writel(CESA_SA_CFG_PARA_DIS, engine->regs + CESA_SA_CFG);
285 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
288 static int mv_cesa_ahash_std_process(struct ahash_request *req, u32 status)
290 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
291 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
293 if (sreq->offset < (req->nbytes - creq->cache_ptr))
299 static inline void mv_cesa_ahash_dma_prepare(struct ahash_request *req)
301 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
302 struct mv_cesa_tdma_req *dreq = &creq->req.dma.base;
304 mv_cesa_dma_prepare(dreq, dreq->base.engine);
307 static void mv_cesa_ahash_std_prepare(struct ahash_request *req)
309 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
310 struct mv_cesa_ahash_std_req *sreq = &creq->req.std;
311 struct mv_cesa_engine *engine = sreq->base.engine;
314 mv_cesa_adjust_op(engine, &creq->op_tmpl);
315 memcpy(engine->sram, &creq->op_tmpl, sizeof(creq->op_tmpl));
318 static void mv_cesa_ahash_step(struct crypto_async_request *req)
320 struct ahash_request *ahashreq = ahash_request_cast(req);
321 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
323 if (creq->req.base.type == CESA_DMA_REQ)
324 mv_cesa_dma_step(&creq->req.dma.base);
326 mv_cesa_ahash_std_step(ahashreq);
329 static int mv_cesa_ahash_process(struct crypto_async_request *req, u32 status)
331 struct ahash_request *ahashreq = ahash_request_cast(req);
332 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
333 struct mv_cesa_engine *engine = creq->req.base.engine;
334 unsigned int digsize;
337 if (creq->req.base.type == CESA_DMA_REQ)
338 ret = mv_cesa_dma_process(&creq->req.dma.base, status);
340 ret = mv_cesa_ahash_std_process(ahashreq, status);
342 if (ret == -EINPROGRESS)
345 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
346 for (i = 0; i < digsize / 4; i++)
347 creq->state[i] = readl(engine->regs + CESA_IVDIG(i));
350 sg_pcopy_to_buffer(ahashreq->src, creq->src_nents,
353 ahashreq->nbytes - creq->cache_ptr);
355 if (creq->last_req) {
357 * Hardware's MD5 digest is in little endian format, but
358 * SHA in big endian format
361 __le32 *result = (void *)ahashreq->result;
363 for (i = 0; i < digsize / 4; i++)
364 result[i] = cpu_to_le32(creq->state[i]);
366 __be32 *result = (void *)ahashreq->result;
368 for (i = 0; i < digsize / 4; i++)
369 result[i] = cpu_to_be32(creq->state[i]);
376 static void mv_cesa_ahash_prepare(struct crypto_async_request *req,
377 struct mv_cesa_engine *engine)
379 struct ahash_request *ahashreq = ahash_request_cast(req);
380 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
381 unsigned int digsize;
384 creq->req.base.engine = engine;
386 if (creq->req.base.type == CESA_DMA_REQ)
387 mv_cesa_ahash_dma_prepare(ahashreq);
389 mv_cesa_ahash_std_prepare(ahashreq);
391 digsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(ahashreq));
392 for (i = 0; i < digsize / 4; i++)
393 writel(creq->state[i],
394 engine->regs + CESA_IVDIG(i));
397 static void mv_cesa_ahash_req_cleanup(struct crypto_async_request *req)
399 struct ahash_request *ahashreq = ahash_request_cast(req);
400 struct mv_cesa_ahash_req *creq = ahash_request_ctx(ahashreq);
403 mv_cesa_ahash_last_cleanup(ahashreq);
405 mv_cesa_ahash_cleanup(ahashreq);
408 static const struct mv_cesa_req_ops mv_cesa_ahash_req_ops = {
409 .step = mv_cesa_ahash_step,
410 .process = mv_cesa_ahash_process,
411 .prepare = mv_cesa_ahash_prepare,
412 .cleanup = mv_cesa_ahash_req_cleanup,
415 static int mv_cesa_ahash_init(struct ahash_request *req,
416 struct mv_cesa_op_ctx *tmpl, bool algo_le)
418 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
420 memset(creq, 0, sizeof(*creq));
421 mv_cesa_update_op_cfg(tmpl,
422 CESA_SA_DESC_CFG_OP_MAC_ONLY |
423 CESA_SA_DESC_CFG_FIRST_FRAG,
424 CESA_SA_DESC_CFG_OP_MSK |
425 CESA_SA_DESC_CFG_FRAG_MSK);
426 mv_cesa_set_mac_op_total_len(tmpl, 0);
427 mv_cesa_set_mac_op_frag_len(tmpl, 0);
428 creq->op_tmpl = *tmpl;
430 creq->algo_le = algo_le;
435 static inline int mv_cesa_ahash_cra_init(struct crypto_tfm *tfm)
437 struct mv_cesa_hash_ctx *ctx = crypto_tfm_ctx(tfm);
439 ctx->base.ops = &mv_cesa_ahash_req_ops;
441 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
442 sizeof(struct mv_cesa_ahash_req));
446 static int mv_cesa_ahash_cache_req(struct ahash_request *req, bool *cached)
448 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
451 if (((creq->cache_ptr + req->nbytes) & CESA_HASH_BLOCK_SIZE_MSK) &&
453 ret = mv_cesa_ahash_alloc_cache(req);
458 if (creq->cache_ptr + req->nbytes < 64 && !creq->last_req) {
464 sg_pcopy_to_buffer(req->src, creq->src_nents,
465 creq->cache + creq->cache_ptr,
468 creq->cache_ptr += req->nbytes;
474 static struct mv_cesa_op_ctx *
475 mv_cesa_ahash_dma_add_cache(struct mv_cesa_tdma_chain *chain,
476 struct mv_cesa_ahash_dma_iter *dma_iter,
477 struct mv_cesa_ahash_req *creq,
480 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
481 struct mv_cesa_op_ctx *op = NULL;
484 if (!creq->cache_ptr)
487 ret = mv_cesa_dma_add_data_transfer(chain,
488 CESA_SA_DATA_SRAM_OFFSET,
489 ahashdreq->cache_dma,
491 CESA_TDMA_DST_IN_SRAM,
496 if (!dma_iter->base.op_len) {
497 op = mv_cesa_dma_add_op(chain, &creq->op_tmpl, false, flags);
501 mv_cesa_set_mac_op_frag_len(op, creq->cache_ptr);
503 /* Add dummy desc to launch crypto operation */
504 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
512 static struct mv_cesa_op_ctx *
513 mv_cesa_ahash_dma_add_data(struct mv_cesa_tdma_chain *chain,
514 struct mv_cesa_ahash_dma_iter *dma_iter,
515 struct mv_cesa_ahash_req *creq,
518 struct mv_cesa_op_ctx *op;
521 op = mv_cesa_dma_add_op(chain, &creq->op_tmpl, false, flags);
525 mv_cesa_set_mac_op_frag_len(op, dma_iter->base.op_len);
527 if ((mv_cesa_get_op_cfg(&creq->op_tmpl) & CESA_SA_DESC_CFG_FRAG_MSK) ==
528 CESA_SA_DESC_CFG_FIRST_FRAG)
529 mv_cesa_update_op_cfg(&creq->op_tmpl,
530 CESA_SA_DESC_CFG_MID_FRAG,
531 CESA_SA_DESC_CFG_FRAG_MSK);
533 /* Add input transfers */
534 ret = mv_cesa_dma_add_op_transfers(chain, &dma_iter->base,
535 &dma_iter->src, flags);
539 /* Add dummy desc to launch crypto operation */
540 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
547 static struct mv_cesa_op_ctx *
548 mv_cesa_ahash_dma_last_req(struct mv_cesa_tdma_chain *chain,
549 struct mv_cesa_ahash_dma_iter *dma_iter,
550 struct mv_cesa_ahash_req *creq,
551 struct mv_cesa_op_ctx *op,
554 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
555 unsigned int len, trailerlen, padoff = 0;
561 if (op && creq->len <= CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX) {
562 u32 frag = CESA_SA_DESC_CFG_NOT_FRAG;
564 if ((mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) !=
565 CESA_SA_DESC_CFG_FIRST_FRAG)
566 frag = CESA_SA_DESC_CFG_LAST_FRAG;
568 mv_cesa_update_op_cfg(op, frag, CESA_SA_DESC_CFG_FRAG_MSK);
573 ret = mv_cesa_ahash_dma_alloc_padding(ahashdreq, flags);
577 trailerlen = mv_cesa_ahash_pad_req(creq, ahashdreq->padding);
580 len = min(CESA_SA_SRAM_PAYLOAD_SIZE - dma_iter->base.op_len,
583 ret = mv_cesa_dma_add_data_transfer(chain,
584 CESA_SA_DATA_SRAM_OFFSET +
585 dma_iter->base.op_len,
586 ahashdreq->padding_dma,
587 len, CESA_TDMA_DST_IN_SRAM,
592 mv_cesa_update_op_cfg(op, CESA_SA_DESC_CFG_MID_FRAG,
593 CESA_SA_DESC_CFG_FRAG_MSK);
594 mv_cesa_set_mac_op_frag_len(op,
595 dma_iter->base.op_len + len);
600 if (padoff >= trailerlen)
603 if ((mv_cesa_get_op_cfg(&creq->op_tmpl) & CESA_SA_DESC_CFG_FRAG_MSK) !=
604 CESA_SA_DESC_CFG_FIRST_FRAG)
605 mv_cesa_update_op_cfg(&creq->op_tmpl,
606 CESA_SA_DESC_CFG_MID_FRAG,
607 CESA_SA_DESC_CFG_FRAG_MSK);
609 op = mv_cesa_dma_add_op(chain, &creq->op_tmpl, false, flags);
613 mv_cesa_set_mac_op_frag_len(op, trailerlen - padoff);
615 ret = mv_cesa_dma_add_data_transfer(chain,
616 CESA_SA_DATA_SRAM_OFFSET,
617 ahashdreq->padding_dma +
620 CESA_TDMA_DST_IN_SRAM,
625 /* Add dummy desc to launch crypto operation */
626 ret = mv_cesa_dma_add_dummy_launch(chain, flags);
633 static int mv_cesa_ahash_dma_req_init(struct ahash_request *req)
635 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
636 gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
637 GFP_KERNEL : GFP_ATOMIC;
638 struct mv_cesa_ahash_dma_req *ahashdreq = &creq->req.dma;
639 struct mv_cesa_tdma_req *dreq = &ahashdreq->base;
640 struct mv_cesa_tdma_chain chain;
641 struct mv_cesa_ahash_dma_iter iter;
642 struct mv_cesa_op_ctx *op = NULL;
645 dreq->chain.first = NULL;
646 dreq->chain.last = NULL;
648 if (creq->src_nents) {
649 ret = dma_map_sg(cesa_dev->dev, req->src, creq->src_nents,
657 mv_cesa_tdma_desc_iter_init(&chain);
658 mv_cesa_ahash_req_iter_init(&iter, req);
660 op = mv_cesa_ahash_dma_add_cache(&chain, &iter,
668 if (!iter.base.op_len)
671 op = mv_cesa_ahash_dma_add_data(&chain, &iter,
677 } while (mv_cesa_ahash_req_iter_next_op(&iter));
679 op = mv_cesa_ahash_dma_last_req(&chain, &iter, creq, op, flags);
686 /* Add dummy desc to wait for crypto operation end */
687 ret = mv_cesa_dma_add_dummy_end(&chain, flags);
693 creq->cache_ptr = req->nbytes + creq->cache_ptr -
703 mv_cesa_dma_cleanup(dreq);
704 dma_unmap_sg(cesa_dev->dev, req->src, creq->src_nents, DMA_TO_DEVICE);
707 mv_cesa_ahash_last_cleanup(req);
712 static int mv_cesa_ahash_req_init(struct ahash_request *req, bool *cached)
714 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
717 if (cesa_dev->caps->has_tdma)
718 creq->req.base.type = CESA_DMA_REQ;
720 creq->req.base.type = CESA_STD_REQ;
722 creq->src_nents = sg_nents_for_len(req->src, req->nbytes);
724 ret = mv_cesa_ahash_cache_req(req, cached);
731 if (creq->req.base.type == CESA_DMA_REQ)
732 ret = mv_cesa_ahash_dma_req_init(req);
737 static int mv_cesa_ahash_update(struct ahash_request *req)
739 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
743 creq->len += req->nbytes;
744 ret = mv_cesa_ahash_req_init(req, &cached);
751 ret = mv_cesa_queue_req(&req->base);
752 if (ret && ret != -EINPROGRESS) {
753 mv_cesa_ahash_cleanup(req);
760 static int mv_cesa_ahash_final(struct ahash_request *req)
762 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
763 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
767 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
768 creq->last_req = true;
771 ret = mv_cesa_ahash_req_init(req, &cached);
778 ret = mv_cesa_queue_req(&req->base);
779 if (ret && ret != -EINPROGRESS)
780 mv_cesa_ahash_cleanup(req);
785 static int mv_cesa_ahash_finup(struct ahash_request *req)
787 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
788 struct mv_cesa_op_ctx *tmpl = &creq->op_tmpl;
792 creq->len += req->nbytes;
793 mv_cesa_set_mac_op_total_len(tmpl, creq->len);
794 creq->last_req = true;
796 ret = mv_cesa_ahash_req_init(req, &cached);
803 ret = mv_cesa_queue_req(&req->base);
804 if (ret && ret != -EINPROGRESS)
805 mv_cesa_ahash_cleanup(req);
810 static int mv_cesa_ahash_export(struct ahash_request *req, void *hash,
811 u64 *len, void *cache)
813 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
814 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
815 unsigned int digsize = crypto_ahash_digestsize(ahash);
816 unsigned int blocksize;
818 blocksize = crypto_ahash_blocksize(ahash);
821 memcpy(hash, creq->state, digsize);
822 memset(cache, 0, blocksize);
824 memcpy(cache, creq->cache, creq->cache_ptr);
829 static int mv_cesa_ahash_import(struct ahash_request *req, const void *hash,
830 u64 len, const void *cache)
832 struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
833 struct mv_cesa_ahash_req *creq = ahash_request_ctx(req);
834 unsigned int digsize = crypto_ahash_digestsize(ahash);
835 unsigned int blocksize;
836 unsigned int cache_ptr;
839 ret = crypto_ahash_init(req);
843 blocksize = crypto_ahash_blocksize(ahash);
844 if (len >= blocksize)
845 mv_cesa_update_op_cfg(&creq->op_tmpl,
846 CESA_SA_DESC_CFG_MID_FRAG,
847 CESA_SA_DESC_CFG_FRAG_MSK);
850 memcpy(creq->state, hash, digsize);
853 cache_ptr = do_div(len, blocksize);
857 ret = mv_cesa_ahash_alloc_cache(req);
861 memcpy(creq->cache, cache, cache_ptr);
862 creq->cache_ptr = cache_ptr;
867 static int mv_cesa_md5_init(struct ahash_request *req)
869 struct mv_cesa_op_ctx tmpl = { };
871 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_MD5);
873 mv_cesa_ahash_init(req, &tmpl, true);
878 static int mv_cesa_md5_export(struct ahash_request *req, void *out)
880 struct md5_state *out_state = out;
882 return mv_cesa_ahash_export(req, out_state->hash,
883 &out_state->byte_count, out_state->block);
886 static int mv_cesa_md5_import(struct ahash_request *req, const void *in)
888 const struct md5_state *in_state = in;
890 return mv_cesa_ahash_import(req, in_state->hash, in_state->byte_count,
894 static int mv_cesa_md5_digest(struct ahash_request *req)
898 ret = mv_cesa_md5_init(req);
902 return mv_cesa_ahash_finup(req);
905 struct ahash_alg mv_md5_alg = {
906 .init = mv_cesa_md5_init,
907 .update = mv_cesa_ahash_update,
908 .final = mv_cesa_ahash_final,
909 .finup = mv_cesa_ahash_finup,
910 .digest = mv_cesa_md5_digest,
911 .export = mv_cesa_md5_export,
912 .import = mv_cesa_md5_import,
914 .digestsize = MD5_DIGEST_SIZE,
915 .statesize = sizeof(struct md5_state),
918 .cra_driver_name = "mv-md5",
920 .cra_flags = CRYPTO_ALG_ASYNC |
921 CRYPTO_ALG_KERN_DRIVER_ONLY,
922 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
923 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
924 .cra_init = mv_cesa_ahash_cra_init,
925 .cra_module = THIS_MODULE,
930 static int mv_cesa_sha1_init(struct ahash_request *req)
932 struct mv_cesa_op_ctx tmpl = { };
934 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA1);
936 mv_cesa_ahash_init(req, &tmpl, false);
941 static int mv_cesa_sha1_export(struct ahash_request *req, void *out)
943 struct sha1_state *out_state = out;
945 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
949 static int mv_cesa_sha1_import(struct ahash_request *req, const void *in)
951 const struct sha1_state *in_state = in;
953 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
957 static int mv_cesa_sha1_digest(struct ahash_request *req)
961 ret = mv_cesa_sha1_init(req);
965 return mv_cesa_ahash_finup(req);
968 struct ahash_alg mv_sha1_alg = {
969 .init = mv_cesa_sha1_init,
970 .update = mv_cesa_ahash_update,
971 .final = mv_cesa_ahash_final,
972 .finup = mv_cesa_ahash_finup,
973 .digest = mv_cesa_sha1_digest,
974 .export = mv_cesa_sha1_export,
975 .import = mv_cesa_sha1_import,
977 .digestsize = SHA1_DIGEST_SIZE,
978 .statesize = sizeof(struct sha1_state),
981 .cra_driver_name = "mv-sha1",
983 .cra_flags = CRYPTO_ALG_ASYNC |
984 CRYPTO_ALG_KERN_DRIVER_ONLY,
985 .cra_blocksize = SHA1_BLOCK_SIZE,
986 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
987 .cra_init = mv_cesa_ahash_cra_init,
988 .cra_module = THIS_MODULE,
993 static int mv_cesa_sha256_init(struct ahash_request *req)
995 struct mv_cesa_op_ctx tmpl = { };
997 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_SHA256);
999 mv_cesa_ahash_init(req, &tmpl, false);
1004 static int mv_cesa_sha256_digest(struct ahash_request *req)
1008 ret = mv_cesa_sha256_init(req);
1012 return mv_cesa_ahash_finup(req);
1015 static int mv_cesa_sha256_export(struct ahash_request *req, void *out)
1017 struct sha256_state *out_state = out;
1019 return mv_cesa_ahash_export(req, out_state->state, &out_state->count,
1023 static int mv_cesa_sha256_import(struct ahash_request *req, const void *in)
1025 const struct sha256_state *in_state = in;
1027 return mv_cesa_ahash_import(req, in_state->state, in_state->count,
1031 struct ahash_alg mv_sha256_alg = {
1032 .init = mv_cesa_sha256_init,
1033 .update = mv_cesa_ahash_update,
1034 .final = mv_cesa_ahash_final,
1035 .finup = mv_cesa_ahash_finup,
1036 .digest = mv_cesa_sha256_digest,
1037 .export = mv_cesa_sha256_export,
1038 .import = mv_cesa_sha256_import,
1040 .digestsize = SHA256_DIGEST_SIZE,
1041 .statesize = sizeof(struct sha256_state),
1043 .cra_name = "sha256",
1044 .cra_driver_name = "mv-sha256",
1045 .cra_priority = 300,
1046 .cra_flags = CRYPTO_ALG_ASYNC |
1047 CRYPTO_ALG_KERN_DRIVER_ONLY,
1048 .cra_blocksize = SHA256_BLOCK_SIZE,
1049 .cra_ctxsize = sizeof(struct mv_cesa_hash_ctx),
1050 .cra_init = mv_cesa_ahash_cra_init,
1051 .cra_module = THIS_MODULE,
1056 struct mv_cesa_ahash_result {
1057 struct completion completion;
1061 static void mv_cesa_hmac_ahash_complete(struct crypto_async_request *req,
1064 struct mv_cesa_ahash_result *result = req->data;
1066 if (error == -EINPROGRESS)
1069 result->error = error;
1070 complete(&result->completion);
1073 static int mv_cesa_ahmac_iv_state_init(struct ahash_request *req, u8 *pad,
1074 void *state, unsigned int blocksize)
1076 struct mv_cesa_ahash_result result;
1077 struct scatterlist sg;
1080 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1081 mv_cesa_hmac_ahash_complete, &result);
1082 sg_init_one(&sg, pad, blocksize);
1083 ahash_request_set_crypt(req, &sg, pad, blocksize);
1084 init_completion(&result.completion);
1086 ret = crypto_ahash_init(req);
1090 ret = crypto_ahash_update(req);
1091 if (ret && ret != -EINPROGRESS)
1094 wait_for_completion_interruptible(&result.completion);
1096 return result.error;
1098 ret = crypto_ahash_export(req, state);
1105 static int mv_cesa_ahmac_pad_init(struct ahash_request *req,
1106 const u8 *key, unsigned int keylen,
1108 unsigned int blocksize)
1110 struct mv_cesa_ahash_result result;
1111 struct scatterlist sg;
1115 if (keylen <= blocksize) {
1116 memcpy(ipad, key, keylen);
1118 u8 *keydup = kmemdup(key, keylen, GFP_KERNEL);
1123 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
1124 mv_cesa_hmac_ahash_complete,
1126 sg_init_one(&sg, keydup, keylen);
1127 ahash_request_set_crypt(req, &sg, ipad, keylen);
1128 init_completion(&result.completion);
1130 ret = crypto_ahash_digest(req);
1131 if (ret == -EINPROGRESS) {
1132 wait_for_completion_interruptible(&result.completion);
1136 /* Set the memory region to 0 to avoid any leak. */
1137 memset(keydup, 0, keylen);
1143 keylen = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
1146 memset(ipad + keylen, 0, blocksize - keylen);
1147 memcpy(opad, ipad, blocksize);
1149 for (i = 0; i < blocksize; i++) {
1157 static int mv_cesa_ahmac_setkey(const char *hash_alg_name,
1158 const u8 *key, unsigned int keylen,
1159 void *istate, void *ostate)
1161 struct ahash_request *req;
1162 struct crypto_ahash *tfm;
1163 unsigned int blocksize;
1168 tfm = crypto_alloc_ahash(hash_alg_name, CRYPTO_ALG_TYPE_AHASH,
1169 CRYPTO_ALG_TYPE_AHASH_MASK);
1171 return PTR_ERR(tfm);
1173 req = ahash_request_alloc(tfm, GFP_KERNEL);
1179 crypto_ahash_clear_flags(tfm, ~0);
1181 blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1183 ipad = kzalloc(2 * blocksize, GFP_KERNEL);
1189 opad = ipad + blocksize;
1191 ret = mv_cesa_ahmac_pad_init(req, key, keylen, ipad, opad, blocksize);
1195 ret = mv_cesa_ahmac_iv_state_init(req, ipad, istate, blocksize);
1199 ret = mv_cesa_ahmac_iv_state_init(req, opad, ostate, blocksize);
1204 ahash_request_free(req);
1206 crypto_free_ahash(tfm);
1211 static int mv_cesa_ahmac_cra_init(struct crypto_tfm *tfm)
1213 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(tfm);
1215 ctx->base.ops = &mv_cesa_ahash_req_ops;
1217 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1218 sizeof(struct mv_cesa_ahash_req));
1222 static int mv_cesa_ahmac_md5_init(struct ahash_request *req)
1224 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1225 struct mv_cesa_op_ctx tmpl = { };
1227 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_MD5);
1228 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1230 mv_cesa_ahash_init(req, &tmpl, true);
1235 static int mv_cesa_ahmac_md5_setkey(struct crypto_ahash *tfm, const u8 *key,
1236 unsigned int keylen)
1238 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1239 struct md5_state istate, ostate;
1242 ret = mv_cesa_ahmac_setkey("mv-md5", key, keylen, &istate, &ostate);
1246 for (i = 0; i < ARRAY_SIZE(istate.hash); i++)
1247 ctx->iv[i] = be32_to_cpu(istate.hash[i]);
1249 for (i = 0; i < ARRAY_SIZE(ostate.hash); i++)
1250 ctx->iv[i + 8] = be32_to_cpu(ostate.hash[i]);
1255 static int mv_cesa_ahmac_md5_digest(struct ahash_request *req)
1259 ret = mv_cesa_ahmac_md5_init(req);
1263 return mv_cesa_ahash_finup(req);
1266 struct ahash_alg mv_ahmac_md5_alg = {
1267 .init = mv_cesa_ahmac_md5_init,
1268 .update = mv_cesa_ahash_update,
1269 .final = mv_cesa_ahash_final,
1270 .finup = mv_cesa_ahash_finup,
1271 .digest = mv_cesa_ahmac_md5_digest,
1272 .setkey = mv_cesa_ahmac_md5_setkey,
1273 .export = mv_cesa_md5_export,
1274 .import = mv_cesa_md5_import,
1276 .digestsize = MD5_DIGEST_SIZE,
1277 .statesize = sizeof(struct md5_state),
1279 .cra_name = "hmac(md5)",
1280 .cra_driver_name = "mv-hmac-md5",
1281 .cra_priority = 300,
1282 .cra_flags = CRYPTO_ALG_ASYNC |
1283 CRYPTO_ALG_KERN_DRIVER_ONLY,
1284 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1285 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1286 .cra_init = mv_cesa_ahmac_cra_init,
1287 .cra_module = THIS_MODULE,
1292 static int mv_cesa_ahmac_sha1_init(struct ahash_request *req)
1294 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1295 struct mv_cesa_op_ctx tmpl = { };
1297 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA1);
1298 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1300 mv_cesa_ahash_init(req, &tmpl, false);
1305 static int mv_cesa_ahmac_sha1_setkey(struct crypto_ahash *tfm, const u8 *key,
1306 unsigned int keylen)
1308 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1309 struct sha1_state istate, ostate;
1312 ret = mv_cesa_ahmac_setkey("mv-sha1", key, keylen, &istate, &ostate);
1316 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1317 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1319 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1320 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1325 static int mv_cesa_ahmac_sha1_digest(struct ahash_request *req)
1329 ret = mv_cesa_ahmac_sha1_init(req);
1333 return mv_cesa_ahash_finup(req);
1336 struct ahash_alg mv_ahmac_sha1_alg = {
1337 .init = mv_cesa_ahmac_sha1_init,
1338 .update = mv_cesa_ahash_update,
1339 .final = mv_cesa_ahash_final,
1340 .finup = mv_cesa_ahash_finup,
1341 .digest = mv_cesa_ahmac_sha1_digest,
1342 .setkey = mv_cesa_ahmac_sha1_setkey,
1343 .export = mv_cesa_sha1_export,
1344 .import = mv_cesa_sha1_import,
1346 .digestsize = SHA1_DIGEST_SIZE,
1347 .statesize = sizeof(struct sha1_state),
1349 .cra_name = "hmac(sha1)",
1350 .cra_driver_name = "mv-hmac-sha1",
1351 .cra_priority = 300,
1352 .cra_flags = CRYPTO_ALG_ASYNC |
1353 CRYPTO_ALG_KERN_DRIVER_ONLY,
1354 .cra_blocksize = SHA1_BLOCK_SIZE,
1355 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1356 .cra_init = mv_cesa_ahmac_cra_init,
1357 .cra_module = THIS_MODULE,
1362 static int mv_cesa_ahmac_sha256_setkey(struct crypto_ahash *tfm, const u8 *key,
1363 unsigned int keylen)
1365 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
1366 struct sha256_state istate, ostate;
1369 ret = mv_cesa_ahmac_setkey("mv-sha256", key, keylen, &istate, &ostate);
1373 for (i = 0; i < ARRAY_SIZE(istate.state); i++)
1374 ctx->iv[i] = be32_to_cpu(istate.state[i]);
1376 for (i = 0; i < ARRAY_SIZE(ostate.state); i++)
1377 ctx->iv[i + 8] = be32_to_cpu(ostate.state[i]);
1382 static int mv_cesa_ahmac_sha256_init(struct ahash_request *req)
1384 struct mv_cesa_hmac_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
1385 struct mv_cesa_op_ctx tmpl = { };
1387 mv_cesa_set_op_cfg(&tmpl, CESA_SA_DESC_CFG_MACM_HMAC_SHA256);
1388 memcpy(tmpl.ctx.hash.iv, ctx->iv, sizeof(ctx->iv));
1390 mv_cesa_ahash_init(req, &tmpl, false);
1395 static int mv_cesa_ahmac_sha256_digest(struct ahash_request *req)
1399 ret = mv_cesa_ahmac_sha256_init(req);
1403 return mv_cesa_ahash_finup(req);
1406 struct ahash_alg mv_ahmac_sha256_alg = {
1407 .init = mv_cesa_ahmac_sha256_init,
1408 .update = mv_cesa_ahash_update,
1409 .final = mv_cesa_ahash_final,
1410 .finup = mv_cesa_ahash_finup,
1411 .digest = mv_cesa_ahmac_sha256_digest,
1412 .setkey = mv_cesa_ahmac_sha256_setkey,
1413 .export = mv_cesa_sha256_export,
1414 .import = mv_cesa_sha256_import,
1416 .digestsize = SHA256_DIGEST_SIZE,
1417 .statesize = sizeof(struct sha256_state),
1419 .cra_name = "hmac(sha256)",
1420 .cra_driver_name = "mv-hmac-sha256",
1421 .cra_priority = 300,
1422 .cra_flags = CRYPTO_ALG_ASYNC |
1423 CRYPTO_ALG_KERN_DRIVER_ONLY,
1424 .cra_blocksize = SHA256_BLOCK_SIZE,
1425 .cra_ctxsize = sizeof(struct mv_cesa_hmac_ctx),
1426 .cra_init = mv_cesa_ahmac_cra_init,
1427 .cra_module = THIS_MODULE,