drivers/cpufreq/imx6q-cpufreq.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/cpufreq.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/opp.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regulator/consumer.h>
  18
  19 #define PU_SOC_VOLTAGE_NORMAL   1250000
  20 #define PU_SOC_VOLTAGE_HIGH     1275000
  21 #define FREQ_1P2_GHZ            1200000000
  22
  23 static struct regulator *arm_reg;
  24 static struct regulator *pu_reg;
  25 static struct regulator *soc_reg;
  26
  27 static struct clk *arm_clk;
  28 static struct clk *pll1_sys_clk;
  29 static struct clk *pll1_sw_clk;
  30 static struct clk *step_clk;
  31 static struct clk *pll2_pfd2_396m_clk;
  32
  33 static struct device *cpu_dev;
  34 static struct cpufreq_frequency_table *freq_table;
  35 static unsigned int transition_latency;
  36
  37 static int imx6q_verify_speed(struct cpufreq_policy *policy)
  38 {
  39         return cpufreq_frequency_table_verify(policy, freq_table);
  40 }
  41
  42 static unsigned int imx6q_get_speed(unsigned int cpu)
  43 {
  44         return clk_get_rate(arm_clk) / 1000;
  45 }
  46
  47 static int imx6q_set_target(struct cpufreq_policy *policy,
  48                             unsigned int target_freq, unsigned int relation)
  49 {
  50         struct cpufreq_freqs freqs;
  51         struct opp *opp;
  52         unsigned long freq_hz, volt, volt_old;
  53         unsigned int index;
  54         int ret;
  55
  56         ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  57                                              relation, &index);
  58         if (ret) {
  59                 dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
  60                         target_freq, ret);
  61                 return ret;
  62         }
  63
  64         freqs.new = freq_table[index].frequency;
  65         freq_hz = freqs.new * 1000;
  66         freqs.old = clk_get_rate(arm_clk) / 1000;
  67
  68         if (freqs.old == freqs.new)
  69                 return 0;
  70
  71         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  72
  73         rcu_read_lock();
  74         opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
  75         if (IS_ERR(opp)) {
  76                 rcu_read_unlock();
  77                 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
  78                 return PTR_ERR(opp);
  79         }
  80
  81         volt = opp_get_voltage(opp);
  82         rcu_read_unlock();
  83         volt_old = regulator_get_voltage(arm_reg);
  84
  85         dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
  86                 freqs.old / 1000, volt_old / 1000,
  87                 freqs.new / 1000, volt / 1000);
  88
  89         /* scaling up?  scale voltage before frequency */
  90         if (freqs.new > freqs.old) {
  91                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
  92                 if (ret) {
  93                         dev_err(cpu_dev,
  94                                 "failed to scale vddarm up: %d\n", ret);
  95                         return ret;
  96                 }
  97
  98                 /*
  99                  * Need to increase vddpu and vddsoc for safety
 100                  * if we are about to run at 1.2 GHz.
 101                  */
 102                 if (freqs.new == FREQ_1P2_GHZ / 1000) {
 103                         regulator_set_voltage_tol(pu_reg,
 104                                         PU_SOC_VOLTAGE_HIGH, 0);
 105                         regulator_set_voltage_tol(soc_reg,
 106                                         PU_SOC_VOLTAGE_HIGH, 0);
 107                 }
 108         }
 109
 110         /*
 111          * The setpoints are selected per PLL/PDF frequencies, so we need to
 112          * reprogram PLL for frequency scaling.  The procedure of reprogramming
 113          * PLL1 is as below.
 114          *
 115          *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
 116          *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
 117          *  - Disable pll2_pfd2_396m_clk
 118          */
 119         clk_prepare_enable(pll2_pfd2_396m_clk);
 120         clk_set_parent(step_clk, pll2_pfd2_396m_clk);
 121         clk_set_parent(pll1_sw_clk, step_clk);
 122         if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
 123                 clk_set_rate(pll1_sys_clk, freqs.new * 1000);
 124                 /*
 125                  * If we are leaving 396 MHz set-point, we need to enable
 126                  * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
 127                  * their use count correct.
 128                  */
 129                 if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
 130                         clk_prepare_enable(pll1_sys_clk);
 131                         clk_disable_unprepare(pll2_pfd2_396m_clk);
 132                 }
 133                 clk_set_parent(pll1_sw_clk, pll1_sys_clk);
 134                 clk_disable_unprepare(pll2_pfd2_396m_clk);
 135         } else {
 136                 /*
 137                  * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
 138                  * to provide the frequency.
 139                  */
 140                 clk_disable_unprepare(pll1_sys_clk);
 141         }
 142
 143         /* Ensure the arm clock divider is what we expect */
 144         ret = clk_set_rate(arm_clk, freqs.new * 1000);
 145         if (ret) {
 146                 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
 147                 regulator_set_voltage_tol(arm_reg, volt_old, 0);
 148                 return ret;
 149         }
 150
 151         /* scaling down?  scale voltage after frequency */
 152         if (freqs.new < freqs.old) {
 153                 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
 154                 if (ret)
 155                         dev_warn(cpu_dev,
 156                                  "failed to scale vddarm down: %d\n", ret);
 157
 158                 if (freqs.old == FREQ_1P2_GHZ / 1000) {
 159                         regulator_set_voltage_tol(pu_reg,
 160                                         PU_SOC_VOLTAGE_NORMAL, 0);
 161                         regulator_set_voltage_tol(soc_reg,
 162                                         PU_SOC_VOLTAGE_NORMAL, 0);
 163                 }
 164         }
 165
 166         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 167
 168         return 0;
 169 }
 170
 171 static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
 172 {
 173         int ret;
 174
 175         ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
 176         if (ret) {
 177                 dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
 178                 return ret;
 179         }
 180
 181         policy->cpuinfo.transition_latency = transition_latency;
 182         policy->cur = clk_get_rate(arm_clk) / 1000;
 183         cpumask_setall(policy->cpus);
 184         cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
 185
 186         return 0;
 187 }
 188
 189 static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
 190 {
 191         cpufreq_frequency_table_put_attr(policy->cpu);
 192         return 0;
 193 }
 194
 195 static struct freq_attr *imx6q_cpufreq_attr[] = {
 196         &cpufreq_freq_attr_scaling_available_freqs,
 197         NULL,
 198 };
 199
 200 static struct cpufreq_driver imx6q_cpufreq_driver = {
 201         .verify = imx6q_verify_speed,
 202         .target = imx6q_set_target,
 203         .get = imx6q_get_speed,
 204         .init = imx6q_cpufreq_init,
 205         .exit = imx6q_cpufreq_exit,
 206         .name = "imx6q-cpufreq",
 207         .attr = imx6q_cpufreq_attr,
 208 };
 209
 210 static int imx6q_cpufreq_probe(struct platform_device *pdev)
 211 {
 212         struct device_node *np;
 213         struct opp *opp;
 214         unsigned long min_volt, max_volt;
 215         int num, ret;
 216
 217         cpu_dev = &pdev->dev;
 218
 219         np = of_find_node_by_path("/cpus/cpu@0");
 220         if (!np) {
 221                 dev_err(cpu_dev, "failed to find cpu0 node\n");
 222                 return -ENOENT;
 223         }
 224
 225         cpu_dev->of_node = np;
 226
 227         arm_clk = devm_clk_get(cpu_dev, "arm");
 228         pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
 229         pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
 230         step_clk = devm_clk_get(cpu_dev, "step");
 231         pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
 232         if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
 233             IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
 234                 dev_err(cpu_dev, "failed to get clocks\n");
 235                 ret = -ENOENT;
 236                 goto put_node;
 237         }
 238
 239         arm_reg = devm_regulator_get(cpu_dev, "arm");
 240         pu_reg = devm_regulator_get(cpu_dev, "pu");
 241         soc_reg = devm_regulator_get(cpu_dev, "soc");
 242         if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
 243                 dev_err(cpu_dev, "failed to get regulators\n");
 244                 ret = -ENOENT;
 245                 goto put_node;
 246         }
 247
 248         /* We expect an OPP table supplied by platform */
 249         num = opp_get_opp_count(cpu_dev);
 250         if (num < 0) {
 251                 ret = num;
 252                 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
 253                 goto put_node;
 254         }
 255
 256         ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
 257         if (ret) {
 258                 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
 259                 goto put_node;
 260         }
 261
 262         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 263                 transition_latency = CPUFREQ_ETERNAL;
 264
 265         /*
 266          * OPP is maintained in order of increasing frequency, and
 267          * freq_table initialised from OPP is therefore sorted in the
 268          * same order.
 269          */
 270         rcu_read_lock();
 271         opp = opp_find_freq_exact(cpu_dev,
 272                                   freq_table[0].frequency * 1000, true);
 273         min_volt = opp_get_voltage(opp);
 274         opp = opp_find_freq_exact(cpu_dev,
 275                                   freq_table[--num].frequency * 1000, true);
 276         max_volt = opp_get_voltage(opp);
 277         rcu_read_unlock();
 278         ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
 279         if (ret > 0)
 280                 transition_latency += ret * 1000;
 281
 282         /* Count vddpu and vddsoc latency in for 1.2 GHz support */
 283         if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
 284                 ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
 285                                                  PU_SOC_VOLTAGE_HIGH);
 286                 if (ret > 0)
 287                         transition_latency += ret * 1000;
 288                 ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
 289                                                  PU_SOC_VOLTAGE_HIGH);
 290                 if (ret > 0)
 291                         transition_latency += ret * 1000;
 292         }
 293
 294         ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
 295         if (ret) {
 296                 dev_err(cpu_dev, "failed register driver: %d\n", ret);
 297                 goto free_freq_table;
 298         }
 299
 300         of_node_put(np);
 301         return 0;
 302
 303 free_freq_table:
 304         opp_free_cpufreq_table(cpu_dev, &freq_table);
 305 put_node:
 306         of_node_put(np);
 307         return ret;
 308 }
 309
 310 static int imx6q_cpufreq_remove(struct platform_device *pdev)
 311 {
 312         cpufreq_unregister_driver(&imx6q_cpufreq_driver);
 313         opp_free_cpufreq_table(cpu_dev, &freq_table);
 314
 315         return 0;
 316 }
 317
 318 static struct platform_driver imx6q_cpufreq_platdrv = {
 319         .driver = {
 320                 .name   = "imx6q-cpufreq",
 321                 .owner  = THIS_MODULE,
 322         },
 323         .probe          = imx6q_cpufreq_probe,
 324         .remove         = imx6q_cpufreq_remove,
 325 };
 326 module_platform_driver(imx6q_cpufreq_platdrv);
 327
 328 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 329 MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
 330 MODULE_LICENSE("GPL");