drivers/clocksource/arm_arch_timer.c

   1 /*
   2  *  linux/drivers/clocksource/arm_arch_timer.c
   3  *
   4  *  Copyright (C) 2011 ARM Ltd.
   5  *  All Rights Reserved
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/device.h>
  14 #include <linux/smp.h>
  15 #include <linux/cpu.h>
  16 #include <linux/clockchips.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/arch_timer.h>
  22 #include <asm/virt.h>
  23
  24 #include <clocksource/arm_arch_timer.h>
  25
  26 static u32 arch_timer_rate;
  27
  28 enum ppi_nr {
  29         PHYS_SECURE_PPI,
  30         PHYS_NONSECURE_PPI,
  31         VIRT_PPI,
  32         HYP_PPI,
  33         MAX_TIMER_PPI
  34 };
  35
  36 static int arch_timer_ppi[MAX_TIMER_PPI];
  37
  38 static struct clock_event_device __percpu *arch_timer_evt;
  39
  40 static bool arch_timer_use_virtual = true;
  41
  42 /*
  43  * Architected system timer support.
  44  */
  45
  46 static inline irqreturn_t timer_handler(const int access,
  47                                         struct clock_event_device *evt)
  48 {
  49         unsigned long ctrl;
  50         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
  51         if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
  52                 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
  53                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
  54                 evt->event_handler(evt);
  55                 return IRQ_HANDLED;
  56         }
  57
  58         return IRQ_NONE;
  59 }
  60
  61 static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
  62 {
  63         struct clock_event_device *evt = dev_id;
  64
  65         return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
  66 }
  67
  68 static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
  69 {
  70         struct clock_event_device *evt = dev_id;
  71
  72         return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
  73 }
  74
  75 static inline void timer_set_mode(const int access, int mode)
  76 {
  77         unsigned long ctrl;
  78         switch (mode) {
  79         case CLOCK_EVT_MODE_UNUSED:
  80         case CLOCK_EVT_MODE_SHUTDOWN:
  81                 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
  82                 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  83                 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
  84                 break;
  85         default:
  86                 break;
  87         }
  88 }
  89
  90 static void arch_timer_set_mode_virt(enum clock_event_mode mode,
  91                                      struct clock_event_device *clk)
  92 {
  93         timer_set_mode(ARCH_TIMER_VIRT_ACCESS, mode);
  94 }
  95
  96 static void arch_timer_set_mode_phys(enum clock_event_mode mode,
  97                                      struct clock_event_device *clk)
  98 {
  99         timer_set_mode(ARCH_TIMER_PHYS_ACCESS, mode);
 100 }
 101
 102 static inline void set_next_event(const int access, unsigned long evt)
 103 {
 104         unsigned long ctrl;
 105         ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL);
 106         ctrl |= ARCH_TIMER_CTRL_ENABLE;
 107         ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
 108         arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt);
 109         arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl);
 110 }
 111
 112 static int arch_timer_set_next_event_virt(unsigned long evt,
 113                                           struct clock_event_device *unused)
 114 {
 115         set_next_event(ARCH_TIMER_VIRT_ACCESS, evt);
 116         return 0;
 117 }
 118
 119 static int arch_timer_set_next_event_phys(unsigned long evt,
 120                                           struct clock_event_device *unused)
 121 {
 122         set_next_event(ARCH_TIMER_PHYS_ACCESS, evt);
 123         return 0;
 124 }
 125
 126 static void arch_timer_configure_evtstream(void)
 127 {
 128         int evt_stream_div, pos;
 129
 130         /* Find the closest power of two to the divisor */
 131         evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
 132         pos = fls(evt_stream_div);
 133         if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
 134                 pos--;
 135         /* enable event stream */
 136         arch_timer_evtstrm_enable(min(pos, 15));
 137 }
 138
 139 static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
 140 {
 141         clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
 142         clk->name = "arch_sys_timer";
 143         clk->rating = 450;
 144         if (arch_timer_use_virtual) {
 145                 clk->irq = arch_timer_ppi[VIRT_PPI];
 146                 clk->set_mode = arch_timer_set_mode_virt;
 147                 clk->set_next_event = arch_timer_set_next_event_virt;
 148         } else {
 149                 clk->irq = arch_timer_ppi[PHYS_SECURE_PPI];
 150                 clk->set_mode = arch_timer_set_mode_phys;
 151                 clk->set_next_event = arch_timer_set_next_event_phys;
 152         }
 153
 154         clk->cpumask = cpumask_of(smp_processor_id());
 155
 156         clk->set_mode(CLOCK_EVT_MODE_SHUTDOWN, NULL);
 157
 158         clockevents_config_and_register(clk, arch_timer_rate,
 159                                         0xf, 0x7fffffff);
 160
 161         if (arch_timer_use_virtual)
 162                 enable_percpu_irq(arch_timer_ppi[VIRT_PPI], 0);
 163         else {
 164                 enable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI], 0);
 165                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 166                         enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], 0);
 167         }
 168
 169         arch_counter_set_user_access();
 170         if (IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM))
 171                 arch_timer_configure_evtstream();
 172
 173         return 0;
 174 }
 175
 176 static int arch_timer_available(void)
 177 {
 178         u32 freq;
 179
 180         if (arch_timer_rate == 0) {
 181                 freq = arch_timer_get_cntfrq();
 182
 183                 /* Check the timer frequency. */
 184                 if (freq == 0) {
 185                         pr_warn("Architected timer frequency not available\n");
 186                         return -EINVAL;
 187                 }
 188
 189                 arch_timer_rate = freq;
 190         }
 191
 192         pr_info_once("Architected local timer running at %lu.%02luMHz (%s).\n",
 193                      (unsigned long)arch_timer_rate / 1000000,
 194                      (unsigned long)(arch_timer_rate / 10000) % 100,
 195                      arch_timer_use_virtual ? "virt" : "phys");
 196         return 0;
 197 }
 198
 199 u32 arch_timer_get_rate(void)
 200 {
 201         return arch_timer_rate;
 202 }
 203
 204 u64 arch_timer_read_counter(void)
 205 {
 206         return arch_counter_get_cntvct();
 207 }
 208
 209 static cycle_t arch_counter_read(struct clocksource *cs)
 210 {
 211         return arch_counter_get_cntvct();
 212 }
 213
 214 static cycle_t arch_counter_read_cc(const struct cyclecounter *cc)
 215 {
 216         return arch_counter_get_cntvct();
 217 }
 218
 219 static struct clocksource clocksource_counter = {
 220         .name   = "arch_sys_counter",
 221         .rating = 400,
 222         .read   = arch_counter_read,
 223         .mask   = CLOCKSOURCE_MASK(56),
 224         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 225 };
 226
 227 static struct cyclecounter cyclecounter = {
 228         .read   = arch_counter_read_cc,
 229         .mask   = CLOCKSOURCE_MASK(56),
 230 };
 231
 232 static struct timecounter timecounter;
 233
 234 struct timecounter *arch_timer_get_timecounter(void)
 235 {
 236         return &timecounter;
 237 }
 238
 239 static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
 240 {
 241         pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
 242                  clk->irq, smp_processor_id());
 243
 244         if (arch_timer_use_virtual)
 245                 disable_percpu_irq(arch_timer_ppi[VIRT_PPI]);
 246         else {
 247                 disable_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI]);
 248                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 249                         disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
 250         }
 251
 252         clk->set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 253 }
 254
 255 static int __cpuinit arch_timer_cpu_notify(struct notifier_block *self,
 256                                            unsigned long action, void *hcpu)
 257 {
 258         /*
 259          * Grab cpu pointer in each case to avoid spurious
 260          * preemptible warnings
 261          */
 262         switch (action & ~CPU_TASKS_FROZEN) {
 263         case CPU_STARTING:
 264                 arch_timer_setup(this_cpu_ptr(arch_timer_evt));
 265                 break;
 266         case CPU_DYING:
 267                 arch_timer_stop(this_cpu_ptr(arch_timer_evt));
 268                 break;
 269         }
 270
 271         return NOTIFY_OK;
 272 }
 273
 274 static struct notifier_block arch_timer_cpu_nb __cpuinitdata = {
 275         .notifier_call = arch_timer_cpu_notify,
 276 };
 277
 278 static int __init arch_timer_register(void)
 279 {
 280         int err;
 281         int ppi;
 282
 283         err = arch_timer_available();
 284         if (err)
 285                 goto out;
 286
 287         arch_timer_evt = alloc_percpu(struct clock_event_device);
 288         if (!arch_timer_evt) {
 289                 err = -ENOMEM;
 290                 goto out;
 291         }
 292
 293         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 294         cyclecounter.mult = clocksource_counter.mult;
 295         cyclecounter.shift = clocksource_counter.shift;
 296         timecounter_init(&timecounter, &cyclecounter,
 297                          arch_counter_get_cntvct());
 298
 299         if (arch_timer_use_virtual) {
 300                 ppi = arch_timer_ppi[VIRT_PPI];
 301                 err = request_percpu_irq(ppi, arch_timer_handler_virt,
 302                                          "arch_timer", arch_timer_evt);
 303         } else {
 304                 ppi = arch_timer_ppi[PHYS_SECURE_PPI];
 305                 err = request_percpu_irq(ppi, arch_timer_handler_phys,
 306                                          "arch_timer", arch_timer_evt);
 307                 if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 308                         ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
 309                         err = request_percpu_irq(ppi, arch_timer_handler_phys,
 310                                                  "arch_timer", arch_timer_evt);
 311                         if (err)
 312                                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 313                                                 arch_timer_evt);
 314                 }
 315         }
 316
 317         if (err) {
 318                 pr_err("arch_timer: can't register interrupt %d (%d)\n",
 319                        ppi, err);
 320                 goto out_free;
 321         }
 322
 323         err = register_cpu_notifier(&arch_timer_cpu_nb);
 324         if (err)
 325                 goto out_free_irq;
 326
 327         /* Immediately configure the timer on the boot CPU */
 328         arch_timer_setup(this_cpu_ptr(arch_timer_evt));
 329
 330         return 0;
 331
 332 out_free_irq:
 333         if (arch_timer_use_virtual)
 334                 free_percpu_irq(arch_timer_ppi[VIRT_PPI], arch_timer_evt);
 335         else {
 336                 free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
 337                                 arch_timer_evt);
 338                 if (arch_timer_ppi[PHYS_NONSECURE_PPI])
 339                         free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
 340                                         arch_timer_evt);
 341         }
 342
 343 out_free:
 344         free_percpu(arch_timer_evt);
 345 out:
 346         return err;
 347 }
 348
 349 static void __init arch_timer_init(struct device_node *np)
 350 {
 351         u32 freq;
 352         int i;
 353
 354         if (arch_timer_get_rate()) {
 355                 pr_warn("arch_timer: multiple nodes in dt, skipping\n");
 356                 return;
 357         }
 358
 359         /* Try to determine the frequency from the device tree or CNTFRQ */
 360         if (!of_property_read_u32(np, "clock-frequency", &freq))
 361                 arch_timer_rate = freq;
 362
 363         for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
 364                 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
 365
 366         of_node_put(np);
 367
 368         /*
 369          * If HYP mode is available, we know that the physical timer
 370          * has been configured to be accessible from PL1. Use it, so
 371          * that a guest can use the virtual timer instead.
 372          *
 373          * If no interrupt provided for virtual timer, we'll have to
 374          * stick to the physical timer. It'd better be accessible...
 375          */
 376         if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
 377                 arch_timer_use_virtual = false;
 378
 379                 if (!arch_timer_ppi[PHYS_SECURE_PPI] ||
 380                     !arch_timer_ppi[PHYS_NONSECURE_PPI]) {
 381                         pr_warn("arch_timer: No interrupt available, giving up\n");
 382                         return;
 383                 }
 384         }
 385
 386         arch_timer_register();
 387         arch_timer_arch_init();
 388 }
 389 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
 390 CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);