drivers/clk/ti/clock.h

   1 /*
   2  * TI Clock driver internal definitions
   3  *
   4  * Copyright (C) 2014 Texas Instruments, Inc
   5  *     Tero Kristo (t-kristo@ti.com)
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16 #ifndef __DRIVERS_CLK_TI_CLOCK__
  17 #define __DRIVERS_CLK_TI_CLOCK__
  18
  19 enum {
  20         TI_CLK_FIXED,
  21         TI_CLK_MUX,
  22         TI_CLK_DIVIDER,
  23         TI_CLK_COMPOSITE,
  24         TI_CLK_FIXED_FACTOR,
  25         TI_CLK_GATE,
  26         TI_CLK_DPLL,
  27 };
  28
  29 /* Global flags */
  30 #define CLKF_INDEX_POWER_OF_TWO         (1 << 0)
  31 #define CLKF_INDEX_STARTS_AT_ONE        (1 << 1)
  32 #define CLKF_SET_RATE_PARENT            (1 << 2)
  33 #define CLKF_OMAP3                      (1 << 3)
  34 #define CLKF_AM35XX                     (1 << 4)
  35
  36 /* Gate flags */
  37 #define CLKF_SET_BIT_TO_DISABLE         (1 << 5)
  38 #define CLKF_INTERFACE                  (1 << 6)
  39 #define CLKF_SSI                        (1 << 7)
  40 #define CLKF_DSS                        (1 << 8)
  41 #define CLKF_HSOTGUSB                   (1 << 9)
  42 #define CLKF_WAIT                       (1 << 10)
  43 #define CLKF_NO_WAIT                    (1 << 11)
  44 #define CLKF_HSDIV                      (1 << 12)
  45 #define CLKF_CLKDM                      (1 << 13)
  46
  47 /* DPLL flags */
  48 #define CLKF_LOW_POWER_STOP             (1 << 5)
  49 #define CLKF_LOCK                       (1 << 6)
  50 #define CLKF_LOW_POWER_BYPASS           (1 << 7)
  51 #define CLKF_PER                        (1 << 8)
  52 #define CLKF_CORE                       (1 << 9)
  53 #define CLKF_J_TYPE                     (1 << 10)
  54
  55 #define CLK(dev, con, ck)               \
  56         {                               \
  57                 .lk = {                 \
  58                         .dev_id = dev,  \
  59                         .con_id = con,  \
  60                 },                      \
  61                 .clk = ck,              \
  62         }
  63
  64 struct ti_clk {
  65         const char *name;
  66         const char *clkdm_name;
  67         int type;
  68         void *data;
  69         struct ti_clk *patch;
  70         struct clk *clk;
  71 };
  72
  73 struct ti_clk_alias {
  74         struct ti_clk *clk;
  75         struct clk_lookup lk;
  76         struct list_head link;
  77 };
  78
  79 struct ti_clk_fixed {
  80         u32 frequency;
  81         u16 flags;
  82 };
  83
  84 struct ti_clk_mux {
  85         u8 bit_shift;
  86         int num_parents;
  87         u16 reg;
  88         u8 module;
  89         const char **parents;
  90         u16 flags;
  91 };
  92
  93 struct ti_clk_divider {
  94         const char *parent;
  95         u8 bit_shift;
  96         u16 max_div;
  97         u16 reg;
  98         u8 module;
  99         int *dividers;
 100         int num_dividers;
 101         u16 flags;
 102 };
 103
 104 struct ti_clk_fixed_factor {
 105         const char *parent;
 106         u16 div;
 107         u16 mult;
 108         u16 flags;
 109 };
 110
 111 struct ti_clk_gate {
 112         const char *parent;
 113         u8 bit_shift;
 114         u16 reg;
 115         u8 module;
 116         u16 flags;
 117 };
 118
 119 struct ti_clk_composite {
 120         struct ti_clk_divider *divider;
 121         struct ti_clk_mux *mux;
 122         struct ti_clk_gate *gate;
 123         u16 flags;
 124 };
 125
 126 struct ti_clk_clkdm_gate {
 127         const char *parent;
 128         u16 flags;
 129 };
 130
 131 struct ti_clk_dpll {
 132         int num_parents;
 133         u16 control_reg;
 134         u16 idlest_reg;
 135         u16 autoidle_reg;
 136         u16 mult_div1_reg;
 137         u8 module;
 138         const char **parents;
 139         u16 flags;
 140         u8 modes;
 141         u32 mult_mask;
 142         u32 div1_mask;
 143         u32 enable_mask;
 144         u32 autoidle_mask;
 145         u32 freqsel_mask;
 146         u32 idlest_mask;
 147         u32 dco_mask;
 148         u32 sddiv_mask;
 149         u16 max_multiplier;
 150         u16 max_divider;
 151         u8 min_divider;
 152         u8 auto_recal_bit;
 153         u8 recal_en_bit;
 154         u8 recal_st_bit;
 155 };
 156
 157 struct clk *ti_clk_register_gate(struct ti_clk *setup);
 158 struct clk *ti_clk_register_interface(struct ti_clk *setup);
 159 struct clk *ti_clk_register_mux(struct ti_clk *setup);
 160 struct clk *ti_clk_register_divider(struct ti_clk *setup);
 161 struct clk *ti_clk_register_composite(struct ti_clk *setup);
 162 struct clk *ti_clk_register_dpll(struct ti_clk *setup);
 163
 164 struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
 165 struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
 166 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
 167
 168 void ti_clk_patch_legacy_clks(struct ti_clk **patch);
 169 struct clk *ti_clk_register_clk(struct ti_clk *setup);
 170 int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
 171
 172 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 173 int of_ti_clk_autoidle_setup(struct device_node *node);
 174 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 175
 176 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 177 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
 178 extern const struct clk_hw_omap_ops clkhwops_iclk;
 179 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 180
 181 u8 omap2_init_dpll_parent(struct clk_hw *hw);
 182 int omap3_noncore_dpll_enable(struct clk_hw *hw);
 183 void omap3_noncore_dpll_disable(struct clk_hw *hw);
 184 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
 185 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
 186                                 unsigned long parent_rate);
 187 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
 188                                            unsigned long rate,
 189                                            unsigned long parent_rate,
 190                                            u8 index);
 191 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
 192                                        unsigned long rate,
 193                                        unsigned long min_rate,
 194                                        unsigned long max_rate,
 195                                        unsigned long *best_parent_rate,
 196                                        struct clk_hw **best_parent_clk);
 197 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 198                            unsigned long *parent_rate);
 199 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 200                                     unsigned long parent_rate);
 201
 202 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
 203 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
 204                          unsigned long parent_rate);
 205 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
 206                                     unsigned long parent_rate, u8 index);
 207 void omap3_clk_lock_dpll5(void);
 208
 209 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
 210                                          unsigned long parent_rate);
 211 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
 212                                     unsigned long target_rate,
 213                                     unsigned long *parent_rate);
 214 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
 215                                         unsigned long rate,
 216                                         unsigned long min_rate,
 217                                         unsigned long max_rate,
 218                                         unsigned long *best_parent_rate,
 219                                         struct clk_hw **best_parent_clk);
 220
 221 #endif