2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/clk-provider.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/clk/tegra.h>
28 #define PLLX_BASE 0xe0
29 #define PLLX_MISC 0xe4
30 #define PLLX_MISC2 0x514
31 #define PLLX_MISC3 0x518
33 #define CCLKG_BURST_POLICY 0x368
34 #define CCLKLP_BURST_POLICY 0x370
35 #define SCLK_BURST_POLICY 0x028
36 #define SYSTEM_CLK_RATE 0x030
38 static DEFINE_SPINLOCK(sysrate_lock);
40 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
41 "pll_p", "pll_p_out2", "unused",
42 "clk_32k", "pll_m_out1" };
44 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
45 "pll_p", "pll_p_out4", "unused",
48 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
49 "pll_p", "pll_p_out4", "unused",
50 "unused", "pll_x", "pll_x_out0" };
52 static void __init tegra_sclk_init(void __iomem *clk_base,
53 struct tegra_clk *tegra_clks)
59 dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
61 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
62 ARRAY_SIZE(sclk_parents),
64 clk_base + SCLK_BURST_POLICY,
70 dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
72 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
73 clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
75 clk = clk_register_gate(NULL, "hclk", "hclk_div",
76 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
77 clk_base + SYSTEM_CLK_RATE,
78 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
83 dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
87 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
88 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
90 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
91 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
92 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
96 void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
97 void __iomem *pmc_base,
98 struct tegra_clk *tegra_clks,
99 struct tegra_clk_pll_params *params)
105 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
107 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
108 ARRAY_SIZE(cclk_g_parents),
110 clk_base + CCLKG_BURST_POLICY,
116 dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
118 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
119 ARRAY_SIZE(cclk_lp_parents),
121 clk_base + CCLKLP_BURST_POLICY,
122 TEGRA_DIVIDER_2, 4, 8, 9, NULL);
126 tegra_sclk_init(clk_base, tegra_clks);
128 #if defined(CONFIG_ARCH_TEGRA_114_SOC) || defined(CONFIG_ARCH_TEGRA_124_SOC)
130 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
134 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
135 pmc_base, CLK_IGNORE_UNUSED, params, NULL);
140 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
143 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
144 CLK_SET_RATE_PARENT, 1, 2);