2 * This header provides IDs for clocks common between several Tegra SoCs
4 #ifndef _TEGRA_CLK_ID_H
5 #define _TEGRA_CLK_ID_H
45 tegra_clk_clk_out_1_mux,
47 tegra_clk_clk_out_2_mux,
49 tegra_clk_clk_out_3_mux,
88 tegra_clk_hda2codec_2x,
131 tegra_clk_pll_a_out0,
136 tegra_clk_pll_c_out1,
139 tegra_clk_pll_d2_out0,
140 tegra_clk_pll_d_out0,
142 tegra_clk_pll_e_out0,
144 tegra_clk_pll_m_out1,
146 tegra_clk_pll_p_out1,
147 tegra_clk_pll_p_out2,
148 tegra_clk_pll_p_out2_int,
149 tegra_clk_pll_p_out3,
150 tegra_clk_pll_p_out4,
151 tegra_clk_pll_p_out5,
153 tegra_clk_pll_re_out,
154 tegra_clk_pll_re_vco,
157 tegra_clk_pll_u_480m,
161 tegra_clk_pll_x_out0,
195 tegra_clk_spdif_in_sync,
221 tegra_clk_vimclk_sync,
223 tegra_clk_vi_sensor2,
224 tegra_clk_vi_sensor_8,
226 tegra_clk_xusb_dev_src,
227 tegra_clk_xusb_falcon_src,
228 tegra_clk_xusb_fs_src,
230 tegra_clk_xusb_host_src,
231 tegra_clk_xusb_hs_src,
233 tegra_clk_xusb_ss_src,
234 tegra_clk_xusb_ss_div2,
238 #endif /* _TEGRA_CLK_ID_H */