2 * Copyright 2013 Emilio López
3 * Emilio López <emilio@elopez.com.ar>
5 * Copyright 2015 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/clk-provider.h>
21 #include <linux/of_address.h>
22 #include <linux/slab.h>
24 #include <dt-bindings/clock/sun4i-a10-pll2.h>
26 #define SUN4I_PLL2_ENABLE 31
28 #define SUN4I_PLL2_PRE_DIV_SHIFT 0
29 #define SUN4I_PLL2_PRE_DIV_WIDTH 5
30 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
32 #define SUN4I_PLL2_N_SHIFT 8
33 #define SUN4I_PLL2_N_WIDTH 7
34 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
36 #define SUN4I_PLL2_POST_DIV_SHIFT 26
37 #define SUN4I_PLL2_POST_DIV_WIDTH 4
38 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
40 #define SUN4I_PLL2_POST_DIV_VALUE 4
42 #define SUN4I_PLL2_OUTPUTS 4
44 struct sun4i_pll2_data {
49 static DEFINE_SPINLOCK(sun4i_a10_pll2_lock);
51 static void __init sun4i_pll2_setup(struct device_node *node,
52 struct sun4i_pll2_data *data)
54 const char *clk_name = node->name, *parent;
55 struct clk **clks, *base_clk, *prediv_clk;
56 struct clk_onecell_data *clk_data;
57 struct clk_multiplier *mult;
58 struct clk_gate *gate;
62 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
66 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
70 clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
74 parent = of_clk_get_parent_name(node, 0);
75 prediv_clk = clk_register_divider(NULL, "pll2-prediv",
77 SUN4I_PLL2_PRE_DIV_SHIFT,
78 SUN4I_PLL2_PRE_DIV_WIDTH,
80 &sun4i_a10_pll2_lock);
82 pr_err("Couldn't register the prediv clock\n");
86 /* Setup the gate part of the PLL2 */
87 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
89 goto err_unregister_prediv;
92 gate->bit_idx = SUN4I_PLL2_ENABLE;
93 gate->lock = &sun4i_a10_pll2_lock;
95 /* Setup the multiplier part of the PLL2 */
96 mult = kzalloc(sizeof(struct clk_multiplier), GFP_KERNEL);
101 mult->shift = SUN4I_PLL2_N_SHIFT;
103 mult->flags = CLK_MULTIPLIER_ZERO_BYPASS |
104 CLK_MULTIPLIER_ROUND_CLOSEST;
105 mult->lock = &sun4i_a10_pll2_lock;
107 parent = __clk_get_name(prediv_clk);
108 base_clk = clk_register_composite(NULL, "pll2-base",
111 &mult->hw, &clk_multiplier_ops,
112 &gate->hw, &clk_gate_ops,
113 CLK_SET_RATE_PARENT);
115 pr_err("Couldn't register the base multiplier clock\n");
116 goto err_free_multiplier;
119 parent = __clk_get_name(base_clk);
124 * This is supposed to have a post divider, but we won't need
125 * to use it, we just need to initialise it to 4, and use a
129 val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV_SHIFT);
130 val |= (SUN4I_PLL2_POST_DIV_VALUE - data->post_div_offset) << SUN4I_PLL2_POST_DIV_SHIFT;
133 of_property_read_string_index(node, "clock-output-names",
134 SUN4I_A10_PLL2_1X, &clk_name);
135 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name,
139 SUN4I_PLL2_POST_DIV_VALUE);
140 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_1X]));
145 * This clock doesn't use the post divider, and really is just
146 * a fixed divider from the PLL2 base clock.
148 of_property_read_string_index(node, "clock-output-names",
149 SUN4I_A10_PLL2_2X, &clk_name);
150 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name,
154 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_2X]));
157 of_property_read_string_index(node, "clock-output-names",
158 SUN4I_A10_PLL2_4X, &clk_name);
159 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name,
163 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_4X]));
166 of_property_read_string_index(node, "clock-output-names",
167 SUN4I_A10_PLL2_8X, &clk_name);
168 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name,
172 WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
174 clk_data->clks = clks;
175 clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
176 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
184 err_unregister_prediv:
185 clk_unregister_divider(prediv_clk);
194 static struct sun4i_pll2_data sun4i_a10_pll2_data = {
195 .pre_div_flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
198 static void __init sun4i_a10_pll2_setup(struct device_node *node)
200 sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
203 CLK_OF_DECLARE(sun4i_a10_pll2, "allwinner,sun4i-a10-pll2-clk",
204 sun4i_a10_pll2_setup);
206 static struct sun4i_pll2_data sun5i_a13_pll2_data = {
207 .post_div_offset = 1,
210 static void __init sun5i_a13_pll2_setup(struct device_node *node)
212 sun4i_pll2_setup(node, &sun5i_a13_pll2_data);
215 CLK_OF_DECLARE(sun5i_a13_pll2, "allwinner,sun5i-a13-pll2-clk",
216 sun5i_a13_pll2_setup);