2 * SPEAr3xx machines clock framework source file
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/err.h>
16 #include <linux/of_platform.h>
17 #include <linux/spinlock_types.h>
20 static DEFINE_SPINLOCK(_lock);
22 #define PLL1_CTR (misc_base + 0x008)
23 #define PLL1_FRQ (misc_base + 0x00C)
24 #define PLL2_CTR (misc_base + 0x014)
25 #define PLL2_FRQ (misc_base + 0x018)
26 #define PLL_CLK_CFG (misc_base + 0x020)
27 /* PLL_CLK_CFG register masks */
28 #define MCTR_CLK_SHIFT 28
29 #define MCTR_CLK_MASK 3
31 #define CORE_CLK_CFG (misc_base + 0x024)
32 /* CORE CLK CFG register masks */
33 #define GEN_SYNTH2_3_CLK_SHIFT 18
34 #define GEN_SYNTH2_3_CLK_MASK 1
36 #define HCLK_RATIO_SHIFT 10
37 #define HCLK_RATIO_MASK 2
38 #define PCLK_RATIO_SHIFT 8
39 #define PCLK_RATIO_MASK 2
41 #define PERIP_CLK_CFG (misc_base + 0x028)
42 /* PERIP_CLK_CFG register masks */
43 #define UART_CLK_SHIFT 4
44 #define UART_CLK_MASK 1
45 #define FIRDA_CLK_SHIFT 5
46 #define FIRDA_CLK_MASK 2
47 #define GPT0_CLK_SHIFT 8
48 #define GPT1_CLK_SHIFT 11
49 #define GPT2_CLK_SHIFT 12
50 #define GPT_CLK_MASK 1
52 #define PERIP1_CLK_ENB (misc_base + 0x02C)
53 /* PERIP1_CLK_ENB register masks */
54 #define UART_CLK_ENB 3
57 #define JPEG_CLK_ENB 8
58 #define FIRDA_CLK_ENB 10
59 #define GPT1_CLK_ENB 11
60 #define GPT2_CLK_ENB 12
61 #define ADC_CLK_ENB 15
62 #define RTC_CLK_ENB 17
63 #define GPIO_CLK_ENB 18
64 #define DMA_CLK_ENB 19
65 #define SMI_CLK_ENB 21
66 #define GMAC_CLK_ENB 23
67 #define USBD_CLK_ENB 24
68 #define USBH_CLK_ENB 25
71 #define RAS_CLK_ENB (misc_base + 0x034)
72 #define RAS_AHB_CLK_ENB 0
73 #define RAS_PLL1_CLK_ENB 1
74 #define RAS_APB_CLK_ENB 2
75 #define RAS_32K_CLK_ENB 3
76 #define RAS_24M_CLK_ENB 4
77 #define RAS_48M_CLK_ENB 5
78 #define RAS_PLL2_CLK_ENB 7
79 #define RAS_SYNT0_CLK_ENB 8
80 #define RAS_SYNT1_CLK_ENB 9
81 #define RAS_SYNT2_CLK_ENB 10
82 #define RAS_SYNT3_CLK_ENB 11
84 #define PRSC0_CLK_CFG (misc_base + 0x044)
85 #define PRSC1_CLK_CFG (misc_base + 0x048)
86 #define PRSC2_CLK_CFG (misc_base + 0x04C)
87 #define AMEM_CLK_CFG (misc_base + 0x050)
88 #define AMEM_CLK_ENB 0
90 #define CLCD_CLK_SYNT (misc_base + 0x05C)
91 #define FIRDA_CLK_SYNT (misc_base + 0x060)
92 #define UART_CLK_SYNT (misc_base + 0x064)
93 #define GMAC_CLK_SYNT (misc_base + 0x068)
94 #define GEN0_CLK_SYNT (misc_base + 0x06C)
95 #define GEN1_CLK_SYNT (misc_base + 0x070)
96 #define GEN2_CLK_SYNT (misc_base + 0x074)
97 #define GEN3_CLK_SYNT (misc_base + 0x078)
99 /* pll rate configuration table, in ascending order of rates */
100 static struct pll_rate_tbl pll_rtbl[] = {
101 {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
102 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
103 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
106 /* aux rate configuration table, in ascending order of rates */
107 static struct aux_rate_tbl aux_rtbl[] = {
108 /* For PLL1 = 332 MHz */
109 {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
110 {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
111 {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
112 {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
113 {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
114 {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
115 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
116 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
117 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
118 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
121 /* gpt rate configuration table, in ascending order of rates */
122 static struct gpt_rate_tbl gpt_rtbl[] = {
123 /* For pll1 = 332 MHz */
124 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
125 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
126 {.mscale = 1, .nscale = 0}, /* 83 MHz */
130 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
131 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
133 static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
134 static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
135 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
136 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
137 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
140 #ifdef CONFIG_MACH_SPEAR300
141 static void __init spear300_clk_init(void)
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
147 clk_register_clkdev(clk, NULL, "60000000.clcd");
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
151 clk_register_clkdev(clk, NULL, "94000000.flash");
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
155 clk_register_clkdev(clk, NULL, "70000000.sdhci");
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
159 clk_register_clkdev(clk, NULL, "a9000000.gpio");
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
163 clk_register_clkdev(clk, NULL, "a0000000.kbd");
166 static inline void spear300_clk_init(void) { }
169 /* array of all spear 310 clock lookups */
170 #ifdef CONFIG_MACH_SPEAR310
171 static void __init spear310_clk_init(void)
175 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
177 clk_register_clkdev(clk, "emi", NULL);
179 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
181 clk_register_clkdev(clk, NULL, "44000000.flash");
183 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
185 clk_register_clkdev(clk, NULL, "tdm");
187 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
189 clk_register_clkdev(clk, NULL, "b2000000.serial");
191 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
193 clk_register_clkdev(clk, NULL, "b2080000.serial");
195 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
197 clk_register_clkdev(clk, NULL, "b2100000.serial");
199 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
201 clk_register_clkdev(clk, NULL, "b2180000.serial");
203 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
205 clk_register_clkdev(clk, NULL, "b2200000.serial");
208 static inline void spear310_clk_init(void) { }
211 /* array of all spear 320 clock lookups */
212 #ifdef CONFIG_MACH_SPEAR320
214 #define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
215 #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
217 #define SPEAR320_UARTX_PCLK_MASK 0x1
218 #define SPEAR320_UART2_PCLK_SHIFT 8
219 #define SPEAR320_UART3_PCLK_SHIFT 9
220 #define SPEAR320_UART4_PCLK_SHIFT 10
221 #define SPEAR320_UART5_PCLK_SHIFT 11
222 #define SPEAR320_UART6_PCLK_SHIFT 12
223 #define SPEAR320_RS485_PCLK_SHIFT 13
224 #define SMII_PCLK_SHIFT 18
225 #define SMII_PCLK_MASK 2
226 #define SMII_PCLK_VAL_PAD 0x0
227 #define SMII_PCLK_VAL_PLL2 0x1
228 #define SMII_PCLK_VAL_SYNTH0 0x2
229 #define SDHCI_PCLK_SHIFT 15
230 #define SDHCI_PCLK_MASK 1
231 #define SDHCI_PCLK_VAL_48M 0x0
232 #define SDHCI_PCLK_VAL_SYNTH3 0x1
233 #define I2S_REF_PCLK_SHIFT 8
234 #define I2S_REF_PCLK_MASK 1
235 #define I2S_REF_PCLK_SYNTH_VAL 0x1
236 #define I2S_REF_PCLK_PLL2_VAL 0x0
237 #define UART1_PCLK_SHIFT 6
238 #define UART1_PCLK_MASK 1
239 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
240 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1
242 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
243 static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
244 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
246 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
248 static void __init spear320_clk_init(void __iomem *soc_config_base)
252 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
253 CLK_IS_ROOT, 125000000);
254 clk_register_clkdev(clk, "smii_125m_pad", NULL);
256 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
258 clk_register_clkdev(clk, NULL, "90000000.clcd");
260 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
262 clk_register_clkdev(clk, "emi", NULL);
264 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
266 clk_register_clkdev(clk, NULL, "4c000000.flash");
268 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
270 clk_register_clkdev(clk, NULL, "a7000000.i2c");
272 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
274 clk_register_clkdev(clk, NULL, "a8000000.pwm");
276 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
278 clk_register_clkdev(clk, NULL, "a5000000.spi");
280 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
282 clk_register_clkdev(clk, NULL, "a6000000.spi");
284 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
286 clk_register_clkdev(clk, NULL, "c_can_platform.0");
288 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
290 clk_register_clkdev(clk, NULL, "c_can_platform.1");
292 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
294 clk_register_clkdev(clk, NULL, "a9400000.i2s");
296 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
297 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
298 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
299 I2S_REF_PCLK_MASK, 0, &_lock);
300 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
302 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
303 CLK_SET_RATE_PARENT, 1,
305 clk_register_clkdev(clk, "i2s_sclk", NULL);
307 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
309 clk_register_clkdev(clk, "hclk", "aa000000.eth");
311 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
313 clk_register_clkdev(clk, "hclk", "ab000000.eth");
315 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
316 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
317 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
318 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
319 clk_register_clkdev(clk, NULL, "a9300000.serial");
321 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
322 ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
323 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
325 clk_register_clkdev(clk, NULL, "70000000.sdhci");
327 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
328 ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG,
329 SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock);
330 clk_register_clkdev(clk, NULL, "smii_pclk");
332 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
333 clk_register_clkdev(clk, NULL, "smii");
335 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
336 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
337 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
339 clk_register_clkdev(clk, NULL, "a3000000.serial");
341 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
342 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
343 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
344 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
345 clk_register_clkdev(clk, NULL, "a4000000.serial");
347 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
348 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
351 clk_register_clkdev(clk, NULL, "a9100000.serial");
353 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
354 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
355 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
356 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
357 clk_register_clkdev(clk, NULL, "a9200000.serial");
359 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
360 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
361 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
362 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
363 clk_register_clkdev(clk, NULL, "60000000.serial");
365 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
366 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
367 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
368 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
369 clk_register_clkdev(clk, NULL, "60100000.serial");
372 static inline void spear320_clk_init(void __iomem *soc_config_base) { }
375 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
377 struct clk *clk, *clk1;
379 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
381 clk_register_clkdev(clk, "osc_32k_clk", NULL);
383 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
385 clk_register_clkdev(clk, "osc_24m_clk", NULL);
387 /* clock derived from 32 KHz osc clk */
388 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
389 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
390 clk_register_clkdev(clk, NULL, "fc900000.rtc");
392 /* clock derived from 24 MHz osc clk */
393 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
395 clk_register_clkdev(clk, "pll3_clk", NULL);
397 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
399 clk_register_clkdev(clk, NULL, "fc880000.wdt");
401 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
402 "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
403 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
404 clk_register_clkdev(clk, "vco1_clk", NULL);
405 clk_register_clkdev(clk1, "pll1_clk", NULL);
407 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
408 "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
409 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
410 clk_register_clkdev(clk, "vco2_clk", NULL);
411 clk_register_clkdev(clk1, "pll2_clk", NULL);
413 /* clock derived from pll1 clk */
414 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
415 CLK_SET_RATE_PARENT, 1, 1);
416 clk_register_clkdev(clk, "cpu_clk", NULL);
418 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
419 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
420 HCLK_RATIO_MASK, 0, &_lock);
421 clk_register_clkdev(clk, "ahb_clk", NULL);
423 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
424 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
426 clk_register_clkdev(clk, "uart_syn_clk", NULL);
427 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
429 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
430 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
431 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
433 clk_register_clkdev(clk, "uart0_mclk", NULL);
435 clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
436 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
438 clk_register_clkdev(clk, NULL, "d0000000.serial");
440 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
441 FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
443 clk_register_clkdev(clk, "firda_syn_clk", NULL);
444 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
446 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
447 ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
448 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
450 clk_register_clkdev(clk, "firda_mclk", NULL);
452 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
453 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
455 clk_register_clkdev(clk, NULL, "firda");
458 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
459 ARRAY_SIZE(gpt_rtbl), &_lock);
460 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
461 ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
462 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
463 clk_register_clkdev(clk, NULL, "gpt0");
465 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
466 ARRAY_SIZE(gpt_rtbl), &_lock);
467 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
468 ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
469 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
470 clk_register_clkdev(clk, "gpt1_mclk", NULL);
471 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
472 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
474 clk_register_clkdev(clk, NULL, "gpt1");
476 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
477 ARRAY_SIZE(gpt_rtbl), &_lock);
478 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
479 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
480 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
481 clk_register_clkdev(clk, "gpt2_mclk", NULL);
482 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
483 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
485 clk_register_clkdev(clk, NULL, "gpt2");
487 /* general synths clocks */
488 clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
489 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
491 clk_register_clkdev(clk, "gen0_syn_clk", NULL);
492 clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
494 clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
495 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
497 clk_register_clkdev(clk, "gen1_syn_clk", NULL);
498 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
500 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
501 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG,
502 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0,
504 clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
506 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
507 "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
508 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
509 clk_register_clkdev(clk, "gen2_syn_clk", NULL);
510 clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
512 clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
513 "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
514 ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
515 clk_register_clkdev(clk, "gen3_syn_clk", NULL);
516 clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
518 /* clock derived from pll3 clk */
519 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
520 USBH_CLK_ENB, 0, &_lock);
521 clk_register_clkdev(clk, NULL, "e1800000.ehci");
522 clk_register_clkdev(clk, NULL, "e1900000.ohci");
523 clk_register_clkdev(clk, NULL, "e2100000.ohci");
525 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
527 clk_register_clkdev(clk, "usbh.0_clk", NULL);
529 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
531 clk_register_clkdev(clk, "usbh.1_clk", NULL);
533 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
534 USBD_CLK_ENB, 0, &_lock);
535 clk_register_clkdev(clk, NULL, "e1100000.usbd");
537 /* clock derived from ahb clk */
538 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
540 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
542 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
543 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
544 MCTR_CLK_MASK, 0, &_lock);
545 clk_register_clkdev(clk, "ddr_clk", NULL);
547 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
548 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
549 PCLK_RATIO_MASK, 0, &_lock);
550 clk_register_clkdev(clk, "apb_clk", NULL);
552 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
553 AMEM_CLK_ENB, 0, &_lock);
554 clk_register_clkdev(clk, "amem_clk", NULL);
556 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
557 C3_CLK_ENB, 0, &_lock);
558 clk_register_clkdev(clk, NULL, "c3_clk");
560 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
561 DMA_CLK_ENB, 0, &_lock);
562 clk_register_clkdev(clk, NULL, "fc400000.dma");
564 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
565 GMAC_CLK_ENB, 0, &_lock);
566 clk_register_clkdev(clk, NULL, "e0800000.eth");
568 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
569 I2C_CLK_ENB, 0, &_lock);
570 clk_register_clkdev(clk, NULL, "d0180000.i2c");
572 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
573 JPEG_CLK_ENB, 0, &_lock);
574 clk_register_clkdev(clk, NULL, "jpeg");
576 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
577 SMI_CLK_ENB, 0, &_lock);
578 clk_register_clkdev(clk, NULL, "fc000000.flash");
580 /* clock derived from apb clk */
581 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
582 ADC_CLK_ENB, 0, &_lock);
583 clk_register_clkdev(clk, NULL, "d0080000.adc");
585 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
586 GPIO_CLK_ENB, 0, &_lock);
587 clk_register_clkdev(clk, NULL, "fc980000.gpio");
589 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
590 SSP_CLK_ENB, 0, &_lock);
591 clk_register_clkdev(clk, NULL, "d0100000.spi");
594 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
595 RAS_AHB_CLK_ENB, 0, &_lock);
596 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
598 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
599 RAS_APB_CLK_ENB, 0, &_lock);
600 clk_register_clkdev(clk, "ras_apb_clk", NULL);
602 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
603 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
604 clk_register_clkdev(clk, "ras_32k_clk", NULL);
606 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
607 RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
608 clk_register_clkdev(clk, "ras_24m_clk", NULL);
610 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
611 RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
612 clk_register_clkdev(clk, "ras_pll1_clk", NULL);
614 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
615 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
616 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
618 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
619 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
620 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
622 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
623 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
625 clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
627 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
628 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
630 clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
632 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
633 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
635 clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
637 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
638 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
640 clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
642 if (of_machine_is_compatible("st,spear300"))
644 else if (of_machine_is_compatible("st,spear310"))
646 else if (of_machine_is_compatible("st,spear320"))
647 spear320_clk_init(soc_config_base);