drivers/clk/spear/spear1310_clock.c

   1 /*
   2  * arch/arm/mach-spear13xx/spear1310_clock.c
   3  *
   4  * SPEAr1310 machine clock framework source file
   5  *
   6  * Copyright (C) 2012 ST Microelectronics
   7  * Viresh Kumar <viresh.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/spinlock_types.h>
  20 #include <mach/spear.h>
  21 #include "clk.h"
  22
  23 /* PLL related registers and bit values */
  24 #define SPEAR1310_PLL_CFG                       (VA_MISC_BASE + 0x210)
  25         /* PLL_CFG bit values */
  26         #define SPEAR1310_CLCD_SYNT_CLK_MASK            1
  27         #define SPEAR1310_CLCD_SYNT_CLK_SHIFT           31
  28         #define SPEAR1310_RAS_SYNT2_3_CLK_MASK          2
  29         #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT         29
  30         #define SPEAR1310_RAS_SYNT_CLK_MASK             2
  31         #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT         27
  32         #define SPEAR1310_PLL_CLK_MASK                  2
  33         #define SPEAR1310_PLL3_CLK_SHIFT                24
  34         #define SPEAR1310_PLL2_CLK_SHIFT                22
  35         #define SPEAR1310_PLL1_CLK_SHIFT                20
  36
  37 #define SPEAR1310_PLL1_CTR                      (VA_MISC_BASE + 0x214)
  38 #define SPEAR1310_PLL1_FRQ                      (VA_MISC_BASE + 0x218)
  39 #define SPEAR1310_PLL2_CTR                      (VA_MISC_BASE + 0x220)
  40 #define SPEAR1310_PLL2_FRQ                      (VA_MISC_BASE + 0x224)
  41 #define SPEAR1310_PLL3_CTR                      (VA_MISC_BASE + 0x22C)
  42 #define SPEAR1310_PLL3_FRQ                      (VA_MISC_BASE + 0x230)
  43 #define SPEAR1310_PLL4_CTR                      (VA_MISC_BASE + 0x238)
  44 #define SPEAR1310_PLL4_FRQ                      (VA_MISC_BASE + 0x23C)
  45 #define SPEAR1310_PERIP_CLK_CFG                 (VA_MISC_BASE + 0x244)
  46         /* PERIP_CLK_CFG bit values */
  47         #define SPEAR1310_GPT_OSC24_VAL                 0
  48         #define SPEAR1310_GPT_APB_VAL                   1
  49         #define SPEAR1310_GPT_CLK_MASK                  1
  50         #define SPEAR1310_GPT3_CLK_SHIFT                11
  51         #define SPEAR1310_GPT2_CLK_SHIFT                10
  52         #define SPEAR1310_GPT1_CLK_SHIFT                9
  53         #define SPEAR1310_GPT0_CLK_SHIFT                8
  54         #define SPEAR1310_UART_CLK_PLL5_VAL             0
  55         #define SPEAR1310_UART_CLK_OSC24_VAL            1
  56         #define SPEAR1310_UART_CLK_SYNT_VAL             2
  57         #define SPEAR1310_UART_CLK_MASK                 2
  58         #define SPEAR1310_UART_CLK_SHIFT                4
  59
  60         #define SPEAR1310_AUX_CLK_PLL5_VAL              0
  61         #define SPEAR1310_AUX_CLK_SYNT_VAL              1
  62         #define SPEAR1310_CLCD_CLK_MASK                 2
  63         #define SPEAR1310_CLCD_CLK_SHIFT                2
  64         #define SPEAR1310_C3_CLK_MASK                   1
  65         #define SPEAR1310_C3_CLK_SHIFT                  1
  66
  67 #define SPEAR1310_GMAC_CLK_CFG                  (VA_MISC_BASE + 0x248)
  68         #define SPEAR1310_GMAC_PHY_IF_SEL_MASK          3
  69         #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT         4
  70         #define SPEAR1310_GMAC_PHY_CLK_MASK             1
  71         #define SPEAR1310_GMAC_PHY_CLK_SHIFT            3
  72         #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK       2
  73         #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT      1
  74
  75 #define SPEAR1310_I2S_CLK_CFG                   (VA_MISC_BASE + 0x24C)
  76         /* I2S_CLK_CFG register mask */
  77         #define SPEAR1310_I2S_SCLK_X_MASK               0x1F
  78         #define SPEAR1310_I2S_SCLK_X_SHIFT              27
  79         #define SPEAR1310_I2S_SCLK_Y_MASK               0x1F
  80         #define SPEAR1310_I2S_SCLK_Y_SHIFT              22
  81         #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT         21
  82         #define SPEAR1310_I2S_SCLK_SYNTH_ENB            20
  83         #define SPEAR1310_I2S_PRS1_CLK_X_MASK           0xFF
  84         #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT          12
  85         #define SPEAR1310_I2S_PRS1_CLK_Y_MASK           0xFF
  86         #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT          4
  87         #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT         3
  88         #define SPEAR1310_I2S_REF_SEL_MASK              1
  89         #define SPEAR1310_I2S_REF_SHIFT                 2
  90         #define SPEAR1310_I2S_SRC_CLK_MASK              2
  91         #define SPEAR1310_I2S_SRC_CLK_SHIFT             0
  92
  93 #define SPEAR1310_C3_CLK_SYNT                   (VA_MISC_BASE + 0x250)
  94 #define SPEAR1310_UART_CLK_SYNT                 (VA_MISC_BASE + 0x254)
  95 #define SPEAR1310_GMAC_CLK_SYNT                 (VA_MISC_BASE + 0x258)
  96 #define SPEAR1310_SDHCI_CLK_SYNT                (VA_MISC_BASE + 0x25C)
  97 #define SPEAR1310_CFXD_CLK_SYNT                 (VA_MISC_BASE + 0x260)
  98 #define SPEAR1310_ADC_CLK_SYNT                  (VA_MISC_BASE + 0x264)
  99 #define SPEAR1310_AMBA_CLK_SYNT                 (VA_MISC_BASE + 0x268)
 100 #define SPEAR1310_CLCD_CLK_SYNT                 (VA_MISC_BASE + 0x270)
 101 #define SPEAR1310_RAS_CLK_SYNT0                 (VA_MISC_BASE + 0x280)
 102 #define SPEAR1310_RAS_CLK_SYNT1                 (VA_MISC_BASE + 0x288)
 103 #define SPEAR1310_RAS_CLK_SYNT2                 (VA_MISC_BASE + 0x290)
 104 #define SPEAR1310_RAS_CLK_SYNT3                 (VA_MISC_BASE + 0x298)
 105         /* Check Fractional synthesizer reg masks */
 106
 107 #define SPEAR1310_PERIP1_CLK_ENB                (VA_MISC_BASE + 0x300)
 108         /* PERIP1_CLK_ENB register masks */
 109         #define SPEAR1310_RTC_CLK_ENB                   31
 110         #define SPEAR1310_ADC_CLK_ENB                   30
 111         #define SPEAR1310_C3_CLK_ENB                    29
 112         #define SPEAR1310_JPEG_CLK_ENB                  28
 113         #define SPEAR1310_CLCD_CLK_ENB                  27
 114         #define SPEAR1310_DMA_CLK_ENB                   25
 115         #define SPEAR1310_GPIO1_CLK_ENB                 24
 116         #define SPEAR1310_GPIO0_CLK_ENB                 23
 117         #define SPEAR1310_GPT1_CLK_ENB                  22
 118         #define SPEAR1310_GPT0_CLK_ENB                  21
 119         #define SPEAR1310_I2S0_CLK_ENB                  20
 120         #define SPEAR1310_I2S1_CLK_ENB                  19
 121         #define SPEAR1310_I2C0_CLK_ENB                  18
 122         #define SPEAR1310_SSP_CLK_ENB                   17
 123         #define SPEAR1310_UART_CLK_ENB                  15
 124         #define SPEAR1310_PCIE_SATA_2_CLK_ENB           14
 125         #define SPEAR1310_PCIE_SATA_1_CLK_ENB           13
 126         #define SPEAR1310_PCIE_SATA_0_CLK_ENB           12
 127         #define SPEAR1310_UOC_CLK_ENB                   11
 128         #define SPEAR1310_UHC1_CLK_ENB                  10
 129         #define SPEAR1310_UHC0_CLK_ENB                  9
 130         #define SPEAR1310_GMAC_CLK_ENB                  8
 131         #define SPEAR1310_CFXD_CLK_ENB                  7
 132         #define SPEAR1310_SDHCI_CLK_ENB                 6
 133         #define SPEAR1310_SMI_CLK_ENB                   5
 134         #define SPEAR1310_FSMC_CLK_ENB                  4
 135         #define SPEAR1310_SYSRAM0_CLK_ENB               3
 136         #define SPEAR1310_SYSRAM1_CLK_ENB               2
 137         #define SPEAR1310_SYSROM_CLK_ENB                1
 138         #define SPEAR1310_BUS_CLK_ENB                   0
 139
 140 #define SPEAR1310_PERIP2_CLK_ENB                (VA_MISC_BASE + 0x304)
 141         /* PERIP2_CLK_ENB register masks */
 142         #define SPEAR1310_THSENS_CLK_ENB                8
 143         #define SPEAR1310_I2S_REF_PAD_CLK_ENB           7
 144         #define SPEAR1310_ACP_CLK_ENB                   6
 145         #define SPEAR1310_GPT3_CLK_ENB                  5
 146         #define SPEAR1310_GPT2_CLK_ENB                  4
 147         #define SPEAR1310_KBD_CLK_ENB                   3
 148         #define SPEAR1310_CPU_DBG_CLK_ENB               2
 149         #define SPEAR1310_DDR_CORE_CLK_ENB              1
 150         #define SPEAR1310_DDR_CTRL_CLK_ENB              0
 151
 152 #define SPEAR1310_RAS_CLK_ENB                   (VA_MISC_BASE + 0x310)
 153         /* RAS_CLK_ENB register masks */
 154         #define SPEAR1310_SYNT3_CLK_ENB                 17
 155         #define SPEAR1310_SYNT2_CLK_ENB                 16
 156         #define SPEAR1310_SYNT1_CLK_ENB                 15
 157         #define SPEAR1310_SYNT0_CLK_ENB                 14
 158         #define SPEAR1310_PCLK3_CLK_ENB                 13
 159         #define SPEAR1310_PCLK2_CLK_ENB                 12
 160         #define SPEAR1310_PCLK1_CLK_ENB                 11
 161         #define SPEAR1310_PCLK0_CLK_ENB                 10
 162         #define SPEAR1310_PLL3_CLK_ENB                  9
 163         #define SPEAR1310_PLL2_CLK_ENB                  8
 164         #define SPEAR1310_C125M_PAD_CLK_ENB             7
 165         #define SPEAR1310_C30M_CLK_ENB                  6
 166         #define SPEAR1310_C48M_CLK_ENB                  5
 167         #define SPEAR1310_OSC_25M_CLK_ENB               4
 168         #define SPEAR1310_OSC_32K_CLK_ENB               3
 169         #define SPEAR1310_OSC_24M_CLK_ENB               2
 170         #define SPEAR1310_PCLK_CLK_ENB                  1
 171         #define SPEAR1310_ACLK_CLK_ENB                  0
 172
 173 /* RAS Area Control Register */
 174 #define SPEAR1310_RAS_CTRL_REG0                 (VA_SPEAR1310_RAS_BASE + 0x000)
 175         #define SPEAR1310_SSP1_CLK_MASK                 3
 176         #define SPEAR1310_SSP1_CLK_SHIFT                26
 177         #define SPEAR1310_TDM_CLK_MASK                  1
 178         #define SPEAR1310_TDM2_CLK_SHIFT                24
 179         #define SPEAR1310_TDM1_CLK_SHIFT                23
 180         #define SPEAR1310_I2C_CLK_MASK                  1
 181         #define SPEAR1310_I2C7_CLK_SHIFT                22
 182         #define SPEAR1310_I2C6_CLK_SHIFT                21
 183         #define SPEAR1310_I2C5_CLK_SHIFT                20
 184         #define SPEAR1310_I2C4_CLK_SHIFT                19
 185         #define SPEAR1310_I2C3_CLK_SHIFT                18
 186         #define SPEAR1310_I2C2_CLK_SHIFT                17
 187         #define SPEAR1310_I2C1_CLK_SHIFT                16
 188         #define SPEAR1310_GPT64_CLK_MASK                1
 189         #define SPEAR1310_GPT64_CLK_SHIFT               15
 190         #define SPEAR1310_RAS_UART_CLK_MASK             1
 191         #define SPEAR1310_UART5_CLK_SHIFT               14
 192         #define SPEAR1310_UART4_CLK_SHIFT               13
 193         #define SPEAR1310_UART3_CLK_SHIFT               12
 194         #define SPEAR1310_UART2_CLK_SHIFT               11
 195         #define SPEAR1310_UART1_CLK_SHIFT               10
 196         #define SPEAR1310_PCI_CLK_MASK                  1
 197         #define SPEAR1310_PCI_CLK_SHIFT                 0
 198
 199 #define SPEAR1310_RAS_CTRL_REG1                 (VA_SPEAR1310_RAS_BASE + 0x004)
 200         #define SPEAR1310_PHY_CLK_MASK                  0x3
 201         #define SPEAR1310_RMII_PHY_CLK_SHIFT            0
 202         #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT      2
 203
 204 #define SPEAR1310_RAS_SW_CLK_CTRL               (VA_SPEAR1310_RAS_BASE + 0x0148)
 205         #define SPEAR1310_CAN1_CLK_ENB                  25
 206         #define SPEAR1310_CAN0_CLK_ENB                  24
 207         #define SPEAR1310_GPT64_CLK_ENB                 23
 208         #define SPEAR1310_SSP1_CLK_ENB                  22
 209         #define SPEAR1310_I2C7_CLK_ENB                  21
 210         #define SPEAR1310_I2C6_CLK_ENB                  20
 211         #define SPEAR1310_I2C5_CLK_ENB                  19
 212         #define SPEAR1310_I2C4_CLK_ENB                  18
 213         #define SPEAR1310_I2C3_CLK_ENB                  17
 214         #define SPEAR1310_I2C2_CLK_ENB                  16
 215         #define SPEAR1310_I2C1_CLK_ENB                  15
 216         #define SPEAR1310_UART5_CLK_ENB                 14
 217         #define SPEAR1310_UART4_CLK_ENB                 13
 218         #define SPEAR1310_UART3_CLK_ENB                 12
 219         #define SPEAR1310_UART2_CLK_ENB                 11
 220         #define SPEAR1310_UART1_CLK_ENB                 10
 221         #define SPEAR1310_RS485_1_CLK_ENB               9
 222         #define SPEAR1310_RS485_0_CLK_ENB               8
 223         #define SPEAR1310_TDM2_CLK_ENB                  7
 224         #define SPEAR1310_TDM1_CLK_ENB                  6
 225         #define SPEAR1310_PCI_CLK_ENB                   5
 226         #define SPEAR1310_GMII_CLK_ENB                  4
 227         #define SPEAR1310_MII2_CLK_ENB                  3
 228         #define SPEAR1310_MII1_CLK_ENB                  2
 229         #define SPEAR1310_MII0_CLK_ENB                  1
 230         #define SPEAR1310_ESRAM_CLK_ENB                 0
 231
 232 static DEFINE_SPINLOCK(_lock);
 233
 234 /* pll rate configuration table, in ascending order of rates */
 235 static struct pll_rate_tbl pll_rtbl[] = {
 236         /* PCLK 24MHz */
 237         {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
 238         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
 239         {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
 240         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
 241         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
 242         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
 243         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 244 };
 245
 246 /* vco-pll4 rate configuration table, in ascending order of rates */
 247 static struct pll_rate_tbl pll4_rtbl[] = {
 248         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
 249         {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
 250         {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
 251         {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
 252 };
 253
 254 /* aux rate configuration table, in ascending order of rates */
 255 static struct aux_rate_tbl aux_rtbl[] = {
 256         /* For VCO1div2 = 500 MHz */
 257         {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
 258         {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
 259         {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
 260         {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
 261         {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
 262         {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
 263 };
 264
 265 /* gmac rate configuration table, in ascending order of rates */
 266 static struct aux_rate_tbl gmac_rtbl[] = {
 267         /* For gmac phy input clk */
 268         {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
 269         {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
 270         {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
 271         {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
 272 };
 273
 274 /* clcd rate configuration table, in ascending order of rates */
 275 static struct frac_rate_tbl clcd_rtbl[] = {
 276         {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
 277         {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
 278         {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
 279         {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
 280         {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
 281         {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
 282         {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
 283         {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
 284         {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
 285         {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
 286 };
 287
 288 /* i2s prescaler1 masks */
 289 static struct aux_clk_masks i2s_prs1_masks = {
 290         .eq_sel_mask = AUX_EQ_SEL_MASK,
 291         .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
 292         .eq1_mask = AUX_EQ1_SEL,
 293         .eq2_mask = AUX_EQ2_SEL,
 294         .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
 295         .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
 296         .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
 297         .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
 298 };
 299
 300 /* i2s sclk (bit clock) syynthesizers masks */
 301 static struct aux_clk_masks i2s_sclk_masks = {
 302         .eq_sel_mask = AUX_EQ_SEL_MASK,
 303         .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
 304         .eq1_mask = AUX_EQ1_SEL,
 305         .eq2_mask = AUX_EQ2_SEL,
 306         .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
 307         .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
 308         .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
 309         .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
 310         .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
 311 };
 312
 313 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 314 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 315         /* For parent clk = 49.152 MHz */
 316         {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
 317 };
 318
 319 /* i2s sclk aux rate configuration table, in ascending order of rates */
 320 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
 321         /* For i2s_ref_clk = 12.288MHz */
 322         {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
 323         {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
 324 };
 325
 326 /* adc rate configuration table, in ascending order of rates */
 327 /* possible adc range is 2.5 MHz to 20 MHz. */
 328 static struct aux_rate_tbl adc_rtbl[] = {
 329         /* For ahb = 166.67 MHz */
 330         {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
 331         {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
 332         {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
 333         {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
 334 };
 335
 336 /* General synth rate configuration table, in ascending order of rates */
 337 static struct frac_rate_tbl gen_rtbl[] = {
 338         /* For vco1div4 = 250 MHz */
 339         {.div = 0x14000}, /* 25 MHz */
 340         {.div = 0x0A000}, /* 50 MHz */
 341         {.div = 0x05000}, /* 100 MHz */
 342         {.div = 0x02000}, /* 250 MHz */
 343 };
 344
 345 /* clock parents */
 346 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 347 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 348 static const char *uart0_parents[] = { "pll5_clk", "uart_synth_gate_clk", };
 349 static const char *c3_parents[] = { "pll5_clk", "c3_synth_gate_clk", };
 350 static const char *gmac_phy_input_parents[] = { "gmii_125m_pad_clk", "pll2_clk",
 351         "osc_25m_clk", };
 352 static const char *gmac_phy_parents[] = { "gmac_phy_input_mux_clk",
 353         "gmac_phy_synth_gate_clk", };
 354 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
 355 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_synth_clk", };
 356 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
 357         "i2s_src_pad_clk", };
 358 static const char *i2s_ref_parents[] = { "i2s_src_mux_clk", "i2s_prs1_clk", };
 359 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 360         "pll3_clk", };
 361 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
 362         "pll2_clk", };
 363 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
 364         "ras_pll2_clk", "ras_synth0_clk", };
 365 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
 366         "ras_pll2_clk", "ras_synth0_clk", };
 367 static const char *uart_parents[] = { "ras_apb_clk", "gen_synth3_clk", };
 368 static const char *i2c_parents[] = { "ras_apb_clk", "gen_synth1_clk", };
 369 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_synth1_clk",
 370         "ras_plclk0_clk", };
 371 static const char *pci_parents[] = { "ras_pll3_clk", "gen_synth2_clk", };
 372 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_synth1_clk", };
 373
 374 void __init spear1310_clk_init(void)
 375 {
 376         struct clk *clk, *clk1;
 377
 378         clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
 379         clk_register_clkdev(clk, "apb_pclk", NULL);
 380
 381         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 382                         32000);
 383         clk_register_clkdev(clk, "osc_32k_clk", NULL);
 384
 385         clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
 386                         24000000);
 387         clk_register_clkdev(clk, "osc_24m_clk", NULL);
 388
 389         clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
 390                         25000000);
 391         clk_register_clkdev(clk, "osc_25m_clk", NULL);
 392
 393         clk = clk_register_fixed_rate(NULL, "gmii_125m_pad_clk", NULL,
 394                         CLK_IS_ROOT, 125000000);
 395         clk_register_clkdev(clk, "gmii_125m_pad_clk", NULL);
 396
 397         clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
 398                         CLK_IS_ROOT, 12288000);
 399         clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
 400
 401         /* clock derived from 32 KHz osc clk */
 402         clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 403                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
 404                         &_lock);
 405         clk_register_clkdev(clk, NULL, "fc900000.rtc");
 406
 407         /* clock derived from 24 or 25 MHz osc clk */
 408         /* vco-pll */
 409         clk = clk_register_mux(NULL, "vco1_mux_clk", vco_parents,
 410                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 411                         SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 412                         &_lock);
 413         clk_register_clkdev(clk, "vco1_mux_clk", NULL);
 414         clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mux_clk",
 415                         0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
 416                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 417         clk_register_clkdev(clk, "vco1_clk", NULL);
 418         clk_register_clkdev(clk1, "pll1_clk", NULL);
 419
 420         clk = clk_register_mux(NULL, "vco2_mux_clk", vco_parents,
 421                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 422                         SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 423                         &_lock);
 424         clk_register_clkdev(clk, "vco2_mux_clk", NULL);
 425         clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mux_clk",
 426                         0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
 427                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 428         clk_register_clkdev(clk, "vco2_clk", NULL);
 429         clk_register_clkdev(clk1, "pll2_clk", NULL);
 430
 431         clk = clk_register_mux(NULL, "vco3_mux_clk", vco_parents,
 432                         ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG,
 433                         SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0,
 434                         &_lock);
 435         clk_register_clkdev(clk, "vco3_mux_clk", NULL);
 436         clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mux_clk",
 437                         0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
 438                         ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
 439         clk_register_clkdev(clk, "vco3_clk", NULL);
 440         clk_register_clkdev(clk1, "pll3_clk", NULL);
 441
 442         clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
 443                         0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
 444                         ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
 445         clk_register_clkdev(clk, "vco4_clk", NULL);
 446         clk_register_clkdev(clk1, "pll4_clk", NULL);
 447
 448         clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
 449                         48000000);
 450         clk_register_clkdev(clk, "pll5_clk", NULL);
 451
 452         clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
 453                         25000000);
 454         clk_register_clkdev(clk, "pll6_clk", NULL);
 455
 456         /* vco div n clocks */
 457         clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
 458                         2);
 459         clk_register_clkdev(clk, "vco1div2_clk", NULL);
 460
 461         clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
 462                         4);
 463         clk_register_clkdev(clk, "vco1div4_clk", NULL);
 464
 465         clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
 466                         2);
 467         clk_register_clkdev(clk, "vco2div2_clk", NULL);
 468
 469         clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
 470                         2);
 471         clk_register_clkdev(clk, "vco3div2_clk", NULL);
 472
 473         /* peripherals */
 474         clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
 475                         128);
 476         clk = clk_register_gate(NULL, "thermal_gate_clk", "thermal_clk", 0,
 477                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
 478                         &_lock);
 479         clk_register_clkdev(clk, NULL, "spear_thermal");
 480
 481         /* clock derived from pll4 clk */
 482         clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
 483                         1);
 484         clk_register_clkdev(clk, "ddr_clk", NULL);
 485
 486         /* clock derived from pll1 clk */
 487         clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2);
 488         clk_register_clkdev(clk, "cpu_clk", NULL);
 489
 490         clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
 491                         2);
 492         clk_register_clkdev(clk, NULL, "ec800620.wdt");
 493
 494         clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 495                         6);
 496         clk_register_clkdev(clk, "ahb_clk", NULL);
 497
 498         clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
 499                         12);
 500         clk_register_clkdev(clk, "apb_clk", NULL);
 501
 502         /* gpt clocks */
 503         clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt_parents,
 504                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 505                         SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 506                         &_lock);
 507         clk_register_clkdev(clk, "gpt0_mux_clk", NULL);
 508         clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mux_clk", 0,
 509                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
 510                         &_lock);
 511         clk_register_clkdev(clk, NULL, "gpt0");
 512
 513         clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt_parents,
 514                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 515                         SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 516                         &_lock);
 517         clk_register_clkdev(clk, "gpt1_mux_clk", NULL);
 518         clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0,
 519                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
 520                         &_lock);
 521         clk_register_clkdev(clk, NULL, "gpt1");
 522
 523         clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt_parents,
 524                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 525                         SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 526                         &_lock);
 527         clk_register_clkdev(clk, "gpt2_mux_clk", NULL);
 528         clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0,
 529                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
 530                         &_lock);
 531         clk_register_clkdev(clk, NULL, "gpt2");
 532
 533         clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt_parents,
 534                         ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 535                         SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0,
 536                         &_lock);
 537         clk_register_clkdev(clk, "gpt3_mux_clk", NULL);
 538         clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0,
 539                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
 540                         &_lock);
 541         clk_register_clkdev(clk, NULL, "gpt3");
 542
 543         /* others */
 544         clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk",
 545                         "vco1div2_clk", 0, SPEAR1310_UART_CLK_SYNT, NULL,
 546                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 547         clk_register_clkdev(clk, "uart_synth_clk", NULL);
 548         clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL);
 549
 550         clk = clk_register_mux(NULL, "uart0_mux_clk", uart0_parents,
 551                         ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 552                         SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0,
 553                         &_lock);
 554         clk_register_clkdev(clk, "uart0_mux_clk", NULL);
 555
 556         clk = clk_register_gate(NULL, "uart0_clk", "uart0_mux_clk", 0,
 557                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0,
 558                         &_lock);
 559         clk_register_clkdev(clk, NULL, "e0000000.serial");
 560
 561         clk = clk_register_aux("sdhci_synth_clk", "sdhci_synth_gate_clk",
 562                         "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
 563                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 564         clk_register_clkdev(clk, "sdhci_synth_clk", NULL);
 565         clk_register_clkdev(clk1, "sdhci_synth_gate_clk", NULL);
 566
 567         clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_synth_gate_clk", 0,
 568                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0,
 569                         &_lock);
 570         clk_register_clkdev(clk, NULL, "b3000000.sdhci");
 571
 572         clk = clk_register_aux("cfxd_synth_clk", "cfxd_synth_gate_clk",
 573                         "vco1div2_clk", 0, SPEAR1310_CFXD_CLK_SYNT, NULL,
 574                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 575         clk_register_clkdev(clk, "cfxd_synth_clk", NULL);
 576         clk_register_clkdev(clk1, "cfxd_synth_gate_clk", NULL);
 577
 578         clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_synth_gate_clk", 0,
 579                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0,
 580                         &_lock);
 581         clk_register_clkdev(clk, NULL, "b2800000.cf");
 582         clk_register_clkdev(clk, NULL, "arasan_xd");
 583
 584         clk = clk_register_aux("c3_synth_clk", "c3_synth_gate_clk",
 585                         "vco1div2_clk", 0, SPEAR1310_C3_CLK_SYNT, NULL,
 586                         aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
 587         clk_register_clkdev(clk, "c3_synth_clk", NULL);
 588         clk_register_clkdev(clk1, "c3_synth_gate_clk", NULL);
 589
 590         clk = clk_register_mux(NULL, "c3_mux_clk", c3_parents,
 591                         ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG,
 592                         SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0,
 593                         &_lock);
 594         clk_register_clkdev(clk, "c3_mux_clk", NULL);
 595
 596         clk = clk_register_gate(NULL, "c3_clk", "c3_mux_clk", 0,
 597                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
 598                         &_lock);
 599         clk_register_clkdev(clk, NULL, "c3");
 600
 601         /* gmac */
 602         clk = clk_register_mux(NULL, "gmac_phy_input_mux_clk",
 603                         gmac_phy_input_parents,
 604                         ARRAY_SIZE(gmac_phy_input_parents), 0,
 605                         SPEAR1310_GMAC_CLK_CFG,
 606                         SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
 607                         SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
 608         clk_register_clkdev(clk, "gmac_phy_input_mux_clk", NULL);
 609
 610         clk = clk_register_aux("gmac_phy_synth_clk", "gmac_phy_synth_gate_clk",
 611                         "gmac_phy_input_mux_clk", 0, SPEAR1310_GMAC_CLK_SYNT,
 612                         NULL, gmac_rtbl, ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
 613         clk_register_clkdev(clk, "gmac_phy_synth_clk", NULL);
 614         clk_register_clkdev(clk1, "gmac_phy_synth_gate_clk", NULL);
 615
 616         clk = clk_register_mux(NULL, "gmac_phy_mux_clk", gmac_phy_parents,
 617                         ARRAY_SIZE(gmac_phy_parents), 0,
 618                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 619                         SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
 620         clk_register_clkdev(clk, NULL, "stmmacphy.0");
 621
 622         /* clcd */
 623         clk = clk_register_mux(NULL, "clcd_synth_mux_clk", clcd_synth_parents,
 624                         ARRAY_SIZE(clcd_synth_parents), 0,
 625                         SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT,
 626                         SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
 627         clk_register_clkdev(clk, "clcd_synth_mux_clk", NULL);
 628
 629         clk = clk_register_frac("clcd_synth_clk", "clcd_synth_mux_clk", 0,
 630                         SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
 631                         ARRAY_SIZE(clcd_rtbl), &_lock);
 632         clk_register_clkdev(clk, "clcd_synth_clk", NULL);
 633
 634         clk = clk_register_mux(NULL, "clcd_pixel_mux_clk", clcd_pixel_parents,
 635                         ARRAY_SIZE(clcd_pixel_parents), 0,
 636                         SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 637                         SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
 638         clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
 639
 640         clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mux_clk", 0,
 641                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
 642                         &_lock);
 643         clk_register_clkdev(clk, "clcd_clk", NULL);
 644
 645         /* i2s */
 646         clk = clk_register_mux(NULL, "i2s_src_mux_clk", i2s_src_parents,
 647                         ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
 648                         SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
 649                         0, &_lock);
 650         clk_register_clkdev(clk, "i2s_src_clk", NULL);
 651
 652         clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mux_clk", 0,
 653                         SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
 654                         ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
 655         clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
 656
 657         clk = clk_register_mux(NULL, "i2s_ref_mux_clk", i2s_ref_parents,
 658                         ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG,
 659                         SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0,
 660                         &_lock);
 661         clk_register_clkdev(clk, "i2s_ref_clk", NULL);
 662
 663         clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mux_clk", 0,
 664                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
 665                         0, &_lock);
 666         clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 667
 668         clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gate_clk",
 669                         "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
 670                         &i2s_sclk_masks, i2s_sclk_rtbl,
 671                         ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
 672         clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
 673         clk_register_clkdev(clk1, "i2s_sclk_gate_clk", NULL);
 674
 675         /* clock derived from ahb clk */
 676         clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
 677                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
 678                         &_lock);
 679         clk_register_clkdev(clk, NULL, "e0280000.i2c");
 680
 681         clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
 682                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
 683                         &_lock);
 684         clk_register_clkdev(clk, NULL, "ea800000.dma");
 685         clk_register_clkdev(clk, NULL, "eb000000.dma");
 686
 687         clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
 688                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
 689                         &_lock);
 690         clk_register_clkdev(clk, NULL, "b2000000.jpeg");
 691
 692         clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
 693                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
 694                         &_lock);
 695         clk_register_clkdev(clk, NULL, "e2000000.eth");
 696
 697         clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
 698                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
 699                         &_lock);
 700         clk_register_clkdev(clk, NULL, "b0000000.flash");
 701
 702         clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
 703                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
 704                         &_lock);
 705         clk_register_clkdev(clk, NULL, "ea000000.flash");
 706
 707         clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 708                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
 709                         &_lock);
 710         clk_register_clkdev(clk, "usbh.0_clk", NULL);
 711
 712         clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 713                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
 714                         &_lock);
 715         clk_register_clkdev(clk, "usbh.1_clk", NULL);
 716
 717         clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 718                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
 719                         &_lock);
 720         clk_register_clkdev(clk, NULL, "uoc");
 721
 722         clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 723                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 724                         0, &_lock);
 725         clk_register_clkdev(clk, NULL, "dw_pcie.0");
 726         clk_register_clkdev(clk, NULL, "ahci.0");
 727
 728         clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 729                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 730                         0, &_lock);
 731         clk_register_clkdev(clk, NULL, "dw_pcie.1");
 732         clk_register_clkdev(clk, NULL, "ahci.1");
 733
 734         clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 735                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 736                         0, &_lock);
 737         clk_register_clkdev(clk, NULL, "dw_pcie.2");
 738         clk_register_clkdev(clk, NULL, "ahci.2");
 739
 740         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 741                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
 742                         &_lock);
 743         clk_register_clkdev(clk, "sysram0_clk", NULL);
 744
 745         clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
 746                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
 747                         &_lock);
 748         clk_register_clkdev(clk, "sysram1_clk", NULL);
 749
 750         clk = clk_register_aux("adc_synth_clk", "adc_synth_gate_clk", "ahb_clk",
 751                         0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
 752                         ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
 753         clk_register_clkdev(clk, "adc_synth_clk", NULL);
 754         clk_register_clkdev(clk1, "adc_synth_gate_clk", NULL);
 755
 756         clk = clk_register_gate(NULL, "adc_clk", "adc_synth_gate_clk", 0,
 757                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
 758                         &_lock);
 759         clk_register_clkdev(clk, NULL, "adc_clk");
 760
 761         /* clock derived from apb clk */
 762         clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
 763                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
 764                         &_lock);
 765         clk_register_clkdev(clk, NULL, "e0100000.spi");
 766
 767         clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
 768                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
 769                         &_lock);
 770         clk_register_clkdev(clk, NULL, "e0600000.gpio");
 771
 772         clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
 773                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
 774                         &_lock);
 775         clk_register_clkdev(clk, NULL, "e0680000.gpio");
 776
 777         clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
 778                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
 779                         &_lock);
 780         clk_register_clkdev(clk, NULL, "e0180000.i2s");
 781
 782         clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
 783                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
 784                         &_lock);
 785         clk_register_clkdev(clk, NULL, "e0200000.i2s");
 786
 787         clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
 788                         SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
 789                         &_lock);
 790         clk_register_clkdev(clk, NULL, "e0300000.kbd");
 791
 792         /* RAS clks */
 793         clk = clk_register_mux(NULL, "gen_synth0_1_mux_clk",
 794                         gen_synth0_1_parents, ARRAY_SIZE(gen_synth0_1_parents),
 795                         0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
 796                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 797         clk_register_clkdev(clk, "gen_synth0_1_clk", NULL);
 798
 799         clk = clk_register_mux(NULL, "gen_synth2_3_mux_clk",
 800                         gen_synth2_3_parents, ARRAY_SIZE(gen_synth2_3_parents),
 801                         0, SPEAR1310_PLL_CFG, SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
 802                         SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
 803         clk_register_clkdev(clk, "gen_synth2_3_clk", NULL);
 804
 805         clk = clk_register_frac("gen_synth0_clk", "gen_synth0_1_clk", 0,
 806                         SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 807                         &_lock);
 808         clk_register_clkdev(clk, "gen_synth0_clk", NULL);
 809
 810         clk = clk_register_frac("gen_synth1_clk", "gen_synth0_1_clk", 0,
 811                         SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 812                         &_lock);
 813         clk_register_clkdev(clk, "gen_synth1_clk", NULL);
 814
 815         clk = clk_register_frac("gen_synth2_clk", "gen_synth2_3_clk", 0,
 816                         SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 817                         &_lock);
 818         clk_register_clkdev(clk, "gen_synth2_clk", NULL);
 819
 820         clk = clk_register_frac("gen_synth3_clk", "gen_synth2_3_clk", 0,
 821                         SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 822                         &_lock);
 823         clk_register_clkdev(clk, "gen_synth3_clk", NULL);
 824
 825         clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
 826                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
 827                         &_lock);
 828         clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
 829
 830         clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
 831                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
 832                         &_lock);
 833         clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
 834
 835         clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
 836                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
 837                         &_lock);
 838         clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
 839
 840         clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
 841                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
 842                         &_lock);
 843         clk_register_clkdev(clk, "ras_pll2_clk", NULL);
 844
 845         clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
 846                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
 847                         &_lock);
 848         clk_register_clkdev(clk, "ras_pll3_clk", NULL);
 849
 850         clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_125m_pad_clk", 0,
 851                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
 852                         &_lock);
 853         clk_register_clkdev(clk, "ras_tx125_clk", NULL);
 854
 855         clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
 856                         30000000);
 857         clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
 858                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
 859                         &_lock);
 860         clk_register_clkdev(clk, "ras_30m_clk", NULL);
 861
 862         clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
 863                         48000000);
 864         clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
 865                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
 866                         &_lock);
 867         clk_register_clkdev(clk, "ras_48m_clk", NULL);
 868
 869         clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
 870                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
 871                         &_lock);
 872         clk_register_clkdev(clk, "ras_ahb_clk", NULL);
 873
 874         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
 875                         SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
 876                         &_lock);
 877         clk_register_clkdev(clk, "ras_apb_clk", NULL);
 878
 879         clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
 880                         50000000);
 881
 882         clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
 883                         50000000);
 884
 885         clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
 886                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
 887                         &_lock);
 888         clk_register_clkdev(clk, NULL, "c_can_platform.0");
 889
 890         clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
 891                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
 892                         &_lock);
 893         clk_register_clkdev(clk, NULL, "c_can_platform.1");
 894
 895         clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
 896                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
 897                         &_lock);
 898         clk_register_clkdev(clk, NULL, "5c400000.eth");
 899
 900         clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
 901                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
 902                         &_lock);
 903         clk_register_clkdev(clk, NULL, "5c500000.eth");
 904
 905         clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
 906                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
 907                         &_lock);
 908         clk_register_clkdev(clk, NULL, "5c600000.eth");
 909
 910         clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
 911                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
 912                         &_lock);
 913         clk_register_clkdev(clk, NULL, "5c700000.eth");
 914
 915         clk = clk_register_mux(NULL, "smii_rgmii_phy_mux_clk",
 916                         smii_rgmii_phy_parents,
 917                         ARRAY_SIZE(smii_rgmii_phy_parents), 0,
 918                         SPEAR1310_RAS_CTRL_REG1,
 919                         SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 920                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 921         clk_register_clkdev(clk, NULL, "stmmacphy.1");
 922         clk_register_clkdev(clk, NULL, "stmmacphy.2");
 923         clk_register_clkdev(clk, NULL, "stmmacphy.4");
 924
 925         clk = clk_register_mux(NULL, "rmii_phy_mux_clk", rmii_phy_parents,
 926                         ARRAY_SIZE(rmii_phy_parents), 0,
 927                         SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 928                         SPEAR1310_PHY_CLK_MASK, 0, &_lock);
 929         clk_register_clkdev(clk, NULL, "stmmacphy.3");
 930
 931         clk = clk_register_mux(NULL, "uart1_mux_clk", uart_parents,
 932                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 933                         SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 934                         0, &_lock);
 935         clk_register_clkdev(clk, "uart1_mux_clk", NULL);
 936
 937         clk = clk_register_gate(NULL, "uart1_clk", "uart1_mux_clk", 0,
 938                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
 939                         &_lock);
 940         clk_register_clkdev(clk, NULL, "5c800000.serial");
 941
 942         clk = clk_register_mux(NULL, "uart2_mux_clk", uart_parents,
 943                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 944                         SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 945                         0, &_lock);
 946         clk_register_clkdev(clk, "uart2_mux_clk", NULL);
 947
 948         clk = clk_register_gate(NULL, "uart2_clk", "uart2_mux_clk", 0,
 949                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
 950                         &_lock);
 951         clk_register_clkdev(clk, NULL, "5c900000.serial");
 952
 953         clk = clk_register_mux(NULL, "uart3_mux_clk", uart_parents,
 954                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 955                         SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 956                         0, &_lock);
 957         clk_register_clkdev(clk, "uart3_mux_clk", NULL);
 958
 959         clk = clk_register_gate(NULL, "uart3_clk", "uart3_mux_clk", 0,
 960                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
 961                         &_lock);
 962         clk_register_clkdev(clk, NULL, "5ca00000.serial");
 963
 964         clk = clk_register_mux(NULL, "uart4_mux_clk", uart_parents,
 965                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 966                         SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 967                         0, &_lock);
 968         clk_register_clkdev(clk, "uart4_mux_clk", NULL);
 969
 970         clk = clk_register_gate(NULL, "uart4_clk", "uart4_mux_clk", 0,
 971                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
 972                         &_lock);
 973         clk_register_clkdev(clk, NULL, "5cb00000.serial");
 974
 975         clk = clk_register_mux(NULL, "uart5_mux_clk", uart_parents,
 976                         ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 977                         SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK,
 978                         0, &_lock);
 979         clk_register_clkdev(clk, "uart5_mux_clk", NULL);
 980
 981         clk = clk_register_gate(NULL, "uart5_clk", "uart5_mux_clk", 0,
 982                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
 983                         &_lock);
 984         clk_register_clkdev(clk, NULL, "5cc00000.serial");
 985
 986         clk = clk_register_mux(NULL, "i2c1_mux_clk", i2c_parents,
 987                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 988                         SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
 989                         &_lock);
 990         clk_register_clkdev(clk, "i2c1_mux_clk", NULL);
 991
 992         clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mux_clk", 0,
 993                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
 994                         &_lock);
 995         clk_register_clkdev(clk, NULL, "5cd00000.i2c");
 996
 997         clk = clk_register_mux(NULL, "i2c2_mux_clk", i2c_parents,
 998                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
 999                         SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1000                         &_lock);
1001         clk_register_clkdev(clk, "i2c2_mux_clk", NULL);
1002
1003         clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mux_clk", 0,
1004                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1005                         &_lock);
1006         clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1007
1008         clk = clk_register_mux(NULL, "i2c3_mux_clk", i2c_parents,
1009                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1010                         SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1011                         &_lock);
1012         clk_register_clkdev(clk, "i2c3_mux_clk", NULL);
1013
1014         clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mux_clk", 0,
1015                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1016                         &_lock);
1017         clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1018
1019         clk = clk_register_mux(NULL, "i2c4_mux_clk", i2c_parents,
1020                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1021                         SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1022                         &_lock);
1023         clk_register_clkdev(clk, "i2c4_mux_clk", NULL);
1024
1025         clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mux_clk", 0,
1026                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1027                         &_lock);
1028         clk_register_clkdev(clk, NULL, "5d000000.i2c");
1029
1030         clk = clk_register_mux(NULL, "i2c5_mux_clk", i2c_parents,
1031                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1032                         SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1033                         &_lock);
1034         clk_register_clkdev(clk, "i2c5_mux_clk", NULL);
1035
1036         clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mux_clk", 0,
1037                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1038                         &_lock);
1039         clk_register_clkdev(clk, NULL, "5d100000.i2c");
1040
1041         clk = clk_register_mux(NULL, "i2c6_mux_clk", i2c_parents,
1042                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1043                         SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1044                         &_lock);
1045         clk_register_clkdev(clk, "i2c6_mux_clk", NULL);
1046
1047         clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mux_clk", 0,
1048                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1049                         &_lock);
1050         clk_register_clkdev(clk, NULL, "5d200000.i2c");
1051
1052         clk = clk_register_mux(NULL, "i2c7_mux_clk", i2c_parents,
1053                         ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1054                         SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0,
1055                         &_lock);
1056         clk_register_clkdev(clk, "i2c7_mux_clk", NULL);
1057
1058         clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mux_clk", 0,
1059                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1060                         &_lock);
1061         clk_register_clkdev(clk, NULL, "5d300000.i2c");
1062
1063         clk = clk_register_mux(NULL, "ssp1_mux_clk", ssp1_parents,
1064                         ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1065                         SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0,
1066                         &_lock);
1067         clk_register_clkdev(clk, "ssp1_mux_clk", NULL);
1068
1069         clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mux_clk", 0,
1070                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1071                         &_lock);
1072         clk_register_clkdev(clk, NULL, "5d400000.spi");
1073
1074         clk = clk_register_mux(NULL, "pci_mux_clk", pci_parents,
1075                         ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1076                         SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0,
1077                         &_lock);
1078         clk_register_clkdev(clk, "pci_mux_clk", NULL);
1079
1080         clk = clk_register_gate(NULL, "pci_clk", "pci_mux_clk", 0,
1081                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1082                         &_lock);
1083         clk_register_clkdev(clk, NULL, "pci");
1084
1085         clk = clk_register_mux(NULL, "tdm1_mux_clk", tdm_parents,
1086                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1087                         SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1088                         &_lock);
1089         clk_register_clkdev(clk, "tdm1_mux_clk", NULL);
1090
1091         clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mux_clk", 0,
1092                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1093                         &_lock);
1094         clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1095
1096         clk = clk_register_mux(NULL, "tdm2_mux_clk", tdm_parents,
1097                         ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0,
1098                         SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0,
1099                         &_lock);
1100         clk_register_clkdev(clk, "tdm2_mux_clk", NULL);
1101
1102         clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mux_clk", 0,
1103                         SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1104                         &_lock);
1105         clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1106 }