2 * Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
4 * based on drivers/clk/tegra/clk.h
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #ifndef __SOCFPGA_CLK_H
18 #define __SOCFPGA_CLK_H
20 #include <linux/clk-provider.h>
21 #include <linux/clkdev.h>
23 /* Clock Manager offsets */
24 #define CLKMGR_CTRL 0x0
25 #define CLKMGR_BYPASS 0x4
26 #define CLKMGR_L4SRC 0x70
27 #define CLKMGR_PERPLL_SRC 0xAC
29 #define SOCFPGA_MAX_PARENTS 5
30 #define div_mask(width) ((1 << (width)) - 1)
32 #define streq(a, b) (strcmp((a), (b)) == 0)
33 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
34 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))
36 extern void __iomem *clk_mgr_base_addr;
37 extern void __iomem *clk_mgr_a10_base_addr;
39 void __init socfpga_pll_init(struct device_node *node);
40 void __init socfpga_periph_init(struct device_node *node);
41 void __init socfpga_gate_init(struct device_node *node);
42 void socfpga_a10_pll_init(struct device_node *node);
43 void socfpga_a10_periph_init(struct device_node *node);
44 void socfpga_a10_gate_init(struct device_node *node);
50 struct socfpga_gate_clk {
54 void __iomem *div_reg;
55 struct regmap *sys_mgr_base_addr;
56 u32 width; /* only valid if div_reg != 0 */
57 u32 shift; /* only valid if div_reg != 0 */
61 struct socfpga_periph_clk {
65 void __iomem *div_reg;
66 u32 width; /* only valid if div_reg != 0 */
67 u32 shift; /* only valid if div_reg != 0 */
70 #endif /* SOCFPGA_CLK_H */