2 * Copyright 2011-2012 Calxeda, Inc.
3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * Based from clk-highbank.c
18 #include <linux/clk.h>
19 #include <linux/clkdev.h>
20 #include <linux/clk-provider.h>
22 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
28 #define SOCFPGA_L4_MP_CLK "l4_mp_clk"
29 #define SOCFPGA_L4_SP_CLK "l4_sp_clk"
30 #define SOCFPGA_NAND_CLK "nand_clk"
31 #define SOCFPGA_NAND_X_CLK "nand_x_clk"
32 #define SOCFPGA_MMC_CLK "sdmmc_clk"
33 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8
35 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
37 /* SDMMC Group for System Manager defines */
38 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
40 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
45 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
46 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
49 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
50 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
51 return !!(l4_src & 2);
54 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
55 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
56 return perpll_src &= 0x3;
57 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
58 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
59 return (perpll_src >> 2) & 3;
62 return (perpll_src >> 4) & 3;
66 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
70 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
71 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
74 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
75 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
76 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
78 src_reg |= (parent << 1);
79 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
81 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
82 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
85 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
86 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
88 src_reg |= (parent << 2);
89 } else {/* QSPI clock */
91 src_reg |= (parent << 4);
93 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
99 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
100 unsigned long parent_rate)
102 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
105 if (socfpgaclk->fixed_div)
106 div = socfpgaclk->fixed_div;
107 else if (socfpgaclk->div_reg) {
108 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
109 val &= div_mask(socfpgaclk->width);
110 /* Check for GPIO_DB_CLK by its offset */
111 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
117 return parent_rate / div;
120 static int socfpga_clk_prepare(struct clk_hw *hwclk)
122 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
123 struct regmap *sys_mgr_base_addr;
128 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
129 sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
130 if (IS_ERR(sys_mgr_base_addr)) {
131 pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__);
135 for (i = 0; i < 2; i++) {
136 switch (socfpgaclk->clk_phase[i]) {
166 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]);
167 regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET,
173 static struct clk_ops gateclk_ops = {
174 .prepare = socfpga_clk_prepare,
175 .recalc_rate = socfpga_clk_recalc_rate,
176 .get_parent = socfpga_clk_get_parent,
177 .set_parent = socfpga_clk_set_parent,
180 static void __init __socfpga_gate_init(struct device_node *node,
181 const struct clk_ops *ops)
188 struct socfpga_gate_clk *socfpga_clk;
189 const char *clk_name = node->name;
190 const char *parent_name[SOCFPGA_MAX_PARENTS];
191 struct clk_init_data init;
194 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
195 if (WARN_ON(!socfpga_clk))
198 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
203 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
204 socfpga_clk->hw.bit_idx = clk_gate[1];
206 gateclk_ops.enable = clk_gate_ops.enable;
207 gateclk_ops.disable = clk_gate_ops.disable;
210 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
212 socfpga_clk->fixed_div = 0;
214 socfpga_clk->fixed_div = fixed_div;
216 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
218 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
219 socfpga_clk->shift = div_reg[1];
220 socfpga_clk->width = div_reg[2];
222 socfpga_clk->div_reg = NULL;
225 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
227 socfpga_clk->clk_phase[0] = clk_phase[0];
228 socfpga_clk->clk_phase[1] = clk_phase[1];
231 of_property_read_string(node, "clock-output-names", &clk_name);
233 init.name = clk_name;
237 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
238 init.parent_names = parent_name;
239 socfpga_clk->hw.hw.init = &init;
241 clk = clk_register(NULL, &socfpga_clk->hw.hw);
242 if (WARN_ON(IS_ERR(clk))) {
246 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
251 void __init socfpga_gate_init(struct device_node *node)
253 __socfpga_gate_init(node, &gateclk_ops);