2 * common clks module for all SiRF SoCs
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
7 * Licensed under GPLv2 or later.
11 #define MHZ (KHZ * KHZ)
13 static void __iomem *sirfsoc_clk_vbase;
14 static void __iomem *sirfsoc_rsc_vbase;
15 static struct clk_onecell_data clk_data;
18 * SiRFprimaII clock controller
19 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
20 * - 3 standard configurable plls: pll1, pll2 & pll3
21 * - 2 exclusive plls: usb phy pll and sata phy pll
22 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
24 * Each clock domain can select its own clock source from five clock sources,
25 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
26 * clock of the group clock.
27 * - dsp domain: gps, mf
28 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
29 * - sys domain: security
34 unsigned short regofs; /* register offset */
37 #define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
41 signed char enable_bit; /* enable bit: 0 ~ 63 */
42 unsigned short regofs; /* register offset */
45 #define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
49 signed char enable_bit; /* enable bit: 0 ~ 63 */
52 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
54 static int std_clk_is_enabled(struct clk_hw *hw);
55 static int std_clk_enable(struct clk_hw *hw);
56 static void std_clk_disable(struct clk_hw *hw);
58 static inline unsigned long clkc_readl(unsigned reg)
60 return readl(sirfsoc_clk_vbase + reg);
63 static inline void clkc_writel(u32 val, unsigned reg)
65 writel(val, sirfsoc_clk_vbase + reg);
72 static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
73 unsigned long parent_rate)
75 unsigned long fin = parent_rate;
76 struct clk_pll *clk = to_pllclk(hw);
77 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
78 SIRFSOC_CLKC_PLL1_CFG0;
80 if (clkc_readl(regcfg2) & BIT(2)) {
84 /* fout = fin * nf / nr / od */
85 u32 cfg0 = clkc_readl(clk->regofs);
86 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
87 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
88 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
90 return fin / MHZ * nf / nr / od * MHZ;
94 static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
95 unsigned long *parent_rate)
97 unsigned long fin, nf, nr, od;
101 * fout = fin * nf / (nr * od);
102 * set od = 1, nr = fin/MHz, so fout = nf * MHz
104 rate = rate - rate % MHZ;
119 dividend = (u64)fin * nf;
120 do_div(dividend, nr * od);
122 return (long)dividend;
125 static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
126 unsigned long parent_rate)
128 struct clk_pll *clk = to_pllclk(hw);
129 unsigned long fin, nf, nr, od, reg;
132 * fout = fin * nf / (nr * od);
133 * set od = 1, nr = fin/MHz, so fout = nf * MHz
137 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
144 BUG_ON((fin % MHZ) || nr > BIT(6));
148 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
149 clkc_writel(reg, clk->regofs);
151 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
152 clkc_writel((nf >> 1) - 1, reg);
154 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
155 while (!(clkc_readl(reg) & BIT(6)))
161 static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
162 unsigned long *parent_rate)
165 * SiRF SoC has not cpu clock control,
166 * So bypass to it's parent pll.
168 struct clk *parent_clk = clk_get_parent(hw->clk);
169 struct clk *pll_parent_clk = clk_get_parent(parent_clk);
170 unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk);
171 return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate);
174 static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
175 unsigned long parent_rate)
178 * SiRF SoC has not cpu clock control,
179 * So return the parent pll rate.
181 struct clk *parent_clk = clk_get_parent(hw->clk);
182 return __clk_get_rate(parent_clk);
185 static struct clk_ops std_pll_ops = {
186 .recalc_rate = pll_clk_recalc_rate,
187 .round_rate = pll_clk_round_rate,
188 .set_rate = pll_clk_set_rate,
191 static const char * const pll_clk_parents[] = {
195 static struct clk_init_data clk_pll1_init = {
198 .parent_names = pll_clk_parents,
199 .num_parents = ARRAY_SIZE(pll_clk_parents),
202 static struct clk_init_data clk_pll2_init = {
205 .parent_names = pll_clk_parents,
206 .num_parents = ARRAY_SIZE(pll_clk_parents),
209 static struct clk_init_data clk_pll3_init = {
212 .parent_names = pll_clk_parents,
213 .num_parents = ARRAY_SIZE(pll_clk_parents),
216 static struct clk_pll clk_pll1 = {
217 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
219 .init = &clk_pll1_init,
223 static struct clk_pll clk_pll2 = {
224 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
226 .init = &clk_pll2_init,
230 static struct clk_pll clk_pll3 = {
231 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
233 .init = &clk_pll3_init,
238 * usb uses specified pll
241 static int usb_pll_clk_enable(struct clk_hw *hw)
243 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
244 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
245 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
246 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
247 SIRFSOC_USBPHY_PLL_LOCK))
253 static void usb_pll_clk_disable(struct clk_hw *clk)
255 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
256 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
257 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
260 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
262 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
263 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
266 static struct clk_ops usb_pll_ops = {
267 .enable = usb_pll_clk_enable,
268 .disable = usb_pll_clk_disable,
269 .recalc_rate = usb_pll_clk_recalc_rate,
272 static struct clk_init_data clk_usb_pll_init = {
275 .parent_names = pll_clk_parents,
276 .num_parents = ARRAY_SIZE(pll_clk_parents),
279 static struct clk_hw usb_pll_clk_hw = {
280 .init = &clk_usb_pll_init,
284 * clock domains - cpu, mem, sys/io, dsp, gfx
287 static const char * const dmn_clk_parents[] = {
295 static u8 dmn_clk_get_parent(struct clk_hw *hw)
297 struct clk_dmn *clk = to_dmnclk(hw);
298 u32 cfg = clkc_readl(clk->regofs);
300 /* parent of io domain can only be pll3 */
301 if (strcmp(hw->init->name, "io") == 0)
304 WARN_ON((cfg & (BIT(3) - 1)) > 4);
306 return cfg & (BIT(3) - 1);
309 static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
311 struct clk_dmn *clk = to_dmnclk(hw);
312 u32 cfg = clkc_readl(clk->regofs);
314 /* parent of io domain can only be pll3 */
315 if (strcmp(hw->init->name, "io") == 0)
318 cfg &= ~(BIT(3) - 1);
319 clkc_writel(cfg | parent, clk->regofs);
320 /* BIT(3) - switching status: 1 - busy, 0 - done */
321 while (clkc_readl(clk->regofs) & BIT(3))
327 static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
328 unsigned long parent_rate)
331 unsigned long fin = parent_rate;
332 struct clk_dmn *clk = to_dmnclk(hw);
334 u32 cfg = clkc_readl(clk->regofs);
337 /* fcd bypass mode */
341 * wait count: bit[19:16], hold count: bit[23:20]
343 u32 wait = (cfg >> 16) & (BIT(4) - 1);
344 u32 hold = (cfg >> 20) & (BIT(4) - 1);
346 return fin / (wait + hold + 2);
350 static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
351 unsigned long *parent_rate)
354 unsigned ratio, wait, hold;
355 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
362 if (ratio > BIT(bits + 1))
363 ratio = BIT(bits + 1);
365 wait = (ratio >> 1) - 1;
366 hold = ratio - wait - 2;
368 return fin / (wait + hold + 2);
371 static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
372 unsigned long parent_rate)
374 struct clk_dmn *clk = to_dmnclk(hw);
376 unsigned ratio, wait, hold, reg;
377 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
382 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
387 wait = (ratio >> 1) - 1;
388 hold = ratio - wait - 2;
390 reg = clkc_readl(clk->regofs);
391 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
392 reg |= (wait << 16) | (hold << 20) | BIT(25);
393 clkc_writel(reg, clk->regofs);
395 /* waiting FCD been effective */
396 while (clkc_readl(clk->regofs) & BIT(25))
402 static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
403 unsigned long parent_rate)
406 struct clk *cur_parent;
408 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
409 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
413 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
414 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
418 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
419 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
423 cur_parent = clk_get_parent(hw->clk);
425 /* switch to tmp pll before setting parent clock's rate */
426 if (cur_parent == clk_pll1.hw.clk) {
427 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
431 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
433 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
435 return ret2 ? ret2 : ret1;
438 static struct clk_ops msi_ops = {
439 .set_rate = dmn_clk_set_rate,
440 .round_rate = dmn_clk_round_rate,
441 .recalc_rate = dmn_clk_recalc_rate,
442 .set_parent = dmn_clk_set_parent,
443 .get_parent = dmn_clk_get_parent,
446 static struct clk_init_data clk_mem_init = {
449 .parent_names = dmn_clk_parents,
450 .num_parents = ARRAY_SIZE(dmn_clk_parents),
453 static struct clk_dmn clk_mem = {
454 .regofs = SIRFSOC_CLKC_MEM_CFG,
456 .init = &clk_mem_init,
460 static struct clk_init_data clk_sys_init = {
463 .parent_names = dmn_clk_parents,
464 .num_parents = ARRAY_SIZE(dmn_clk_parents),
465 .flags = CLK_SET_RATE_GATE,
468 static struct clk_dmn clk_sys = {
469 .regofs = SIRFSOC_CLKC_SYS_CFG,
471 .init = &clk_sys_init,
475 static struct clk_init_data clk_io_init = {
478 .parent_names = dmn_clk_parents,
479 .num_parents = ARRAY_SIZE(dmn_clk_parents),
482 static struct clk_dmn clk_io = {
483 .regofs = SIRFSOC_CLKC_IO_CFG,
485 .init = &clk_io_init,
489 static struct clk_ops cpu_ops = {
490 .set_parent = dmn_clk_set_parent,
491 .get_parent = dmn_clk_get_parent,
492 .set_rate = cpu_clk_set_rate,
493 .round_rate = cpu_clk_round_rate,
494 .recalc_rate = cpu_clk_recalc_rate,
497 static struct clk_init_data clk_cpu_init = {
500 .parent_names = dmn_clk_parents,
501 .num_parents = ARRAY_SIZE(dmn_clk_parents),
502 .flags = CLK_SET_RATE_PARENT,
505 static struct clk_dmn clk_cpu = {
506 .regofs = SIRFSOC_CLKC_CPU_CFG,
508 .init = &clk_cpu_init,
512 static struct clk_ops dmn_ops = {
513 .is_enabled = std_clk_is_enabled,
514 .enable = std_clk_enable,
515 .disable = std_clk_disable,
516 .set_rate = dmn_clk_set_rate,
517 .round_rate = dmn_clk_round_rate,
518 .recalc_rate = dmn_clk_recalc_rate,
519 .set_parent = dmn_clk_set_parent,
520 .get_parent = dmn_clk_get_parent,
523 /* dsp, gfx, mm, lcd and vpp domain */
525 static struct clk_init_data clk_dsp_init = {
528 .parent_names = dmn_clk_parents,
529 .num_parents = ARRAY_SIZE(dmn_clk_parents),
532 static struct clk_dmn clk_dsp = {
533 .regofs = SIRFSOC_CLKC_DSP_CFG,
536 .init = &clk_dsp_init,
540 static struct clk_init_data clk_gfx_init = {
543 .parent_names = dmn_clk_parents,
544 .num_parents = ARRAY_SIZE(dmn_clk_parents),
547 static struct clk_dmn clk_gfx = {
548 .regofs = SIRFSOC_CLKC_GFX_CFG,
551 .init = &clk_gfx_init,
555 static struct clk_init_data clk_mm_init = {
558 .parent_names = dmn_clk_parents,
559 .num_parents = ARRAY_SIZE(dmn_clk_parents),
562 static struct clk_dmn clk_mm = {
563 .regofs = SIRFSOC_CLKC_MM_CFG,
566 .init = &clk_mm_init,
571 * for atlas6, gfx2d holds the bit of prima2's clk_mm
573 #define clk_gfx2d clk_mm
575 static struct clk_init_data clk_lcd_init = {
578 .parent_names = dmn_clk_parents,
579 .num_parents = ARRAY_SIZE(dmn_clk_parents),
582 static struct clk_dmn clk_lcd = {
583 .regofs = SIRFSOC_CLKC_LCD_CFG,
586 .init = &clk_lcd_init,
590 static struct clk_init_data clk_vpp_init = {
593 .parent_names = dmn_clk_parents,
594 .num_parents = ARRAY_SIZE(dmn_clk_parents),
597 static struct clk_dmn clk_vpp = {
598 .regofs = SIRFSOC_CLKC_LCD_CFG,
601 .init = &clk_vpp_init,
605 static struct clk_init_data clk_mmc01_init = {
608 .parent_names = dmn_clk_parents,
609 .num_parents = ARRAY_SIZE(dmn_clk_parents),
612 static struct clk_init_data clk_mmc23_init = {
615 .parent_names = dmn_clk_parents,
616 .num_parents = ARRAY_SIZE(dmn_clk_parents),
619 static struct clk_init_data clk_mmc45_init = {
622 .parent_names = dmn_clk_parents,
623 .num_parents = ARRAY_SIZE(dmn_clk_parents),
627 * peripheral controllers in io domain
630 static int std_clk_is_enabled(struct clk_hw *hw)
634 struct clk_std *clk = to_stdclk(hw);
636 bit = clk->enable_bit % 32;
637 reg = clk->enable_bit / 32;
638 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
640 return !!(clkc_readl(reg) & BIT(bit));
643 static int std_clk_enable(struct clk_hw *hw)
647 struct clk_std *clk = to_stdclk(hw);
649 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
651 bit = clk->enable_bit % 32;
652 reg = clk->enable_bit / 32;
653 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
655 val = clkc_readl(reg) | BIT(bit);
656 clkc_writel(val, reg);
660 static void std_clk_disable(struct clk_hw *hw)
664 struct clk_std *clk = to_stdclk(hw);
666 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
668 bit = clk->enable_bit % 32;
669 reg = clk->enable_bit / 32;
670 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
672 val = clkc_readl(reg) & ~BIT(bit);
673 clkc_writel(val, reg);
676 static const char * const std_clk_io_parents[] = {
680 static struct clk_ops ios_ops = {
681 .is_enabled = std_clk_is_enabled,
682 .enable = std_clk_enable,
683 .disable = std_clk_disable,
686 static struct clk_init_data clk_cphif_init = {
689 .parent_names = std_clk_io_parents,
690 .num_parents = ARRAY_SIZE(std_clk_io_parents),
693 static struct clk_std clk_cphif = {
696 .init = &clk_cphif_init,
700 static struct clk_init_data clk_dmac0_init = {
703 .parent_names = std_clk_io_parents,
704 .num_parents = ARRAY_SIZE(std_clk_io_parents),
707 static struct clk_std clk_dmac0 = {
710 .init = &clk_dmac0_init,
714 static struct clk_init_data clk_dmac1_init = {
717 .parent_names = std_clk_io_parents,
718 .num_parents = ARRAY_SIZE(std_clk_io_parents),
721 static struct clk_std clk_dmac1 = {
724 .init = &clk_dmac1_init,
728 static struct clk_init_data clk_audio_init = {
731 .parent_names = std_clk_io_parents,
732 .num_parents = ARRAY_SIZE(std_clk_io_parents),
735 static struct clk_std clk_audio = {
738 .init = &clk_audio_init,
742 static struct clk_init_data clk_uart0_init = {
745 .parent_names = std_clk_io_parents,
746 .num_parents = ARRAY_SIZE(std_clk_io_parents),
749 static struct clk_std clk_uart0 = {
752 .init = &clk_uart0_init,
756 static struct clk_init_data clk_uart1_init = {
759 .parent_names = std_clk_io_parents,
760 .num_parents = ARRAY_SIZE(std_clk_io_parents),
763 static struct clk_std clk_uart1 = {
766 .init = &clk_uart1_init,
770 static struct clk_init_data clk_uart2_init = {
773 .parent_names = std_clk_io_parents,
774 .num_parents = ARRAY_SIZE(std_clk_io_parents),
777 static struct clk_std clk_uart2 = {
780 .init = &clk_uart2_init,
784 static struct clk_init_data clk_usp0_init = {
787 .parent_names = std_clk_io_parents,
788 .num_parents = ARRAY_SIZE(std_clk_io_parents),
791 static struct clk_std clk_usp0 = {
794 .init = &clk_usp0_init,
798 static struct clk_init_data clk_usp1_init = {
801 .parent_names = std_clk_io_parents,
802 .num_parents = ARRAY_SIZE(std_clk_io_parents),
805 static struct clk_std clk_usp1 = {
808 .init = &clk_usp1_init,
812 static struct clk_init_data clk_usp2_init = {
815 .parent_names = std_clk_io_parents,
816 .num_parents = ARRAY_SIZE(std_clk_io_parents),
819 static struct clk_std clk_usp2 = {
822 .init = &clk_usp2_init,
826 static struct clk_init_data clk_vip_init = {
829 .parent_names = std_clk_io_parents,
830 .num_parents = ARRAY_SIZE(std_clk_io_parents),
833 static struct clk_std clk_vip = {
836 .init = &clk_vip_init,
840 static struct clk_init_data clk_spi0_init = {
843 .parent_names = std_clk_io_parents,
844 .num_parents = ARRAY_SIZE(std_clk_io_parents),
847 static struct clk_std clk_spi0 = {
850 .init = &clk_spi0_init,
854 static struct clk_init_data clk_spi1_init = {
857 .parent_names = std_clk_io_parents,
858 .num_parents = ARRAY_SIZE(std_clk_io_parents),
861 static struct clk_std clk_spi1 = {
864 .init = &clk_spi1_init,
868 static struct clk_init_data clk_tsc_init = {
871 .parent_names = std_clk_io_parents,
872 .num_parents = ARRAY_SIZE(std_clk_io_parents),
875 static struct clk_std clk_tsc = {
878 .init = &clk_tsc_init,
882 static struct clk_init_data clk_i2c0_init = {
885 .parent_names = std_clk_io_parents,
886 .num_parents = ARRAY_SIZE(std_clk_io_parents),
889 static struct clk_std clk_i2c0 = {
892 .init = &clk_i2c0_init,
896 static struct clk_init_data clk_i2c1_init = {
899 .parent_names = std_clk_io_parents,
900 .num_parents = ARRAY_SIZE(std_clk_io_parents),
903 static struct clk_std clk_i2c1 = {
906 .init = &clk_i2c1_init,
910 static struct clk_init_data clk_pwmc_init = {
913 .parent_names = std_clk_io_parents,
914 .num_parents = ARRAY_SIZE(std_clk_io_parents),
917 static struct clk_std clk_pwmc = {
920 .init = &clk_pwmc_init,
924 static struct clk_init_data clk_efuse_init = {
927 .parent_names = std_clk_io_parents,
928 .num_parents = ARRAY_SIZE(std_clk_io_parents),
931 static struct clk_std clk_efuse = {
934 .init = &clk_efuse_init,
938 static struct clk_init_data clk_pulse_init = {
941 .parent_names = std_clk_io_parents,
942 .num_parents = ARRAY_SIZE(std_clk_io_parents),
945 static struct clk_std clk_pulse = {
948 .init = &clk_pulse_init,
952 static const char * const std_clk_dsp_parents[] = {
956 static struct clk_init_data clk_gps_init = {
959 .parent_names = std_clk_dsp_parents,
960 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
963 static struct clk_std clk_gps = {
966 .init = &clk_gps_init,
970 static struct clk_init_data clk_mf_init = {
973 .parent_names = std_clk_io_parents,
974 .num_parents = ARRAY_SIZE(std_clk_io_parents),
977 static struct clk_std clk_mf = {
980 .init = &clk_mf_init,
984 static const char * const std_clk_sys_parents[] = {
988 static struct clk_init_data clk_security_init = {
991 .parent_names = std_clk_sys_parents,
992 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
995 static struct clk_std clk_security = {
998 .init = &clk_security_init,
1002 static const char * const std_clk_usb_parents[] = {
1006 static struct clk_init_data clk_usb0_init = {
1009 .parent_names = std_clk_usb_parents,
1010 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1013 static struct clk_std clk_usb0 = {
1016 .init = &clk_usb0_init,
1020 static struct clk_init_data clk_usb1_init = {
1023 .parent_names = std_clk_usb_parents,
1024 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1027 static struct clk_std clk_usb1 = {
1030 .init = &clk_usb1_init,