drivers/clk/samsung/clk-pll.h

   1 /*
   2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   3  * Copyright (c) 2013 Linaro Ltd.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for all PLL's in Samsung platforms
  10 */
  11
  12 #ifndef __SAMSUNG_CLK_PLL_H
  13 #define __SAMSUNG_CLK_PLL_H
  14
  15 enum samsung_pll_type {
  16         pll_2126,
  17         pll_3000,
  18         pll_35xx,
  19         pll_36xx,
  20         pll_2550,
  21         pll_2650,
  22         pll_4500,
  23         pll_4502,
  24         pll_4508,
  25         pll_4600,
  26         pll_4650,
  27         pll_4650c,
  28         pll_6552,
  29         pll_6552_s3c2416,
  30         pll_6553,
  31         pll_s3c2410_mpll,
  32         pll_s3c2410_upll,
  33         pll_s3c2440_mpll,
  34 };
  35
  36 #define PLL_35XX_RATE(_rate, _m, _p, _s)                        \
  37         {                                                       \
  38                 .rate   =       (_rate),                                \
  39                 .mdiv   =       (_m),                           \
  40                 .pdiv   =       (_p),                           \
  41                 .sdiv   =       (_s),                           \
  42         }
  43
  44 #define PLL_36XX_RATE(_rate, _m, _p, _s, _k)                    \
  45         {                                                       \
  46                 .rate   =       (_rate),                                \
  47                 .mdiv   =       (_m),                           \
  48                 .pdiv   =       (_p),                           \
  49                 .sdiv   =       (_s),                           \
  50                 .kdiv   =       (_k),                           \
  51         }
  52
  53 #define PLL_45XX_RATE(_rate, _m, _p, _s, _afc)                  \
  54         {                                                       \
  55                 .rate   =       (_rate),                        \
  56                 .mdiv   =       (_m),                           \
  57                 .pdiv   =       (_p),                           \
  58                 .sdiv   =       (_s),                           \
  59                 .afc    =       (_afc),                         \
  60         }
  61
  62 #define PLL_4600_RATE(_rate, _m, _p, _s, _k, _vsel)             \
  63         {                                                       \
  64                 .rate   =       (_rate),                        \
  65                 .mdiv   =       (_m),                           \
  66                 .pdiv   =       (_p),                           \
  67                 .sdiv   =       (_s),                           \
  68                 .kdiv   =       (_k),                           \
  69                 .vsel   =       (_vsel),                        \
  70         }
  71
  72 #define PLL_4650_RATE(_rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \
  73         {                                                       \
  74                 .rate   =       (_rate),                        \
  75                 .mdiv   =       (_m),                           \
  76                 .pdiv   =       (_p),                           \
  77                 .sdiv   =       (_s),                           \
  78                 .kdiv   =       (_k),                           \
  79                 .mfr    =       (_mfr),                         \
  80                 .mrr    =       (_mrr),                         \
  81                 .vsel   =       (_vsel),                        \
  82         }
  83
  84 /* NOTE: Rate table should be kept sorted in descending order. */
  85
  86 struct samsung_pll_rate_table {
  87         unsigned int rate;
  88         unsigned int pdiv;
  89         unsigned int mdiv;
  90         unsigned int sdiv;
  91         unsigned int kdiv;
  92         unsigned int afc;
  93         unsigned int mfr;
  94         unsigned int mrr;
  95         unsigned int vsel;
  96 };
  97
  98 extern struct clk * __init samsung_clk_register_pll2550x(const char *name,
  99                         const char *pname, const void __iomem *reg_base,
 100                         const unsigned long offset);
 101
 102 #endif /* __SAMSUNG_CLK_PLL_H */