drivers/clk/samsung/clk-exynos5433.c

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Common Clock Framework support for Exynos5443 SoC.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clkdev.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/of.h>
  16
  17 #include <dt-bindings/clock/exynos5433.h>
  18
  19 #include "clk.h"
  20 #include "clk-pll.h"
  21
  22 /*
  23  * Register offset definitions for CMU_TOP
  24  */
  25 #define ISP_PLL_LOCK                    0x0000
  26 #define AUD_PLL_LOCK                    0x0004
  27 #define ISP_PLL_CON0                    0x0100
  28 #define ISP_PLL_CON1                    0x0104
  29 #define ISP_PLL_FREQ_DET                0x0108
  30 #define AUD_PLL_CON0                    0x0110
  31 #define AUD_PLL_CON1                    0x0114
  32 #define AUD_PLL_CON2                    0x0118
  33 #define AUD_PLL_FREQ_DET                0x011c
  34 #define MUX_SEL_TOP0                    0x0200
  35 #define MUX_SEL_TOP1                    0x0204
  36 #define MUX_SEL_TOP2                    0x0208
  37 #define MUX_SEL_TOP3                    0x020c
  38 #define MUX_SEL_TOP4                    0x0210
  39 #define MUX_SEL_TOP_MSCL                0x0220
  40 #define MUX_SEL_TOP_CAM1                0x0224
  41 #define MUX_SEL_TOP_DISP                0x0228
  42 #define MUX_SEL_TOP_FSYS0               0x0230
  43 #define MUX_SEL_TOP_FSYS1               0x0234
  44 #define MUX_SEL_TOP_PERIC0              0x0238
  45 #define MUX_SEL_TOP_PERIC1              0x023c
  46 #define MUX_ENABLE_TOP0                 0x0300
  47 #define MUX_ENABLE_TOP1                 0x0304
  48 #define MUX_ENABLE_TOP2                 0x0308
  49 #define MUX_ENABLE_TOP3                 0x030c
  50 #define MUX_ENABLE_TOP4                 0x0310
  51 #define MUX_ENABLE_TOP_MSCL             0x0320
  52 #define MUX_ENABLE_TOP_CAM1             0x0324
  53 #define MUX_ENABLE_TOP_DISP             0x0328
  54 #define MUX_ENABLE_TOP_FSYS0            0x0330
  55 #define MUX_ENABLE_TOP_FSYS1            0x0334
  56 #define MUX_ENABLE_TOP_PERIC0           0x0338
  57 #define MUX_ENABLE_TOP_PERIC1           0x033c
  58 #define MUX_STAT_TOP0                   0x0400
  59 #define MUX_STAT_TOP1                   0x0404
  60 #define MUX_STAT_TOP2                   0x0408
  61 #define MUX_STAT_TOP3                   0x040c
  62 #define MUX_STAT_TOP4                   0x0410
  63 #define MUX_STAT_TOP_MSCL               0x0420
  64 #define MUX_STAT_TOP_CAM1               0x0424
  65 #define MUX_STAT_TOP_FSYS0              0x0430
  66 #define MUX_STAT_TOP_FSYS1              0x0434
  67 #define MUX_STAT_TOP_PERIC0             0x0438
  68 #define MUX_STAT_TOP_PERIC1             0x043c
  69 #define DIV_TOP0                        0x0600
  70 #define DIV_TOP1                        0x0604
  71 #define DIV_TOP2                        0x0608
  72 #define DIV_TOP3                        0x060c
  73 #define DIV_TOP4                        0x0610
  74 #define DIV_TOP_MSCL                    0x0618
  75 #define DIV_TOP_CAM10                   0x061c
  76 #define DIV_TOP_CAM11                   0x0620
  77 #define DIV_TOP_FSYS0                   0x062c
  78 #define DIV_TOP_FSYS1                   0x0630
  79 #define DIV_TOP_FSYS2                   0x0634
  80 #define DIV_TOP_PERIC0                  0x0638
  81 #define DIV_TOP_PERIC1                  0x063c
  82 #define DIV_TOP_PERIC2                  0x0640
  83 #define DIV_TOP_PERIC3                  0x0644
  84 #define DIV_TOP_PERIC4                  0x0648
  85 #define DIV_TOP_PLL_FREQ_DET            0x064c
  86 #define DIV_STAT_TOP0                   0x0700
  87 #define DIV_STAT_TOP1                   0x0704
  88 #define DIV_STAT_TOP2                   0x0708
  89 #define DIV_STAT_TOP3                   0x070c
  90 #define DIV_STAT_TOP4                   0x0710
  91 #define DIV_STAT_TOP_MSCL               0x0718
  92 #define DIV_STAT_TOP_CAM10              0x071c
  93 #define DIV_STAT_TOP_CAM11              0x0720
  94 #define DIV_STAT_TOP_FSYS0              0x072c
  95 #define DIV_STAT_TOP_FSYS1              0x0730
  96 #define DIV_STAT_TOP_FSYS2              0x0734
  97 #define DIV_STAT_TOP_PERIC0             0x0738
  98 #define DIV_STAT_TOP_PERIC1             0x073c
  99 #define DIV_STAT_TOP_PERIC2             0x0740
 100 #define DIV_STAT_TOP_PERIC3             0x0744
 101 #define DIV_STAT_TOP_PLL_FREQ_DET       0x074c
 102 #define ENABLE_ACLK_TOP                 0x0800
 103 #define ENABLE_SCLK_TOP                 0x0a00
 104 #define ENABLE_SCLK_TOP_MSCL            0x0a04
 105 #define ENABLE_SCLK_TOP_CAM1            0x0a08
 106 #define ENABLE_SCLK_TOP_DISP            0x0a0c
 107 #define ENABLE_SCLK_TOP_FSYS            0x0a10
 108 #define ENABLE_SCLK_TOP_PERIC           0x0a14
 109 #define ENABLE_IP_TOP                   0x0b00
 110 #define ENABLE_CMU_TOP                  0x0c00
 111 #define ENABLE_CMU_TOP_DIV_STAT         0x0c04
 112
 113 static unsigned long top_clk_regs[] __initdata = {
 114         ISP_PLL_LOCK,
 115         AUD_PLL_LOCK,
 116         ISP_PLL_CON0,
 117         ISP_PLL_CON1,
 118         ISP_PLL_FREQ_DET,
 119         AUD_PLL_CON0,
 120         AUD_PLL_CON1,
 121         AUD_PLL_CON2,
 122         AUD_PLL_FREQ_DET,
 123         MUX_SEL_TOP0,
 124         MUX_SEL_TOP1,
 125         MUX_SEL_TOP2,
 126         MUX_SEL_TOP3,
 127         MUX_SEL_TOP4,
 128         MUX_SEL_TOP_MSCL,
 129         MUX_SEL_TOP_CAM1,
 130         MUX_SEL_TOP_DISP,
 131         MUX_SEL_TOP_FSYS0,
 132         MUX_SEL_TOP_FSYS1,
 133         MUX_SEL_TOP_PERIC0,
 134         MUX_SEL_TOP_PERIC1,
 135         MUX_ENABLE_TOP0,
 136         MUX_ENABLE_TOP1,
 137         MUX_ENABLE_TOP2,
 138         MUX_ENABLE_TOP3,
 139         MUX_ENABLE_TOP4,
 140         MUX_ENABLE_TOP_MSCL,
 141         MUX_ENABLE_TOP_CAM1,
 142         MUX_ENABLE_TOP_DISP,
 143         MUX_ENABLE_TOP_FSYS0,
 144         MUX_ENABLE_TOP_FSYS1,
 145         MUX_ENABLE_TOP_PERIC0,
 146         MUX_ENABLE_TOP_PERIC1,
 147         MUX_STAT_TOP0,
 148         MUX_STAT_TOP1,
 149         MUX_STAT_TOP2,
 150         MUX_STAT_TOP3,
 151         MUX_STAT_TOP4,
 152         MUX_STAT_TOP_MSCL,
 153         MUX_STAT_TOP_CAM1,
 154         MUX_STAT_TOP_FSYS0,
 155         MUX_STAT_TOP_FSYS1,
 156         MUX_STAT_TOP_PERIC0,
 157         MUX_STAT_TOP_PERIC1,
 158         DIV_TOP0,
 159         DIV_TOP1,
 160         DIV_TOP2,
 161         DIV_TOP3,
 162         DIV_TOP4,
 163         DIV_TOP_MSCL,
 164         DIV_TOP_CAM10,
 165         DIV_TOP_CAM11,
 166         DIV_TOP_FSYS0,
 167         DIV_TOP_FSYS1,
 168         DIV_TOP_FSYS2,
 169         DIV_TOP_PERIC0,
 170         DIV_TOP_PERIC1,
 171         DIV_TOP_PERIC2,
 172         DIV_TOP_PERIC3,
 173         DIV_TOP_PERIC4,
 174         DIV_TOP_PLL_FREQ_DET,
 175         DIV_STAT_TOP0,
 176         DIV_STAT_TOP1,
 177         DIV_STAT_TOP2,
 178         DIV_STAT_TOP3,
 179         DIV_STAT_TOP4,
 180         DIV_STAT_TOP_MSCL,
 181         DIV_STAT_TOP_CAM10,
 182         DIV_STAT_TOP_CAM11,
 183         DIV_STAT_TOP_FSYS0,
 184         DIV_STAT_TOP_FSYS1,
 185         DIV_STAT_TOP_FSYS2,
 186         DIV_STAT_TOP_PERIC0,
 187         DIV_STAT_TOP_PERIC1,
 188         DIV_STAT_TOP_PERIC2,
 189         DIV_STAT_TOP_PERIC3,
 190         DIV_STAT_TOP_PLL_FREQ_DET,
 191         ENABLE_ACLK_TOP,
 192         ENABLE_SCLK_TOP,
 193         ENABLE_SCLK_TOP_MSCL,
 194         ENABLE_SCLK_TOP_CAM1,
 195         ENABLE_SCLK_TOP_DISP,
 196         ENABLE_SCLK_TOP_FSYS,
 197         ENABLE_SCLK_TOP_PERIC,
 198         ENABLE_IP_TOP,
 199         ENABLE_CMU_TOP,
 200         ENABLE_CMU_TOP_DIV_STAT,
 201 };
 202
 203 /* list of all parent clock list */
 204 PNAME(mout_aud_pll_p)           = { "oscclk", "fout_aud_pll", };
 205 PNAME(mout_isp_pll_p)           = { "oscclk", "fout_isp_pll", };
 206 PNAME(mout_aud_pll_user_p)      = { "oscclk", "mout_aud_pll", };
 207 PNAME(mout_mphy_pll_user_p)     = { "oscclk", "sclk_mphy_pll", };
 208 PNAME(mout_mfc_pll_user_p)      = { "oscclk", "sclk_mfc_pll", };
 209 PNAME(mout_bus_pll_user_p)      = { "oscclk", "sclk_bus_pll", };
 210 PNAME(mout_bus_pll_user_t_p)    = { "oscclk", "mout_bus_pll_user", };
 211 PNAME(mout_mphy_pll_user_t_p)   = { "oscclk", "mout_mphy_pll_user", };
 212
 213 PNAME(mout_bus_mfc_pll_user_p)  = { "mout_bus_pll_user", "mout_mfc_pll_user",};
 214 PNAME(mout_mfc_bus_pll_user_p)  = { "mout_mfc_pll_user", "mout_bus_pll_user",};
 215 PNAME(mout_aclk_cam1_552_b_p)   = { "mout_aclk_cam1_552_a",
 216                                     "mout_mfc_pll_user", };
 217 PNAME(mout_aclk_cam1_552_a_p)   = { "mout_isp_pll", "mout_bus_pll_user", };
 218
 219 PNAME(mout_aclk_mfc_400_c_p)    = { "mout_aclk_mfc_400_b",
 220                                     "mout_mphy_pll_user", };
 221 PNAME(mout_aclk_mfc_400_b_p)    = { "mout_aclk_mfc_400_a",
 222                                     "mout_bus_pll_user", };
 223 PNAME(mout_aclk_mfc_400_a_p)    = { "mout_mfc_pll_user", "mout_isp_pll", };
 224
 225 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
 226                                     "mout_mphy_pll_user", };
 227 PNAME(mout_aclk_mscl_b_p)       = { "mout_aclk_mscl_400_a",
 228                                     "mout_mphy_pll_user", };
 229 PNAME(mout_aclk_g2d_400_b_p)    = { "mout_aclk_g2d_400_a",
 230                                     "mout_mphy_pll_user", };
 231
 232 PNAME(mout_sclk_jpeg_c_p)       = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
 233 PNAME(mout_sclk_jpeg_b_p)       = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
 234
 235 PNAME(mout_sclk_mmc2_b_p)       = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
 236 PNAME(mout_sclk_mmc1_b_p)       = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
 237 PNAME(mout_sclk_mmc0_d_p)       = { "mout_sclk_mmc0_c", "mout_isp_pll", };
 238 PNAME(mout_sclk_mmc0_c_p)       = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
 239 PNAME(mout_sclk_mmc0_b_p)       = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
 240
 241 PNAME(mout_sclk_spdif_p)        = { "sclk_audio0", "sclk_audio1",
 242                                     "oscclk", "ioclk_spdif_extclk", };
 243 PNAME(mout_sclk_audio1_p)       = { "ioclk_audiocdclk1", "oscclk",
 244                                     "mout_aud_pll_user_t",};
 245 PNAME(mout_sclk_audio0_p)       = { "ioclk_audiocdclk0", "oscclk",
 246                                     "mout_aud_pll_user_t",};
 247
 248 static struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initdata = {
 249         FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
 250 };
 251
 252 static struct samsung_fixed_rate_clock top_fixed_clks[] __initdata = {
 253         /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
 254         FRATE(0, "ioclk_audiocdclk1", NULL, CLK_IS_ROOT, 100000000),
 255         FRATE(0, "ioclk_audiocdclk0", NULL, CLK_IS_ROOT, 100000000),
 256         /* Xi2s1SDI input clock for SPDIF */
 257         FRATE(0, "ioclk_spdif_extclk", NULL, CLK_IS_ROOT, 100000000),
 258         /* XspiCLK[4:0] input clock for SPI */
 259         FRATE(0, "ioclk_spi4_clk_in", NULL, CLK_IS_ROOT, 50000000),
 260         FRATE(0, "ioclk_spi3_clk_in", NULL, CLK_IS_ROOT, 50000000),
 261         FRATE(0, "ioclk_spi2_clk_in", NULL, CLK_IS_ROOT, 50000000),
 262         FRATE(0, "ioclk_spi1_clk_in", NULL, CLK_IS_ROOT, 50000000),
 263         FRATE(0, "ioclk_spi0_clk_in", NULL, CLK_IS_ROOT, 50000000),
 264         /* Xi2s1SCLK input clock for I2S1_BCLK */
 265         FRATE(0, "ioclk_i2s1_bclk_in", NULL, CLK_IS_ROOT, 12288000),
 266 };
 267
 268 static struct samsung_mux_clock top_mux_clks[] __initdata = {
 269         /* MUX_SEL_TOP0 */
 270         MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
 271                         4, 1),
 272         MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
 273                         0, 1),
 274
 275         /* MUX_SEL_TOP1 */
 276         MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
 277                         mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
 278         MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
 279                         MUX_SEL_TOP1, 8, 1),
 280         MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
 281                         MUX_SEL_TOP1, 4, 1),
 282         MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
 283                         MUX_SEL_TOP1, 0, 1),
 284
 285         /* MUX_SEL_TOP2 */
 286         MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
 287                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
 288         MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
 289                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
 290         MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
 291                         mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
 292         MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
 293                         mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
 294         MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
 295                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
 296         MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
 297                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
 298
 299         /* MUX_SEL_TOP3 */
 300         MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
 301                         mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
 302         MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
 303                         mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
 304         MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
 305                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
 306         MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
 307                         mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
 308         MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
 309                         mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
 310         MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
 311                         mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
 312
 313         /* MUX_SEL_TOP4 */
 314         MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
 315                         mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
 316         MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
 317                         mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
 318         MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
 319                         mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
 320
 321         /* MUX_SEL_TOP_MSCL */
 322         MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
 323                         MUX_SEL_TOP_MSCL, 8, 1),
 324         MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
 325                         MUX_SEL_TOP_MSCL, 4, 1),
 326         MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
 327                         MUX_SEL_TOP_MSCL, 0, 1),
 328
 329         /* MUX_SEL_TOP_CAM1 */
 330         MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
 331                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
 332         MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
 333                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
 334         MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
 335                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
 336         MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
 337                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
 338         MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
 339                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
 340         MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
 341                         mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
 342
 343         /* MUX_SEL_TOP_FSYS0 */
 344         MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
 345                         MUX_SEL_TOP_FSYS0, 28, 1),
 346         MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
 347                         MUX_SEL_TOP_FSYS0, 24, 1),
 348         MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
 349                         MUX_SEL_TOP_FSYS0, 20, 1),
 350         MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
 351                         MUX_SEL_TOP_FSYS0, 16, 1),
 352         MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
 353                         MUX_SEL_TOP_FSYS0, 12, 1),
 354         MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
 355                         MUX_SEL_TOP_FSYS0, 8, 1),
 356         MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
 357                         MUX_SEL_TOP_FSYS0, 4, 1),
 358         MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
 359                         MUX_SEL_TOP_FSYS0, 0, 1),
 360
 361         /* MUX_SEL_TOP_FSYS1 */
 362         MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
 363                         MUX_SEL_TOP_FSYS1, 12, 1),
 364         MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
 365                         mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
 366         MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
 367                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
 368         MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
 369                         mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
 370
 371         /* MUX_SEL_TOP_PERIC0 */
 372         MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
 373                         MUX_SEL_TOP_PERIC0, 28, 1),
 374         MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
 375                         MUX_SEL_TOP_PERIC0, 24, 1),
 376         MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
 377                         MUX_SEL_TOP_PERIC0, 20, 1),
 378         MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
 379                         MUX_SEL_TOP_PERIC0, 16, 1),
 380         MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
 381                         MUX_SEL_TOP_PERIC0, 12, 1),
 382         MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
 383                         MUX_SEL_TOP_PERIC0, 8, 1),
 384         MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
 385                         MUX_SEL_TOP_PERIC0, 4, 1),
 386         MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
 387                         MUX_SEL_TOP_PERIC0, 0, 1),
 388
 389         /* MUX_SEL_TOP_PERIC1 */
 390         MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
 391                         MUX_SEL_TOP_PERIC1, 16, 1),
 392         MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
 393                         MUX_SEL_TOP_PERIC1, 12, 2),
 394         MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
 395                         MUX_SEL_TOP_PERIC1, 4, 2),
 396         MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
 397                         MUX_SEL_TOP_PERIC1, 0, 2),
 398 };
 399
 400 static struct samsung_div_clock top_div_clks[] __initdata = {
 401         /* DIV_TOP1 */
 402         DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
 403                         DIV_TOP1, 28, 3),
 404         DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
 405                         DIV_TOP1, 24, 3),
 406         DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
 407                         DIV_TOP1, 20, 3),
 408         DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
 409                         DIV_TOP1, 12, 3),
 410         DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
 411                         DIV_TOP1, 8, 3),
 412         DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
 413                         DIV_TOP1, 0, 3),
 414
 415         /* DIV_TOP2 */
 416         DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
 417                         DIV_TOP2, 0, 3),
 418
 419         /* DIV_TOP3 */
 420         DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
 421                         "mout_bus_pll_user", DIV_TOP3, 24, 3),
 422         DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
 423                         "mout_bus_pll_user", DIV_TOP3, 20, 3),
 424         DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
 425                         "mout_bus_pll_user", DIV_TOP3, 16, 3),
 426         DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
 427                         "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
 428         DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
 429                         "mout_bus_pll_user", DIV_TOP3, 8, 3),
 430         DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
 431                         "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
 432         DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
 433                         "mout_bus_pll_user", DIV_TOP3, 0, 3),
 434
 435         /* DIV_TOP_FSYS0 */
 436         DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
 437                         DIV_TOP_FSYS0, 16, 8),
 438         DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
 439                         DIV_TOP_FSYS0, 12, 4),
 440         DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
 441                         DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
 442         DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
 443                         DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
 444
 445         /* DIV_TOP_FSYS1 */
 446         DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
 447                         DIV_TOP_FSYS1, 4, 8),
 448         DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
 449                         DIV_TOP_FSYS1, 0, 4),
 450
 451         /* DIV_TOP_PERIC0 */
 452         DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
 453                         DIV_TOP_PERIC0, 16, 8),
 454         DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
 455                         DIV_TOP_PERIC0, 12, 4),
 456         DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
 457                         DIV_TOP_PERIC0, 4, 8),
 458         DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
 459                         DIV_TOP_PERIC0, 0, 4),
 460
 461         /* DIV_TOP_PERIC1 */
 462         DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
 463                         DIV_TOP_PERIC1, 4, 8),
 464         DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
 465                         DIV_TOP_PERIC1, 0, 4),
 466
 467         /* DIV_TOP_PERIC2 */
 468         DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
 469                         DIV_TOP_PERIC2, 8, 4),
 470         DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
 471                         DIV_TOP_PERIC2, 4, 4),
 472         DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
 473                         DIV_TOP_PERIC2, 0, 4),
 474
 475         /* DIV_TOP_PERIC3 */
 476         DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
 477                         DIV_TOP_PERIC3, 16, 6),
 478         DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
 479                         DIV_TOP_PERIC3, 8, 8),
 480         DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
 481                         DIV_TOP_PERIC3, 4, 4),
 482         DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
 483                         DIV_TOP_PERIC3, 0, 4),
 484
 485         /* DIV_TOP_PERIC4 */
 486         DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
 487                         DIV_TOP_PERIC4, 16, 8),
 488         DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
 489                         DIV_TOP_PERIC4, 12, 4),
 490         DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
 491                         DIV_TOP_PERIC4, 4, 8),
 492         DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
 493                         DIV_TOP_PERIC4, 0, 4),
 494 };
 495
 496 static struct samsung_gate_clock top_gate_clks[] __initdata = {
 497         /* ENABLE_ACLK_TOP */
 498         GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
 499                         ENABLE_ACLK_TOP, 22,
 500                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 501         GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
 502                         ENABLE_ACLK_TOP, 21,
 503                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 504         GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
 505                         ENABLE_ACLK_TOP, 18,
 506                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 507         GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
 508                         ENABLE_ACLK_TOP, 2,
 509                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 510         GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
 511                         ENABLE_ACLK_TOP, 0,
 512                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
 513
 514         /* ENABLE_SCLK_TOP_FSYS */
 515         GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
 516                         ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
 517         GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
 518                         ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
 519         GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
 520                         ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
 521
 522         /* ENABLE_SCLK_TOP_PERIC */
 523         GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
 524                         ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
 525         GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
 526                         ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
 527         GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
 528                         ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
 529         GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
 530                         ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
 531         GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
 532                         ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
 533         GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
 534                         ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT, 0),
 535         GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
 536                         ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT, 0),
 537         GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
 538                         ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT, 0),
 539         GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
 540                         ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
 541         GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
 542                         ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
 543         GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
 544                         ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
 545
 546         /* MUX_ENABLE_TOP_PERIC1 */
 547         GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
 548                         MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
 549         GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
 550                         MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
 551         GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
 552                         MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
 553 };
 554
 555 /*
 556  * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
 557  * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
 558  */
 559 static struct samsung_pll_rate_table exynos5443_pll_rates[] = {
 560         PLL_35XX_RATE(2500000000U, 625, 6,  0),
 561         PLL_35XX_RATE(2400000000U, 500, 5,  0),
 562         PLL_35XX_RATE(2300000000U, 575, 6,  0),
 563         PLL_35XX_RATE(2200000000U, 550, 6,  0),
 564         PLL_35XX_RATE(2100000000U, 350, 4,  0),
 565         PLL_35XX_RATE(2000000000U, 500, 6,  0),
 566         PLL_35XX_RATE(1900000000U, 475, 6,  0),
 567         PLL_35XX_RATE(1800000000U, 375, 5,  0),
 568         PLL_35XX_RATE(1700000000U, 425, 6,  0),
 569         PLL_35XX_RATE(1600000000U, 400, 6,  0),
 570         PLL_35XX_RATE(1500000000U, 250, 4,  0),
 571         PLL_35XX_RATE(1400000000U, 350, 6,  0),
 572         PLL_35XX_RATE(1332000000U, 222, 4,  0),
 573         PLL_35XX_RATE(1300000000U, 325, 6,  0),
 574         PLL_35XX_RATE(1200000000U, 500, 5,  1),
 575         PLL_35XX_RATE(1100000000U, 550, 6,  1),
 576         PLL_35XX_RATE(1086000000U, 362, 4,  1),
 577         PLL_35XX_RATE(1066000000U, 533, 6,  1),
 578         PLL_35XX_RATE(1000000000U, 500, 6,  1),
 579         PLL_35XX_RATE(933000000U,  311, 4,  1),
 580         PLL_35XX_RATE(921000000U,  307, 4,  1),
 581         PLL_35XX_RATE(900000000U,  375, 5,  1),
 582         PLL_35XX_RATE(825000000U,  275, 4,  1),
 583         PLL_35XX_RATE(800000000U,  400, 6,  1),
 584         PLL_35XX_RATE(733000000U,  733, 12, 1),
 585         PLL_35XX_RATE(700000000U,  360, 6,  1),
 586         PLL_35XX_RATE(667000000U,  222, 4,  1),
 587         PLL_35XX_RATE(633000000U,  211, 4,  1),
 588         PLL_35XX_RATE(600000000U,  500, 5,  2),
 589         PLL_35XX_RATE(552000000U,  460, 5,  2),
 590         PLL_35XX_RATE(550000000U,  550, 6,  2),
 591         PLL_35XX_RATE(543000000U,  362, 4,  2),
 592         PLL_35XX_RATE(533000000U,  533, 6,  2),
 593         PLL_35XX_RATE(500000000U,  500, 6,  2),
 594         PLL_35XX_RATE(444000000U,  370, 5,  2),
 595         PLL_35XX_RATE(420000000U,  350, 5,  2),
 596         PLL_35XX_RATE(400000000U,  400, 6,  2),
 597         PLL_35XX_RATE(350000000U,  360, 6,  2),
 598         PLL_35XX_RATE(333000000U,  222, 4,  2),
 599         PLL_35XX_RATE(300000000U,  500, 5,  3),
 600         PLL_35XX_RATE(266000000U,  532, 6,  3),
 601         PLL_35XX_RATE(200000000U,  400, 6,  3),
 602         PLL_35XX_RATE(166000000U,  332, 6,  3),
 603         PLL_35XX_RATE(160000000U,  320, 6,  3),
 604         PLL_35XX_RATE(133000000U,  552, 6,  4),
 605         PLL_35XX_RATE(100000000U,  400, 6,  4),
 606         { /* sentinel */ }
 607 };
 608
 609 /* AUD_PLL */
 610 static struct samsung_pll_rate_table exynos5443_aud_pll_rates[] = {
 611         PLL_36XX_RATE(400000000U, 200, 3, 2,      0),
 612         PLL_36XX_RATE(393216000U, 197, 3, 2, -25690),
 613         PLL_36XX_RATE(384000000U, 128, 2, 2,      0),
 614         PLL_36XX_RATE(368640000U, 246, 4, 2, -15729),
 615         PLL_36XX_RATE(361507200U, 181, 3, 2, -16148),
 616         PLL_36XX_RATE(338688000U, 113, 2, 2,  -6816),
 617         PLL_36XX_RATE(294912000U,  98, 1, 3,  19923),
 618         PLL_36XX_RATE(288000000U,  96, 1, 3,      0),
 619         PLL_36XX_RATE(252000000U,  84, 1, 3,      0),
 620         { /* sentinel */ }
 621 };
 622
 623 static struct samsung_pll_clock top_pll_clks[] __initdata = {
 624         PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
 625                 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates),
 626         PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
 627                 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates),
 628 };
 629
 630 static struct samsung_cmu_info top_cmu_info __initdata = {
 631         .pll_clks               = top_pll_clks,
 632         .nr_pll_clks            = ARRAY_SIZE(top_pll_clks),
 633         .mux_clks               = top_mux_clks,
 634         .nr_mux_clks            = ARRAY_SIZE(top_mux_clks),
 635         .div_clks               = top_div_clks,
 636         .nr_div_clks            = ARRAY_SIZE(top_div_clks),
 637         .gate_clks              = top_gate_clks,
 638         .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
 639         .fixed_clks             = top_fixed_clks,
 640         .nr_fixed_clks          = ARRAY_SIZE(top_fixed_clks),
 641         .fixed_factor_clks      = top_fixed_factor_clks,
 642         .nr_fixed_factor_clks   = ARRAY_SIZE(top_fixed_factor_clks),
 643         .nr_clk_ids             = TOP_NR_CLK,
 644         .clk_regs               = top_clk_regs,
 645         .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
 646 };
 647
 648 static void __init exynos5433_cmu_top_init(struct device_node *np)
 649 {
 650         samsung_cmu_register_one(np, &top_cmu_info);
 651 }
 652 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
 653                 exynos5433_cmu_top_init);
 654
 655 /*
 656  * Register offset definitions for CMU_CPIF
 657  */
 658 #define MPHY_PLL_LOCK           0x0000
 659 #define MPHY_PLL_CON0           0x0100
 660 #define MPHY_PLL_CON1           0x0104
 661 #define MPHY_PLL_FREQ_DET       0x010c
 662 #define MUX_SEL_CPIF0           0x0200
 663 #define DIV_CPIF                0x0600
 664 #define ENABLE_SCLK_CPIF        0x0a00
 665
 666 static unsigned long cpif_clk_regs[] __initdata = {
 667         MPHY_PLL_LOCK,
 668         MPHY_PLL_CON0,
 669         MPHY_PLL_CON1,
 670         MPHY_PLL_FREQ_DET,
 671         MUX_SEL_CPIF0,
 672         ENABLE_SCLK_CPIF,
 673 };
 674
 675 /* list of all parent clock list */
 676 PNAME(mout_mphy_pll_p)          = { "oscclk", "fout_mphy_pll", };
 677
 678 static struct samsung_pll_clock cpif_pll_clks[] __initdata = {
 679         PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
 680                 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates),
 681 };
 682
 683 static struct samsung_mux_clock cpif_mux_clks[] __initdata = {
 684         /* MUX_SEL_CPIF0 */
 685         MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
 686                         0, 1),
 687 };
 688
 689 static struct samsung_div_clock cpif_div_clks[] __initdata = {
 690         /* DIV_CPIF */
 691         DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
 692                         0, 6),
 693 };
 694
 695 static struct samsung_gate_clock cpif_gate_clks[] __initdata = {
 696         /* ENABLE_SCLK_CPIF */
 697         GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
 698                         ENABLE_SCLK_CPIF, 9, 0, 0),
 699         GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
 700                         ENABLE_SCLK_CPIF, 4, 0, 0),
 701 };
 702
 703 static struct samsung_cmu_info cpif_cmu_info __initdata = {
 704         .pll_clks               = cpif_pll_clks,
 705         .nr_pll_clks            = ARRAY_SIZE(cpif_pll_clks),
 706         .mux_clks               = cpif_mux_clks,
 707         .nr_mux_clks            = ARRAY_SIZE(cpif_mux_clks),
 708         .div_clks               = cpif_div_clks,
 709         .nr_div_clks            = ARRAY_SIZE(cpif_div_clks),
 710         .gate_clks              = cpif_gate_clks,
 711         .nr_gate_clks           = ARRAY_SIZE(cpif_gate_clks),
 712         .nr_clk_ids             = CPIF_NR_CLK,
 713         .clk_regs               = cpif_clk_regs,
 714         .nr_clk_regs            = ARRAY_SIZE(cpif_clk_regs),
 715 };
 716
 717 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
 718 {
 719         samsung_cmu_register_one(np, &cpif_cmu_info);
 720 }
 721 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
 722                 exynos5433_cmu_cpif_init);
 723
 724 /*
 725  * Register offset definitions for CMU_MIF
 726  */
 727 #define MEM0_PLL_LOCK                   0x0000
 728 #define MEM1_PLL_LOCK                   0x0004
 729 #define BUS_PLL_LOCK                    0x0008
 730 #define MFC_PLL_LOCK                    0x000c
 731 #define MEM0_PLL_CON0                   0x0100
 732 #define MEM0_PLL_CON1                   0x0104
 733 #define MEM0_PLL_FREQ_DET               0x010c
 734 #define MEM1_PLL_CON0                   0x0110
 735 #define MEM1_PLL_CON1                   0x0114
 736 #define MEM1_PLL_FREQ_DET               0x011c
 737 #define BUS_PLL_CON0                    0x0120
 738 #define BUS_PLL_CON1                    0x0124
 739 #define BUS_PLL_FREQ_DET                0x012c
 740 #define MFC_PLL_CON0                    0x0130
 741 #define MFC_PLL_CON1                    0x0134
 742 #define MFC_PLL_FREQ_DET                0x013c
 743 #define MUX_SEL_MIF0                    0x0200
 744 #define MUX_SEL_MIF1                    0x0204
 745 #define MUX_SEL_MIF2                    0x0208
 746 #define MUX_SEL_MIF3                    0x020c
 747 #define MUX_SEL_MIF4                    0x0210
 748 #define MUX_SEL_MIF5                    0x0214
 749 #define MUX_SEL_MIF6                    0x0218
 750 #define MUX_SEL_MIF7                    0x021c
 751 #define MUX_ENABLE_MIF0                 0x0300
 752 #define MUX_ENABLE_MIF1                 0x0304
 753 #define MUX_ENABLE_MIF2                 0x0308
 754 #define MUX_ENABLE_MIF3                 0x030c
 755 #define MUX_ENABLE_MIF4                 0x0310
 756 #define MUX_ENABLE_MIF5                 0x0314
 757 #define MUX_ENABLE_MIF6                 0x0318
 758 #define MUX_ENABLE_MIF7                 0x031c
 759 #define MUX_STAT_MIF0                   0x0400
 760 #define MUX_STAT_MIF1                   0x0404
 761 #define MUX_STAT_MIF2                   0x0408
 762 #define MUX_STAT_MIF3                   0x040c
 763 #define MUX_STAT_MIF4                   0x0410
 764 #define MUX_STAT_MIF5                   0x0414
 765 #define MUX_STAT_MIF6                   0x0418
 766 #define MUX_STAT_MIF7                   0x041c
 767 #define DIV_MIF1                        0x0604
 768 #define DIV_MIF2                        0x0608
 769 #define DIV_MIF3                        0x060c
 770 #define DIV_MIF4                        0x0610
 771 #define DIV_MIF5                        0x0614
 772 #define DIV_MIF_PLL_FREQ_DET            0x0618
 773 #define DIV_STAT_MIF1                   0x0704
 774 #define DIV_STAT_MIF2                   0x0708
 775 #define DIV_STAT_MIF3                   0x070c
 776 #define DIV_STAT_MIF4                   0x0710
 777 #define DIV_STAT_MIF5                   0x0714
 778 #define DIV_STAT_MIF_PLL_FREQ_DET       0x0718
 779 #define ENABLE_ACLK_MIF0                0x0800
 780 #define ENABLE_ACLK_MIF1                0x0804
 781 #define ENABLE_ACLK_MIF2                0x0808
 782 #define ENABLE_ACLK_MIF3                0x080c
 783 #define ENABLE_PCLK_MIF                 0x0900
 784 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
 785 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
 786 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT    0x090c
 787 #define ENABLE_PCLK_MIF_SECURE_RTC      0x0910
 788 #define ENABLE_SCLK_MIF                 0x0a00
 789 #define ENABLE_IP_MIF0                  0x0b00
 790 #define ENABLE_IP_MIF1                  0x0b04
 791 #define ENABLE_IP_MIF2                  0x0b08
 792 #define ENABLE_IP_MIF3                  0x0b0c
 793 #define ENABLE_IP_MIF_SECURE_DREX0_TZ   0x0b10
 794 #define ENABLE_IP_MIF_SECURE_DREX1_TZ   0x0b14
 795 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT      0x0b18
 796 #define ENABLE_IP_MIF_SECURE_RTC        0x0b1c
 797 #define CLKOUT_CMU_MIF                  0x0c00
 798 #define CLKOUT_CMU_MIF_DIV_STAT         0x0c04
 799 #define DREX_FREQ_CTRL0                 0x1000
 800 #define DREX_FREQ_CTRL1                 0x1004
 801 #define PAUSE                           0x1008
 802 #define DDRPHY_LOCK_CTRL                0x100c
 803
 804 static unsigned long mif_clk_regs[] __initdata = {
 805         MEM0_PLL_LOCK,
 806         MEM1_PLL_LOCK,
 807         BUS_PLL_LOCK,
 808         MFC_PLL_LOCK,
 809         MEM0_PLL_CON0,
 810         MEM0_PLL_CON1,
 811         MEM0_PLL_FREQ_DET,
 812         MEM1_PLL_CON0,
 813         MEM1_PLL_CON1,
 814         MEM1_PLL_FREQ_DET,
 815         BUS_PLL_CON0,
 816         BUS_PLL_CON1,
 817         BUS_PLL_FREQ_DET,
 818         MFC_PLL_CON0,
 819         MFC_PLL_CON1,
 820         MFC_PLL_FREQ_DET,
 821         MUX_SEL_MIF0,
 822         MUX_SEL_MIF1,
 823         MUX_SEL_MIF2,
 824         MUX_SEL_MIF3,
 825         MUX_SEL_MIF4,
 826         MUX_SEL_MIF5,
 827         MUX_SEL_MIF6,
 828         MUX_SEL_MIF7,
 829         MUX_ENABLE_MIF0,
 830         MUX_ENABLE_MIF1,
 831         MUX_ENABLE_MIF2,
 832         MUX_ENABLE_MIF3,
 833         MUX_ENABLE_MIF4,
 834         MUX_ENABLE_MIF5,
 835         MUX_ENABLE_MIF6,
 836         MUX_ENABLE_MIF7,
 837         MUX_STAT_MIF0,
 838         MUX_STAT_MIF1,
 839         MUX_STAT_MIF2,
 840         MUX_STAT_MIF3,
 841         MUX_STAT_MIF4,
 842         MUX_STAT_MIF5,
 843         MUX_STAT_MIF6,
 844         MUX_STAT_MIF7,
 845         DIV_MIF1,
 846         DIV_MIF2,
 847         DIV_MIF3,
 848         DIV_MIF4,
 849         DIV_MIF5,
 850         DIV_MIF_PLL_FREQ_DET,
 851         DIV_STAT_MIF1,
 852         DIV_STAT_MIF2,
 853         DIV_STAT_MIF3,
 854         DIV_STAT_MIF4,
 855         DIV_STAT_MIF5,
 856         DIV_STAT_MIF_PLL_FREQ_DET,
 857         ENABLE_ACLK_MIF0,
 858         ENABLE_ACLK_MIF1,
 859         ENABLE_ACLK_MIF2,
 860         ENABLE_ACLK_MIF3,
 861         ENABLE_PCLK_MIF,
 862         ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
 863         ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
 864         ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
 865         ENABLE_PCLK_MIF_SECURE_RTC,
 866         ENABLE_SCLK_MIF,
 867         ENABLE_IP_MIF0,
 868         ENABLE_IP_MIF1,
 869         ENABLE_IP_MIF2,
 870         ENABLE_IP_MIF3,
 871         ENABLE_IP_MIF_SECURE_DREX0_TZ,
 872         ENABLE_IP_MIF_SECURE_DREX1_TZ,
 873         ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
 874         ENABLE_IP_MIF_SECURE_RTC,
 875         CLKOUT_CMU_MIF,
 876         CLKOUT_CMU_MIF_DIV_STAT,
 877         DREX_FREQ_CTRL0,
 878         DREX_FREQ_CTRL1,
 879         PAUSE,
 880         DDRPHY_LOCK_CTRL,
 881 };
 882
 883 static struct samsung_pll_clock mif_pll_clks[] __initdata = {
 884         PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
 885                 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates),
 886         PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
 887                 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates),
 888         PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
 889                 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates),
 890         PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
 891                 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates),
 892 };
 893
 894 /* list of all parent clock list */
 895 PNAME(mout_mfc_pll_div2_p)      = { "mout_mfc_pll", "dout_mfc_pll", };
 896 PNAME(mout_bus_pll_div2_p)      = { "mout_bus_pll", "dout_bus_pll", };
 897 PNAME(mout_mem1_pll_div2_p)     = { "mout_mem1_pll", "dout_mem1_pll", };
 898 PNAME(mout_mem0_pll_div2_p)     = { "mout_mem0_pll", "dout_mem0_pll", };
 899 PNAME(mout_mfc_pll_p)           = { "oscclk", "fout_mfc_pll", };
 900 PNAME(mout_bus_pll_p)           = { "oscclk", "fout_bus_pll", };
 901 PNAME(mout_mem1_pll_p)          = { "oscclk", "fout_mem1_pll", };
 902 PNAME(mout_mem0_pll_p)          = { "oscclk", "fout_mem0_pll", };
 903
 904 PNAME(mout_clk2x_phy_c_p)       = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
 905 PNAME(mout_clk2x_phy_b_p)       = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
 906 PNAME(mout_clk2x_phy_a_p)       = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
 907 PNAME(mout_clkm_phy_b_p)        = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
 908
 909 PNAME(mout_aclk_mifnm_200_p)    = { "mout_mem0_pll_div2", "div_mif_pre", };
 910 PNAME(mout_aclk_mifnm_400_p)    = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
 911
 912 PNAME(mout_aclk_disp_333_b_p)   = { "mout_aclk_disp_333_a",
 913                                     "mout_bus_pll_div2", };
 914 PNAME(mout_aclk_disp_333_a_p)   = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
 915
 916 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
 917                                     "sclk_mphy_pll", };
 918 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
 919                                     "mout_mfc_pll_div2", };
 920 PNAME(mout_sclk_decon_p)        = { "oscclk", "mout_bus_pll_div2", };
 921 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
 922                                     "sclk_mphy_pll", };
 923 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
 924                                     "mout_mfc_pll_div2", };
 925
 926 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
 927                                        "sclk_mphy_pll", };
 928 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
 929                                        "mout_mfc_pll_div2", };
 930 PNAME(mout_sclk_dsd_c_p)        = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
 931 PNAME(mout_sclk_dsd_b_p)        = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
 932 PNAME(mout_sclk_dsd_a_p)        = { "oscclk", "mout_mfc_pll_div2", };
 933
 934 PNAME(mout_sclk_dsim0_c_p)      = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
 935 PNAME(mout_sclk_dsim0_b_p)      = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
 936
 937 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
 938                                        "sclk_mphy_pll", };
 939 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
 940                                        "mout_mfc_pll_div2", };
 941 PNAME(mout_sclk_dsim1_c_p)      = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
 942 PNAME(mout_sclk_dsim1_b_p)      = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
 943
 944 static struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initdata = {
 945         /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
 946         FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
 947         FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
 948         FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
 949         FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
 950 };
 951
 952 static struct samsung_mux_clock mif_mux_clks[] __initdata = {
 953         /* MUX_SEL_MIF0 */
 954         MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
 955                         MUX_SEL_MIF0, 28, 1),
 956         MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
 957                         MUX_SEL_MIF0, 24, 1),
 958         MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
 959                         MUX_SEL_MIF0, 20, 1),
 960         MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
 961                         MUX_SEL_MIF0, 16, 1),
 962         MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
 963                         12, 1),
 964         MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
 965                         8, 1),
 966         MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
 967                         4, 1),
 968         MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
 969                         0, 1),
 970
 971         /* MUX_SEL_MIF1 */
 972         MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
 973                         MUX_SEL_MIF1, 24, 1),
 974         MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
 975                         MUX_SEL_MIF1, 20, 1),
 976         MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
 977                         MUX_SEL_MIF1, 16, 1),
 978         MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
 979                         MUX_SEL_MIF1, 12, 1),
 980         MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
 981                         MUX_SEL_MIF1, 8, 1),
 982         MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
 983                         MUX_SEL_MIF1, 4, 1),
 984
 985         /* MUX_SEL_MIF2 */
 986         MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
 987                         mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
 988         MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
 989                         mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
 990
 991         /* MUX_SEL_MIF3 */
 992         MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
 993                         mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
 994         MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
 995                         mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
 996
 997         /* MUX_SEL_MIF4 */
 998         MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
 999                         mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1000         MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1001                         mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1002         MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1003                         mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1004         MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1005                         mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1006         MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1007                         mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1008         MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1009                         mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1010
1011         /* MUX_SEL_MIF5 */
1012         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1013                         mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1014         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1015                         mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1016         MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1017                         mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1018         MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1019                         MUX_SEL_MIF5, 8, 1),
1020         MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1021                         MUX_SEL_MIF5, 4, 1),
1022         MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1023                         MUX_SEL_MIF5, 0, 1),
1024
1025         /* MUX_SEL_MIF6 */
1026         MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1027                         MUX_SEL_MIF6, 8, 1),
1028         MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1029                         MUX_SEL_MIF6, 4, 1),
1030         MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1031                         MUX_SEL_MIF6, 0, 1),
1032
1033         /* MUX_SEL_MIF7 */
1034         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1035                         mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1036         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1037                         mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1038         MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1039                         mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1040         MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1041                         MUX_SEL_MIF7, 8, 1),
1042         MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1043                         MUX_SEL_MIF7, 4, 1),
1044         MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1045                         MUX_SEL_MIF7, 0, 1),
1046 };
1047
1048 static struct samsung_div_clock mif_div_clks[] __initdata = {
1049         /* DIV_MIF1 */
1050         DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1051                         DIV_MIF1, 16, 2),
1052         DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1053                         12, 2),
1054         DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1055                         8, 2),
1056         DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1057                         4, 4),
1058
1059         /* DIV_MIF2 */
1060         DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1061                         DIV_MIF2, 20, 3),
1062         DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1063                         DIV_MIF2, 16, 4),
1064         DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1065                         DIV_MIF2, 12, 4),
1066         DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1067                         "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1068         DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1069                         DIV_MIF2, 4, 2),
1070         DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1071                         DIV_MIF2, 0, 3),
1072
1073         /* DIV_MIF3 */
1074         DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1075                         DIV_MIF3, 16, 4),
1076         DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1077                         DIV_MIF3, 4, 3),
1078         DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1079                         DIV_MIF3, 0, 3),
1080
1081         /* DIV_MIF4 */
1082         DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1083                         DIV_MIF4, 24, 4),
1084         DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1085                         "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1086         DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1087                         DIV_MIF4, 16, 4),
1088         DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1089                         DIV_MIF4, 12, 4),
1090         DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1091                         "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1092         DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1093                         "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1094         DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1095                         "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1096
1097         /* DIV_MIF5 */
1098         DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1099                         0, 3),
1100 };
1101
1102 static struct samsung_gate_clock mif_gate_clks[] __initdata = {
1103         /* ENABLE_ACLK_MIF0 */
1104         GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1105                         19, CLK_IGNORE_UNUSED, 0),
1106         GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1107                         18, CLK_IGNORE_UNUSED, 0),
1108         GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1109                         17, CLK_IGNORE_UNUSED, 0),
1110         GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1111                         16, CLK_IGNORE_UNUSED, 0),
1112         GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1113                         15, CLK_IGNORE_UNUSED, 0),
1114         GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1115                         14, CLK_IGNORE_UNUSED, 0),
1116         GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1117                         ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1118         GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1119                         ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1120         GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1121                         ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1122         GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1123                         ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1124         GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1125                         ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1126         GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1127                         ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1128         GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1129                         ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1130         GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1131                         ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1132         GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1133                         ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1134         GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1135                         ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1136         GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1137                         ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1138         GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1139                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1140         GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1141                         ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1142         GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1143                         ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1144
1145         /* ENABLE_ACLK_MIF1 */
1146         GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1147                         "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1148                         CLK_IGNORE_UNUSED, 0),
1149         GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1150                         "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1151                         27, CLK_IGNORE_UNUSED, 0),
1152         GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1153                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1154                         26, CLK_IGNORE_UNUSED, 0),
1155         GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1156                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1157                         25, CLK_IGNORE_UNUSED, 0),
1158         GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1159                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1160                         24, CLK_IGNORE_UNUSED, 0),
1161         GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1162                         "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1163                         23, CLK_IGNORE_UNUSED, 0),
1164         GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1165                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1166                         22, CLK_IGNORE_UNUSED, 0),
1167         GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1168                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1169                         21, CLK_IGNORE_UNUSED, 0),
1170         GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1171                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1172                         20, CLK_IGNORE_UNUSED, 0),
1173         GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1174                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1175                         19, CLK_IGNORE_UNUSED, 0),
1176         GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1177                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1178                         18, CLK_IGNORE_UNUSED, 0),
1179         GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1180                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1181                         17, CLK_IGNORE_UNUSED, 0),
1182         GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1183                         "div_aclk_drex1", ENABLE_ACLK_MIF1,
1184                         16, CLK_IGNORE_UNUSED, 0),
1185         GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1186                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1187                         15, CLK_IGNORE_UNUSED, 0),
1188         GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1189                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1190                         14, CLK_IGNORE_UNUSED, 0),
1191         GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1192                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1193                         13, CLK_IGNORE_UNUSED, 0),
1194         GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1195                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1196                         12, CLK_IGNORE_UNUSED, 0),
1197         GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1198                         "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1199                         11, CLK_IGNORE_UNUSED, 0),
1200         GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1201                         "div_aclk_drex0", ENABLE_ACLK_MIF1,
1202                         10, CLK_IGNORE_UNUSED, 0),
1203         GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1204                         ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1205         GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1206                         ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1207         GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1208                         ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1209         GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1210                         ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1211         GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1212                         ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1213         GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1214                         ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1215         GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1216                         ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1217         GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1218                         ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1219         GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1220                         ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1221         GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1222                         0, CLK_IGNORE_UNUSED, 0),
1223
1224         /* ENABLE_ACLK_MIF2 */
1225         GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1226                         ENABLE_ACLK_MIF2, 20, 0, 0),
1227         GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1228                         ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1229         GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1230                         ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1231         GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1232                         ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1233         GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1234                         ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1235         GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1236                         ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1237         GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1238                         ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1239         GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1240                         "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1241                         CLK_IGNORE_UNUSED, 0),
1242         GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1243                         "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1244                         5, CLK_IGNORE_UNUSED, 0),
1245         GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1246                         ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1247         GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1248                         "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1249                         3, CLK_IGNORE_UNUSED, 0),
1250         GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1251                         "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1252
1253         /* ENABLE_ACLK_MIF3 */
1254         GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1255                         ENABLE_ACLK_MIF3, 4,
1256                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1257         GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1258                         ENABLE_ACLK_MIF3, 1,
1259                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1260         GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1261                         ENABLE_ACLK_MIF3, 0,
1262                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1263
1264         /* ENABLE_PCLK_MIF */
1265         GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1266                         ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1267         GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1268                         ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1269         GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1270                         ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1271         GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1272                         ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1273         GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1274                         ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1275         GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1276                         ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1277         GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1278                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1279                         CLK_IGNORE_UNUSED, 0),
1280         GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1281                         ENABLE_PCLK_MIF, 19, 0, 0),
1282         GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1283                         ENABLE_PCLK_MIF, 18, 0, 0),
1284         GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1285                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1286         GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1287                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1288         GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1289                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1290         GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1291                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1292         GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1293                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1294         GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1295                         "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1296         GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1297                         ENABLE_PCLK_MIF, 11, 0, 0),
1298         GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1299                         ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1300         GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1301                         ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1302         GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1303                         ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1304         GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1305                         ENABLE_PCLK_MIF, 7, 0, 0),
1306         GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1307                         ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1308         GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1309                         ENABLE_PCLK_MIF, 5, 0, 0),
1310         GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1311                         ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1312         GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1313                         ENABLE_PCLK_MIF, 2, 0, 0),
1314         GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1315                         ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1316
1317         /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1318         GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1319                         ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 0, 0),
1320
1321         /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1322         GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1323                         ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 0, 0),
1324
1325         /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1326         GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1327                         ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1328
1329         /* ENABLE_PCLK_MIF_SECURE_RTC */
1330         GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1331                         ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1332
1333         /* ENABLE_SCLK_MIF */
1334         GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1335                         ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1336         GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1337                         "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1338                         14, CLK_IGNORE_UNUSED, 0),
1339         GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1340                         ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1341         GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1342                         ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1343         GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1344                         "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1345                         7, CLK_IGNORE_UNUSED, 0),
1346         GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1347                         "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1348                         6, CLK_IGNORE_UNUSED, 0),
1349         GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1350                         "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1351                         5, CLK_IGNORE_UNUSED, 0),
1352         GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1353                         ENABLE_SCLK_MIF, 4,
1354                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1355         GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1356                         ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1357         GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1358                         ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1359         GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1360                         ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1361         GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1362                         ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1363 };
1364
1365 static struct samsung_cmu_info mif_cmu_info __initdata = {
1366         .pll_clks               = mif_pll_clks,
1367         .nr_pll_clks            = ARRAY_SIZE(mif_pll_clks),
1368         .mux_clks               = mif_mux_clks,
1369         .nr_mux_clks            = ARRAY_SIZE(mif_mux_clks),
1370         .div_clks               = mif_div_clks,
1371         .nr_div_clks            = ARRAY_SIZE(mif_div_clks),
1372         .gate_clks              = mif_gate_clks,
1373         .nr_gate_clks           = ARRAY_SIZE(mif_gate_clks),
1374         .fixed_factor_clks      = mif_fixed_factor_clks,
1375         .nr_fixed_factor_clks   = ARRAY_SIZE(mif_fixed_factor_clks),
1376         .nr_clk_ids             = MIF_NR_CLK,
1377         .clk_regs               = mif_clk_regs,
1378         .nr_clk_regs            = ARRAY_SIZE(mif_clk_regs),
1379 };
1380
1381 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1382 {
1383         samsung_cmu_register_one(np, &mif_cmu_info);
1384 }
1385 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1386                 exynos5433_cmu_mif_init);
1387
1388 /*
1389  * Register offset definitions for CMU_PERIC
1390  */
1391 #define DIV_PERIC                       0x0600
1392 #define DIV_STAT_PERIC                  0x0700
1393 #define ENABLE_ACLK_PERIC               0x0800
1394 #define ENABLE_PCLK_PERIC0              0x0900
1395 #define ENABLE_PCLK_PERIC1              0x0904
1396 #define ENABLE_SCLK_PERIC               0x0A00
1397 #define ENABLE_IP_PERIC0                0x0B00
1398 #define ENABLE_IP_PERIC1                0x0B04
1399 #define ENABLE_IP_PERIC2                0x0B08
1400
1401 static unsigned long peric_clk_regs[] __initdata = {
1402         DIV_PERIC,
1403         DIV_STAT_PERIC,
1404         ENABLE_ACLK_PERIC,
1405         ENABLE_PCLK_PERIC0,
1406         ENABLE_PCLK_PERIC1,
1407         ENABLE_SCLK_PERIC,
1408         ENABLE_IP_PERIC0,
1409         ENABLE_IP_PERIC1,
1410         ENABLE_IP_PERIC2,
1411 };
1412
1413 static struct samsung_div_clock peric_div_clks[] __initdata = {
1414         /* DIV_PERIC */
1415         DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1416         DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1417 };
1418
1419 static struct samsung_gate_clock peric_gate_clks[] __initdata = {
1420         /* ENABLE_ACLK_PERIC */
1421         GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1422                         ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1423         GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1424                         ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1425         GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1426                         ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1427         GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1428                         ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1429
1430         /* ENABLE_PCLK_PERIC0 */
1431         GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1432                         31, CLK_SET_RATE_PARENT, 0),
1433         GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1434                         ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1435         GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1436                         ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1437         GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1438                         28, CLK_SET_RATE_PARENT, 0),
1439         GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1440                         26, CLK_SET_RATE_PARENT, 0),
1441         GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1442                         25, CLK_SET_RATE_PARENT, 0),
1443         GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1444                         24, CLK_SET_RATE_PARENT, 0),
1445         GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1446                         23, CLK_SET_RATE_PARENT, 0),
1447         GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1448                         22, CLK_SET_RATE_PARENT, 0),
1449         GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1450                         21, CLK_SET_RATE_PARENT, 0),
1451         GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1452                         20, CLK_SET_RATE_PARENT, 0),
1453         GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1454                         ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1455         GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1456                         ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1457         GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1458                         ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1459         GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1460                         ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1461         GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1462                         ENABLE_PCLK_PERIC0, 15,
1463                         CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1464         GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1465                         14, CLK_SET_RATE_PARENT, 0),
1466         GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1467                         13, CLK_SET_RATE_PARENT, 0),
1468         GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1469                         12, CLK_SET_RATE_PARENT, 0),
1470         GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1471                         ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1472         GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1473                         ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1474         GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1475                         ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1476         GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1477                         ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1478         GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1479                         7, CLK_SET_RATE_PARENT, 0),
1480         GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1481                         6, CLK_SET_RATE_PARENT, 0),
1482         GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1483                         5, CLK_SET_RATE_PARENT, 0),
1484         GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1485                         4, CLK_SET_RATE_PARENT, 0),
1486         GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1487                         3, CLK_SET_RATE_PARENT, 0),
1488         GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1489                         2, CLK_SET_RATE_PARENT, 0),
1490         GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1491                         1, CLK_SET_RATE_PARENT, 0),
1492         GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1493                         0, CLK_SET_RATE_PARENT, 0),
1494
1495         /* ENABLE_PCLK_PERIC1 */
1496         GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1497                         9, CLK_SET_RATE_PARENT, 0),
1498         GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1499                         8, CLK_SET_RATE_PARENT, 0),
1500         GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1501                         ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1502         GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1503                         ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1504         GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1505                         ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1506         GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1507                         ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1508         GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1509                         ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1510         GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1511                         ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1512         GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1513                         ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1514         GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1515                         ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1516
1517         /* ENABLE_SCLK_PERIC */
1518         GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1519                         ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1520         GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1521                         ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1522         GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1523                         19, CLK_SET_RATE_PARENT, 0),
1524         GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1525                         18, CLK_SET_RATE_PARENT, 0),
1526         GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1527                         17, 0, 0),
1528         GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1529                         16, 0, 0),
1530         GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1531         GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1532                         ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1533         GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1534                         ENABLE_SCLK_PERIC, 12,
1535                         CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1536         GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1537                         ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1538         GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1539                         "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1540                         CLK_SET_RATE_PARENT, 0),
1541         GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1542                         ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1543         GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1544                         ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1545         GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1546                         ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1547         GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1548                         5, CLK_SET_RATE_PARENT, 0),
1549         GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1550                         4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1551         GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1552                         3, CLK_SET_RATE_PARENT, 0),
1553         GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1554                         ENABLE_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1555         GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1556                         ENABLE_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1557         GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1558                         ENABLE_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1559 };
1560
1561 static struct samsung_cmu_info peric_cmu_info __initdata = {
1562         .div_clks               = peric_div_clks,
1563         .nr_div_clks            = ARRAY_SIZE(peric_div_clks),
1564         .gate_clks              = peric_gate_clks,
1565         .nr_gate_clks           = ARRAY_SIZE(peric_gate_clks),
1566         .nr_clk_ids             = PERIC_NR_CLK,
1567         .clk_regs               = peric_clk_regs,
1568         .nr_clk_regs            = ARRAY_SIZE(peric_clk_regs),
1569 };
1570
1571 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1572 {
1573         samsung_cmu_register_one(np, &peric_cmu_info);
1574 }
1575
1576 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1577                 exynos5433_cmu_peric_init);
1578
1579 /*
1580  * Register offset definitions for CMU_PERIS
1581  */
1582 #define ENABLE_ACLK_PERIS                               0x0800
1583 #define ENABLE_PCLK_PERIS                               0x0900
1584 #define ENABLE_PCLK_PERIS_SECURE_TZPC                   0x0904
1585 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF           0x0908
1586 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF           0x090c
1587 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC                 0x0910
1588 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF     0x0914
1589 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF      0x0918
1590 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF          0x091c
1591 #define ENABLE_SCLK_PERIS                               0x0a00
1592 #define ENABLE_SCLK_PERIS_SECURE_SECKEY                 0x0a04
1593 #define ENABLE_SCLK_PERIS_SECURE_CHIPID                 0x0a08
1594 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC                 0x0a0c
1595 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE           0x0a10
1596 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT            0x0a14
1597 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON                0x0a18
1598 #define ENABLE_IP_PERIS0                                0x0b00
1599 #define ENABLE_IP_PERIS1                                0x0b04
1600 #define ENABLE_IP_PERIS_SECURE_TZPC                     0x0b08
1601 #define ENABLE_IP_PERIS_SECURE_SECKEY                   0x0b0c
1602 #define ENABLE_IP_PERIS_SECURE_CHIPID                   0x0b10
1603 #define ENABLE_IP_PERIS_SECURE_TOPRTC                   0x0b14
1604 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE             0x0b18
1605 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT              0x0b1c
1606 #define ENABLE_IP_PERIS_SECURE_OTP_CON                  0x0b20
1607
1608 static unsigned long peris_clk_regs[] __initdata = {
1609         ENABLE_ACLK_PERIS,
1610         ENABLE_PCLK_PERIS,
1611         ENABLE_PCLK_PERIS_SECURE_TZPC,
1612         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1613         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1614         ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1615         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1616         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1617         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1618         ENABLE_SCLK_PERIS,
1619         ENABLE_SCLK_PERIS_SECURE_SECKEY,
1620         ENABLE_SCLK_PERIS_SECURE_CHIPID,
1621         ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1622         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1623         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1624         ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1625         ENABLE_IP_PERIS0,
1626         ENABLE_IP_PERIS1,
1627         ENABLE_IP_PERIS_SECURE_TZPC,
1628         ENABLE_IP_PERIS_SECURE_SECKEY,
1629         ENABLE_IP_PERIS_SECURE_CHIPID,
1630         ENABLE_IP_PERIS_SECURE_TOPRTC,
1631         ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1632         ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1633         ENABLE_IP_PERIS_SECURE_OTP_CON,
1634 };
1635
1636 static struct samsung_gate_clock peris_gate_clks[] __initdata = {
1637         /* ENABLE_ACLK_PERIS */
1638         GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1639                         ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1640         GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1641                         ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1642         GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1643                         ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1644
1645         /* ENABLE_PCLK_PERIS */
1646         GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1647                         ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1648         GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1649                         ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1650         GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1651                         ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1652         GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1653                         ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1654         GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1655                         ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1656         GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1657                         ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1658         GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1659                         ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1660         GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1661                         ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1662         GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1663                         ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1664         GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1665                         ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1666
1667         /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1668         GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1669                         ENABLE_PCLK_PERIS_SECURE_TZPC, 12, 0, 0),
1670         GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1671                         ENABLE_PCLK_PERIS_SECURE_TZPC, 11, 0, 0),
1672         GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1673                         ENABLE_PCLK_PERIS_SECURE_TZPC, 10, 0, 0),
1674         GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1675                         ENABLE_PCLK_PERIS_SECURE_TZPC, 9, 0, 0),
1676         GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1677                         ENABLE_PCLK_PERIS_SECURE_TZPC, 8, 0, 0),
1678         GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1679                         ENABLE_PCLK_PERIS_SECURE_TZPC, 7, 0, 0),
1680         GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1681                         ENABLE_PCLK_PERIS_SECURE_TZPC, 6, 0, 0),
1682         GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1683                         ENABLE_PCLK_PERIS_SECURE_TZPC, 5, 0, 0),
1684         GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1685                         ENABLE_PCLK_PERIS_SECURE_TZPC, 4, 0, 0),
1686         GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1687                         ENABLE_PCLK_PERIS_SECURE_TZPC, 3, 0, 0),
1688         GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1689                         ENABLE_PCLK_PERIS_SECURE_TZPC, 2, 0, 0),
1690         GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1691                         ENABLE_PCLK_PERIS_SECURE_TZPC, 1, 0, 0),
1692         GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1693                         ENABLE_PCLK_PERIS_SECURE_TZPC, 0, 0, 0),
1694
1695         /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1696         GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1697                         ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, 0, 0),
1698
1699         /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1700         GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1701                         ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, 0, 0),
1702
1703         /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1704         GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1705                         ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1706
1707         /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1708         GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1709                         "aclk_peris_66",
1710                         ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1711
1712         /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1713         GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1714                         "aclk_peris_66",
1715                         ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1716
1717         /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1718         GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1719                         "aclk_peris_66",
1720                         ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1721
1722         /* ENABLE_SCLK_PERIS */
1723         GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1724                         ENABLE_SCLK_PERIS, 10, 0, 0),
1725         GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1726                         ENABLE_SCLK_PERIS, 4, 0, 0),
1727         GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1728                         ENABLE_SCLK_PERIS, 3, 0, 0),
1729
1730         /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1731         GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1732                         ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, 0, 0),
1733
1734         /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1735         GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1736                         ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
1737
1738         /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1739         GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1740                         ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1741
1742         /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1743         GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1744                         ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1745
1746         /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1747         GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1748                         ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1749
1750         /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1751         GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1752                         ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1753 };
1754
1755 static struct samsung_cmu_info peris_cmu_info __initdata = {
1756         .gate_clks              = peris_gate_clks,
1757         .nr_gate_clks           = ARRAY_SIZE(peris_gate_clks),
1758         .nr_clk_ids             = PERIS_NR_CLK,
1759         .clk_regs               = peris_clk_regs,
1760         .nr_clk_regs            = ARRAY_SIZE(peris_clk_regs),
1761 };
1762
1763 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1764 {
1765         samsung_cmu_register_one(np, &peris_cmu_info);
1766 }
1767
1768 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1769                 exynos5433_cmu_peris_init);
1770
1771 /*
1772  * Register offset definitions for CMU_FSYS
1773  */
1774 #define MUX_SEL_FSYS0                   0x0200
1775 #define MUX_SEL_FSYS1                   0x0204
1776 #define MUX_SEL_FSYS2                   0x0208
1777 #define MUX_SEL_FSYS3                   0x020c
1778 #define MUX_SEL_FSYS4                   0x0210
1779 #define MUX_ENABLE_FSYS0                0x0300
1780 #define MUX_ENABLE_FSYS1                0x0304
1781 #define MUX_ENABLE_FSYS2                0x0308
1782 #define MUX_ENABLE_FSYS3                0x030c
1783 #define MUX_ENABLE_FSYS4                0x0310
1784 #define MUX_STAT_FSYS0                  0x0400
1785 #define MUX_STAT_FSYS1                  0x0404
1786 #define MUX_STAT_FSYS2                  0x0408
1787 #define MUX_STAT_FSYS3                  0x040c
1788 #define MUX_STAT_FSYS4                  0x0410
1789 #define MUX_IGNORE_FSYS2                0x0508
1790 #define MUX_IGNORE_FSYS3                0x050c
1791 #define ENABLE_ACLK_FSYS0               0x0800
1792 #define ENABLE_ACLK_FSYS1               0x0804
1793 #define ENABLE_PCLK_FSYS                0x0900
1794 #define ENABLE_SCLK_FSYS                0x0a00
1795 #define ENABLE_IP_FSYS0                 0x0b00
1796 #define ENABLE_IP_FSYS1                 0x0b04
1797
1798 /* list of all parent clock list */
1799 PNAME(mout_aclk_fsys_200_user_p)        = { "oscclk", "div_aclk_fsys_200", };
1800 PNAME(mout_sclk_mmc2_user_p)            = { "oscclk", "sclk_mmc2_fsys", };
1801 PNAME(mout_sclk_mmc1_user_p)            = { "oscclk", "sclk_mmc1_fsys", };
1802 PNAME(mout_sclk_mmc0_user_p)            = { "oscclk", "sclk_mmc0_fsys", };
1803
1804 static unsigned long fsys_clk_regs[] __initdata = {
1805         MUX_SEL_FSYS0,
1806         MUX_SEL_FSYS1,
1807         MUX_SEL_FSYS2,
1808         MUX_SEL_FSYS3,
1809         MUX_SEL_FSYS4,
1810         MUX_ENABLE_FSYS0,
1811         MUX_ENABLE_FSYS1,
1812         MUX_ENABLE_FSYS2,
1813         MUX_ENABLE_FSYS3,
1814         MUX_ENABLE_FSYS4,
1815         MUX_STAT_FSYS0,
1816         MUX_STAT_FSYS1,
1817         MUX_STAT_FSYS2,
1818         MUX_STAT_FSYS3,
1819         MUX_STAT_FSYS4,
1820         MUX_IGNORE_FSYS2,
1821         MUX_IGNORE_FSYS3,
1822         ENABLE_ACLK_FSYS0,
1823         ENABLE_ACLK_FSYS1,
1824         ENABLE_PCLK_FSYS,
1825         ENABLE_SCLK_FSYS,
1826         ENABLE_IP_FSYS0,
1827         ENABLE_IP_FSYS1,
1828 };
1829
1830 static struct samsung_mux_clock fsys_mux_clks[] __initdata = {
1831         /* MUX_SEL_FSYS0 */
1832         MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
1833                         mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
1834
1835         /* MUX_SEL_FSYS1 */
1836         MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
1837                         mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
1838         MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
1839                         mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
1840         MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
1841                         mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
1842 };
1843
1844 static struct samsung_gate_clock fsys_gate_clks[] __initdata = {
1845         /* ENABLE_ACLK_FSYS0 */
1846         GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
1847                         ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
1848         GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
1849                         ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
1850         GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
1851                         ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
1852         GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
1853                         ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
1854         GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
1855                         ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
1856         GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
1857                         ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
1858         GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
1859                         ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
1860         GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
1861                         ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
1862         GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
1863                         ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
1864         GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
1865                         ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
1866         GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
1867                         ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
1868
1869         /* ENABLE_SCLK_FSYS */
1870         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
1871                         ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
1872         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
1873                         ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
1874         GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
1875                         ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1876
1877         /* ENABLE_IP_FSYS0 */
1878         GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
1879         GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
1880 };
1881
1882 static struct samsung_cmu_info fsys_cmu_info __initdata = {
1883         .mux_clks               = fsys_mux_clks,
1884         .nr_mux_clks            = ARRAY_SIZE(fsys_mux_clks),
1885         .gate_clks              = fsys_gate_clks,
1886         .nr_gate_clks           = ARRAY_SIZE(fsys_gate_clks),
1887         .nr_clk_ids             = FSYS_NR_CLK,
1888         .clk_regs               = fsys_clk_regs,
1889         .nr_clk_regs            = ARRAY_SIZE(fsys_clk_regs),
1890 };
1891
1892 static void __init exynos5433_cmu_fsys_init(struct device_node *np)
1893 {
1894         samsung_cmu_register_one(np, &fsys_cmu_info);
1895 }
1896
1897 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
1898                 exynos5433_cmu_fsys_init);
1899
1900 /*
1901  * Register offset definitions for CMU_G2D
1902  */
1903 #define MUX_SEL_G2D0                            0x0200
1904 #define MUX_SEL_ENABLE_G2D0                     0x0300
1905 #define MUX_SEL_STAT_G2D0                       0x0400
1906 #define DIV_G2D                                 0x0600
1907 #define DIV_STAT_G2D                            0x0700
1908 #define DIV_ENABLE_ACLK_G2D                     0x0800
1909 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D     0x0804
1910 #define DIV_ENABLE_PCLK_G2D                     0x0900
1911 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D     0x0904
1912 #define DIV_ENABLE_IP_G2D0                      0x0b00
1913 #define DIV_ENABLE_IP_G2D1                      0x0b04
1914 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D       0x0b08
1915
1916 static unsigned long g2d_clk_regs[] __initdata = {
1917         MUX_SEL_G2D0,
1918         MUX_SEL_ENABLE_G2D0,
1919         MUX_SEL_STAT_G2D0,
1920         DIV_G2D,
1921         DIV_STAT_G2D,
1922         DIV_ENABLE_ACLK_G2D,
1923         DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
1924         DIV_ENABLE_PCLK_G2D,
1925         DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
1926         DIV_ENABLE_IP_G2D0,
1927         DIV_ENABLE_IP_G2D1,
1928         DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
1929 };
1930
1931 /* list of all parent clock list */
1932 PNAME(mout_aclk_g2d_266_user_p)         = { "oscclk", "aclk_g2d_266", };
1933 PNAME(mout_aclk_g2d_400_user_p)         = { "oscclk", "aclk_g2d_400", };
1934
1935 static struct samsung_mux_clock g2d_mux_clks[] __initdata = {
1936         /* MUX_SEL_G2D0 */
1937         MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
1938                         mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
1939         MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
1940                         mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
1941 };
1942
1943 static struct samsung_div_clock g2d_div_clks[] __initdata = {
1944         /* DIV_G2D */
1945         DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
1946                         DIV_G2D, 0, 2),
1947 };
1948
1949 static struct samsung_gate_clock g2d_gate_clks[] __initdata = {
1950         /* DIV_ENABLE_ACLK_G2D */
1951         GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
1952                         DIV_ENABLE_ACLK_G2D, 12, 0, 0),
1953         GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
1954                         DIV_ENABLE_ACLK_G2D, 11, 0, 0),
1955         GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
1956                         DIV_ENABLE_ACLK_G2D, 10, 0, 0),
1957         GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
1958                         DIV_ENABLE_ACLK_G2D, 9, 0, 0),
1959         GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
1960                         DIV_ENABLE_ACLK_G2D, 8, 0, 0),
1961         GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
1962                         "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
1963                         7, 0, 0),
1964         GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
1965                         DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
1966         GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
1967                         DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
1968         GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
1969                         DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
1970         GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
1971                         DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
1972         GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
1973                         DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
1974         GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
1975                         DIV_ENABLE_ACLK_G2D, 1, 0, 0),
1976         GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
1977                         DIV_ENABLE_ACLK_G2D, 0, 0, 0),
1978
1979         /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
1980         GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
1981                 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
1982
1983         /* DIV_ENABLE_PCLK_G2D */
1984         GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
1985                         DIV_ENABLE_PCLK_G2D, 7, 0, 0),
1986         GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
1987                         DIV_ENABLE_PCLK_G2D, 6, 0, 0),
1988         GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
1989                         DIV_ENABLE_PCLK_G2D, 5, 0, 0),
1990         GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
1991                         DIV_ENABLE_PCLK_G2D, 4, 0, 0),
1992         GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
1993                         DIV_ENABLE_PCLK_G2D, 3, 0, 0),
1994         GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
1995                         DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
1996         GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
1997                         DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
1998         GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
1999                         0, 0, 0),
2000
2001         /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2002         GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2003                 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2004 };
2005
2006 static struct samsung_cmu_info g2d_cmu_info __initdata = {
2007         .mux_clks               = g2d_mux_clks,
2008         .nr_mux_clks            = ARRAY_SIZE(g2d_mux_clks),
2009         .div_clks               = g2d_div_clks,
2010         .nr_div_clks            = ARRAY_SIZE(g2d_div_clks),
2011         .gate_clks              = g2d_gate_clks,
2012         .nr_gate_clks           = ARRAY_SIZE(g2d_gate_clks),
2013         .nr_clk_ids             = G2D_NR_CLK,
2014         .clk_regs               = g2d_clk_regs,
2015         .nr_clk_regs            = ARRAY_SIZE(g2d_clk_regs),
2016 };
2017
2018 static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2019 {
2020         samsung_cmu_register_one(np, &g2d_cmu_info);
2021 }
2022
2023 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2024                 exynos5433_cmu_g2d_init);