2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Common Clock Framework support for Exynos4415 SoC.
12 #include <linux/clk.h>
13 #include <linux/clkdev.h>
14 #include <linux/clk-provider.h>
16 #include <linux/of_address.h>
17 #include <linux/platform_device.h>
18 #include <linux/syscore_ops.h>
20 #include <dt-bindings/clock/exynos4415.h>
25 #define SRC_LEFTBUS 0x4200
26 #define DIV_LEFTBUS 0x4500
27 #define GATE_IP_LEFTBUS 0x4800
28 #define GATE_IP_IMAGE 0x4930
29 #define SRC_RIGHTBUS 0x8200
30 #define DIV_RIGHTBUS 0x8500
31 #define GATE_IP_RIGHTBUS 0x8800
32 #define GATE_IP_PERIR 0x8960
33 #define EPLL_LOCK 0xc010
34 #define G3D_PLL_LOCK 0xc020
35 #define DISP_PLL_LOCK 0xc030
36 #define ISP_PLL_LOCK 0xc040
37 #define EPLL_CON0 0xc110
38 #define EPLL_CON1 0xc114
39 #define EPLL_CON2 0xc118
40 #define G3D_PLL_CON0 0xc120
41 #define G3D_PLL_CON1 0xc124
42 #define G3D_PLL_CON2 0xc128
43 #define ISP_PLL_CON0 0xc130
44 #define ISP_PLL_CON1 0xc134
45 #define ISP_PLL_CON2 0xc138
46 #define DISP_PLL_CON0 0xc140
47 #define DISP_PLL_CON1 0xc144
48 #define DISP_PLL_CON2 0xc148
49 #define SRC_TOP0 0xc210
50 #define SRC_TOP1 0xc214
51 #define SRC_CAM 0xc220
53 #define SRC_MFC 0xc228
54 #define SRC_G3D 0xc22c
55 #define SRC_LCD 0xc234
56 #define SRC_ISP 0xc238
57 #define SRC_MAUDIO 0xc23c
58 #define SRC_FSYS 0xc240
59 #define SRC_PERIL0 0xc250
60 #define SRC_PERIL1 0xc254
61 #define SRC_CAM1 0xc258
62 #define SRC_TOP_ISP0 0xc25c
63 #define SRC_TOP_ISP1 0xc260
64 #define SRC_MASK_TOP 0xc310
65 #define SRC_MASK_CAM 0xc320
66 #define SRC_MASK_TV 0xc324
67 #define SRC_MASK_LCD 0xc334
68 #define SRC_MASK_ISP 0xc338
69 #define SRC_MASK_MAUDIO 0xc33c
70 #define SRC_MASK_FSYS 0xc340
71 #define SRC_MASK_PERIL0 0xc350
72 #define SRC_MASK_PERIL1 0xc354
73 #define DIV_TOP 0xc510
74 #define DIV_CAM 0xc520
76 #define DIV_MFC 0xc528
77 #define DIV_G3D 0xc52c
78 #define DIV_LCD 0xc534
79 #define DIV_ISP 0xc538
80 #define DIV_MAUDIO 0xc53c
81 #define DIV_FSYS0 0xc540
82 #define DIV_FSYS1 0xc544
83 #define DIV_FSYS2 0xc548
84 #define DIV_PERIL0 0xc550
85 #define DIV_PERIL1 0xc554
86 #define DIV_PERIL2 0xc558
87 #define DIV_PERIL3 0xc55c
88 #define DIV_PERIL4 0xc560
89 #define DIV_PERIL5 0xc564
90 #define DIV_CAM1 0xc568
91 #define DIV_TOP_ISP1 0xc56c
92 #define DIV_TOP_ISP0 0xc570
93 #define CLKDIV2_RATIO 0xc580
94 #define GATE_SCLK_CAM 0xc820
95 #define GATE_SCLK_TV 0xc824
96 #define GATE_SCLK_MFC 0xc828
97 #define GATE_SCLK_G3D 0xc82c
98 #define GATE_SCLK_LCD 0xc834
99 #define GATE_SCLK_MAUDIO 0xc83c
100 #define GATE_SCLK_FSYS 0xc840
101 #define GATE_SCLK_PERIL 0xc850
102 #define GATE_IP_CAM 0xc920
103 #define GATE_IP_TV 0xc924
104 #define GATE_IP_MFC 0xc928
105 #define GATE_IP_G3D 0xc92c
106 #define GATE_IP_LCD 0xc934
107 #define GATE_IP_FSYS 0xc940
108 #define GATE_IP_PERIL 0xc950
109 #define GATE_BLOCK 0xc970
110 #define APLL_LOCK 0x14000
111 #define APLL_CON0 0x14100
112 #define SRC_CPU 0x14200
113 #define DIV_CPU0 0x14500
114 #define DIV_CPU1 0x14504
116 static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
209 /* list of all parent clock list */
210 PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
212 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
213 PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
214 PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
215 PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
217 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
218 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
219 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
220 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
222 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
223 PNAME(mout_ebi_1_p) = { "mout_ebi", "mout_g3d_pll", };
225 PNAME(mout_gdl_p) = { "mout_mpll_user_l", };
226 PNAME(mout_gdr_p) = { "mout_mpll_user_r", };
228 PNAME(mout_aclk_266_p) = { "mout_mpll_user_t", "mout_g3d_pll", };
230 PNAME(group_epll_g3dpll_p) = { "mout_epll", "mout_g3d_pll" };
231 PNAME(group_sclk_p) = { "xxti", "xusbxti",
232 "none", "mout_isp_pll",
233 "none", "none", "div_mpll_pre",
234 "mout_epll", "mout_g3d_pll", };
235 PNAME(group_spdif_p) = { "mout_audio0", "mout_audio1",
236 "mout_audio2", "spdif_extclk", };
237 PNAME(group_sclk_audio2_p) = { "audiocdclk2", "none",
238 "none", "mout_isp_pll",
239 "mout_disp_pll", "xusbxti",
240 "div_mpll_pre", "mout_epll",
242 PNAME(group_sclk_audio1_p) = { "audiocdclk1", "none",
243 "none", "mout_isp_pll",
244 "mout_disp_pll", "xusbxti",
245 "div_mpll_pre", "mout_epll",
247 PNAME(group_sclk_audio0_p) = { "audiocdclk0", "none",
248 "none", "mout_isp_pll",
249 "mout_disp_pll", "xusbxti",
250 "div_mpll_pre", "mout_epll",
252 PNAME(group_fimc_lclk_p) = { "xxti", "xusbxti",
253 "none", "mout_isp_pll",
254 "none", "mout_disp_pll",
255 "mout_mpll_user_t", "mout_epll",
257 PNAME(group_sclk_fimd0_p) = { "xxti", "xusbxti",
258 "m_bitclkhsdiv4_4l", "mout_isp_pll",
259 "mout_disp_pll", "sclk_hdmiphy",
260 "div_mpll_pre", "mout_epll",
262 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy" };
263 PNAME(mout_mfc_p) = { "mout_mfc_0", "mout_mfc_1" };
264 PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" };
265 PNAME(mout_jpeg_p) = { "mout_jpeg_0", "mout_jpeg_1" };
266 PNAME(mout_jpeg1_p) = { "mout_epll", "mout_g3d_pll" };
267 PNAME(group_aclk_isp0_300_p) = { "mout_isp_pll", "div_mpll_pre" };
268 PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" };
269 PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" };
270 PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" };
271 PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" };
273 static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = {
274 /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */
275 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
278 static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = {
279 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
282 static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = {
284 * NOTE: Following table is sorted by register address in ascending
285 * order and then bitfield shift in descending order, as it is done
286 * in the User's Manual. When adding new entries, please make sure
287 * that the order is preserved, to avoid merge conflicts and make
288 * further work with defined data easier.
292 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
294 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
297 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
299 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
302 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
303 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_mout_mpll_user_t_p,
305 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_mout_mpll_user_t_p,
307 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_mout_mpll_user_t_p,
309 MUX(CLK_MOUT_ACLK_266, "mout_aclk_266", mout_aclk_266_p,
311 MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
313 MUX(CLK_MOUT_EPLL, "mout_epll", mout_epll_p, SRC_TOP0, 4, 1),
314 MUX(CLK_MOUT_EBI_1, "mout_ebi_1", mout_ebi_1_p, SRC_TOP0, 0, 1),
317 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p,
319 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p,
321 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p,
323 MUX(CLK_MOUT_ACLK_400_MCUISP, "mout_aclk_400_mcuisp",
324 group_mout_mpll_user_t_p, SRC_TOP1, 8, 1),
325 MUX(CLK_MOUT_G3D_PLLSRC, "mout_g3d_pllsrc", mout_g3d_pllsrc_p,
329 MUX(CLK_MOUT_CSIS1, "mout_csis1", group_fimc_lclk_p, SRC_CAM, 28, 4),
330 MUX(CLK_MOUT_CSIS0, "mout_csis0", group_fimc_lclk_p, SRC_CAM, 24, 4),
331 MUX(CLK_MOUT_CAM1, "mout_cam1", group_fimc_lclk_p, SRC_CAM, 20, 4),
332 MUX(CLK_MOUT_FIMC3_LCLK, "mout_fimc3_lclk", group_fimc_lclk_p, SRC_CAM,
334 MUX(CLK_MOUT_FIMC2_LCLK, "mout_fimc2_lclk", group_fimc_lclk_p, SRC_CAM,
336 MUX(CLK_MOUT_FIMC1_LCLK, "mout_fimc1_lclk", group_fimc_lclk_p, SRC_CAM,
338 MUX(CLK_MOUT_FIMC0_LCLK, "mout_fimc0_lclk", group_fimc_lclk_p, SRC_CAM,
342 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
345 MUX(CLK_MOUT_MFC, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
346 MUX(CLK_MOUT_MFC_1, "mout_mfc_1", group_epll_g3dpll_p, SRC_MFC, 4, 1),
347 MUX(CLK_MOUT_MFC_0, "mout_mfc_0", group_mout_mpll_user_t_p, SRC_MFC, 0,
351 MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1),
352 MUX(CLK_MOUT_G3D_1, "mout_g3d_1", group_epll_g3dpll_p, SRC_G3D, 4, 1),
353 MUX(CLK_MOUT_G3D_0, "mout_g3d_0", group_mout_mpll_user_t_p, SRC_G3D, 0,
357 MUX(CLK_MOUT_MIPI0, "mout_mipi0", group_fimc_lclk_p, SRC_LCD, 12, 4),
358 MUX(CLK_MOUT_FIMD0, "mout_fimd0", group_sclk_fimd0_p, SRC_LCD, 0, 4),
361 MUX(CLK_MOUT_TSADC_ISP, "mout_tsadc_isp", group_fimc_lclk_p, SRC_ISP,
363 MUX(CLK_MOUT_UART_ISP, "mout_uart_isp", group_fimc_lclk_p, SRC_ISP,
365 MUX(CLK_MOUT_SPI1_ISP, "mout_spi1_isp", group_fimc_lclk_p, SRC_ISP,
367 MUX(CLK_MOUT_SPI0_ISP, "mout_spi0_isp", group_fimc_lclk_p, SRC_ISP,
369 MUX(CLK_MOUT_PWM_ISP, "mout_pwm_isp", group_fimc_lclk_p, SRC_ISP,
373 MUX(CLK_MOUT_AUDIO0, "mout_audio0", group_sclk_audio0_p, SRC_MAUDIO,
377 MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
378 MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
379 MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
380 MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
383 MUX(CLK_MOUT_UART3, "mout_uart3", group_sclk_p, SRC_PERIL0, 12, 4),
384 MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
385 MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
386 MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
389 MUX(CLK_MOUT_SPI2, "mout_spi2", group_sclk_p, SRC_PERIL1, 24, 4),
390 MUX(CLK_MOUT_SPI1, "mout_spi1", group_sclk_p, SRC_PERIL1, 20, 4),
391 MUX(CLK_MOUT_SPI0, "mout_spi0", group_sclk_p, SRC_PERIL1, 16, 4),
392 MUX(CLK_MOUT_SPDIF, "mout_spdif", group_spdif_p, SRC_PERIL1, 8, 4),
393 MUX(CLK_MOUT_AUDIO2, "mout_audio2", group_sclk_audio2_p, SRC_PERIL1,
395 MUX(CLK_MOUT_AUDIO1, "mout_audio1", group_sclk_audio1_p, SRC_PERIL1,
399 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
401 MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
402 MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
404 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
405 CLK_SET_RATE_PARENT, 0),
408 MUX(CLK_MOUT_PXLASYNC_CSIS1_FIMC, "mout_pxlasync_csis1",
409 group_fimc_lclk_p, SRC_CAM1, 20, 1),
410 MUX(CLK_MOUT_PXLASYNC_CSIS0_FIMC, "mout_pxlasync_csis0",
411 group_fimc_lclk_p, SRC_CAM1, 16, 1),
412 MUX(CLK_MOUT_JPEG, "mout_jpeg", mout_jpeg_p, SRC_CAM1, 8, 1),
413 MUX(CLK_MOUT_JPEG1, "mout_jpeg_1", mout_jpeg1_p, SRC_CAM1, 4, 1),
414 MUX(CLK_MOUT_JPEG0, "mout_jpeg_0", group_mout_mpll_user_t_p, SRC_CAM1,
418 MUX(CLK_MOUT_ACLK_ISP0_300, "mout_aclk_isp0_300",
419 group_aclk_isp0_300_p, SRC_TOP_ISP0, 8, 1),
420 MUX(CLK_MOUT_ACLK_ISP0_400, "mout_aclk_isp0_400_user",
421 group_aclk_isp0_400_user_p, SRC_TOP_ISP0, 4, 1),
422 MUX(CLK_MOUT_ACLK_ISP0_300_USER, "mout_aclk_isp0_300_user",
423 group_aclk_isp0_300_user_p, SRC_TOP_ISP0, 0, 1),
426 MUX(CLK_MOUT_ACLK_ISP1_300, "mout_aclk_isp1_300",
427 group_aclk_isp0_300_p, SRC_TOP_ISP1, 4, 1),
428 MUX(CLK_MOUT_ACLK_ISP1_300_USER, "mout_aclk_isp1_300_user",
429 group_aclk_isp1_300_user_p, SRC_TOP_ISP1, 0, 1),
432 static struct samsung_div_clock exynos4415_div_clks[] __initdata = {
434 * NOTE: Following table is sorted by register address in ascending
435 * order and then bitfield shift in descending order, as it is done
436 * in the User's Manual. When adding new entries, please make sure
437 * that the order is preserved, to avoid merge conflicts and make
438 * further work with defined data easier.
442 DIV(CLK_DIV_GPL, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
443 DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 4),
446 DIV(CLK_DIV_GPR, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
447 DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 4),
450 DIV(CLK_DIV_ACLK_400_MCUISP, "div_aclk_400_mcuisp",
451 "mout_aclk_400_mcuisp", DIV_TOP, 24, 3),
452 DIV(CLK_DIV_EBI, "div_ebi", "mout_ebi_1", DIV_TOP, 16, 3),
453 DIV(CLK_DIV_ACLK_200, "div_aclk_200", "mout_aclk_200", DIV_TOP, 12, 3),
454 DIV(CLK_DIV_ACLK_160, "div_aclk_160", "mout_aclk_160", DIV_TOP, 8, 3),
455 DIV(CLK_DIV_ACLK_100, "div_aclk_100", "mout_aclk_100", DIV_TOP, 4, 4),
456 DIV(CLK_DIV_ACLK_266, "div_aclk_266", "mout_aclk_266", DIV_TOP, 0, 3),
459 DIV(CLK_DIV_CSIS1, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
460 DIV(CLK_DIV_CSIS0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
461 DIV(CLK_DIV_CAM1, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
462 DIV(CLK_DIV_FIMC3_LCLK, "div_fimc3_lclk", "mout_fimc3_lclk", DIV_CAM,
464 DIV(CLK_DIV_FIMC2_LCLK, "div_fimc2_lclk", "mout_fimc2_lclk", DIV_CAM,
466 DIV(CLK_DIV_FIMC1_LCLK, "div_fimc1_lclk", "mout_fimc1_lclk", DIV_CAM,
468 DIV(CLK_DIV_FIMC0_LCLK, "div_fimc0_lclk", "mout_fimc0_lclk", DIV_CAM,
472 DIV(CLK_DIV_TV_BLK, "div_tv_blk", "mout_g3d_pll", DIV_TV, 0, 4),
475 DIV(CLK_DIV_MFC, "div_mfc", "mout_mfc", DIV_MFC, 0, 4),
478 DIV(CLK_DIV_G3D, "div_g3d", "mout_g3d", DIV_G3D, 0, 4),
481 DIV_F(CLK_DIV_MIPI0_PRE, "div_mipi0_pre", "div_mipi0", DIV_LCD, 20, 4,
482 CLK_SET_RATE_PARENT, 0),
483 DIV(CLK_DIV_MIPI0, "div_mipi0", "mout_mipi0", DIV_LCD, 16, 4),
484 DIV(CLK_DIV_FIMD0, "div_fimd0", "mout_fimd0", DIV_LCD, 0, 4),
487 DIV(CLK_DIV_UART_ISP, "div_uart_isp", "mout_uart_isp", DIV_ISP, 28, 4),
488 DIV_F(CLK_DIV_SPI1_ISP_PRE, "div_spi1_isp_pre", "div_spi1_isp",
489 DIV_ISP, 20, 8, CLK_SET_RATE_PARENT, 0),
490 DIV(CLK_DIV_SPI1_ISP, "div_spi1_isp", "mout_spi1_isp", DIV_ISP, 16, 4),
491 DIV_F(CLK_DIV_SPI0_ISP_PRE, "div_spi0_isp_pre", "div_spi0_isp",
492 DIV_ISP, 8, 8, CLK_SET_RATE_PARENT, 0),
493 DIV(CLK_DIV_SPI0_ISP, "div_spi0_isp", "mout_spi0_isp", DIV_ISP, 4, 4),
494 DIV(CLK_DIV_PWM_ISP, "div_pwm_isp", "mout_pwm_isp", DIV_ISP, 0, 4),
497 DIV(CLK_DIV_PCM0, "div_pcm0", "div_audio0", DIV_MAUDIO, 4, 8),
498 DIV(CLK_DIV_AUDIO0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
501 DIV_F(CLK_DIV_TSADC_PRE, "div_tsadc_pre", "div_tsadc", DIV_FSYS0, 8, 8,
502 CLK_SET_RATE_PARENT, 0),
503 DIV(CLK_DIV_TSADC, "div_tsadc", "mout_tsadc", DIV_FSYS0, 0, 4),
506 DIV_F(CLK_DIV_MMC1_PRE, "div_mmc1_pre", "div_mmc1", DIV_FSYS1, 24, 8,
507 CLK_SET_RATE_PARENT, 0),
508 DIV(CLK_DIV_MMC1, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
509 DIV_F(CLK_DIV_MMC0_PRE, "div_mmc0_pre", "div_mmc0", DIV_FSYS1, 8, 8,
510 CLK_SET_RATE_PARENT, 0),
511 DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
514 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
515 CLK_SET_RATE_PARENT, 0),
516 DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4,
517 CLK_SET_RATE_PARENT, 0),
520 DIV(CLK_DIV_UART3, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
521 DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
522 DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
523 DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
526 DIV_F(CLK_DIV_SPI1_PRE, "div_spi1_pre", "div_spi1", DIV_PERIL1, 24, 8,
527 CLK_SET_RATE_PARENT, 0),
528 DIV(CLK_DIV_SPI1, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
529 DIV_F(CLK_DIV_SPI0_PRE, "div_spi0_pre", "div_spi0", DIV_PERIL1, 8, 8,
530 CLK_SET_RATE_PARENT, 0),
531 DIV(CLK_DIV_SPI0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
534 DIV_F(CLK_DIV_SPI2_PRE, "div_spi2_pre", "div_spi2", DIV_PERIL2, 8, 8,
535 CLK_SET_RATE_PARENT, 0),
536 DIV(CLK_DIV_SPI2, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
539 DIV(CLK_DIV_PCM2, "div_pcm2", "div_audio2", DIV_PERIL4, 20, 8),
540 DIV(CLK_DIV_AUDIO2, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
541 DIV(CLK_DIV_PCM1, "div_pcm1", "div_audio1", DIV_PERIL4, 20, 8),
542 DIV(CLK_DIV_AUDIO1, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
545 DIV(CLK_DIV_I2S1, "div_i2s1", "div_audio1", DIV_PERIL5, 0, 6),
548 DIV(CLK_DIV_PXLASYNC_CSIS1_FIMC, "div_pxlasync_csis1_fimc",
549 "mout_pxlasync_csis1", DIV_CAM1, 24, 4),
550 DIV(CLK_DIV_PXLASYNC_CSIS0_FIMC, "div_pxlasync_csis0_fimc",
551 "mout_pxlasync_csis0", DIV_CAM1, 20, 4),
552 DIV(CLK_DIV_JPEG, "div_jpeg", "mout_jpeg", DIV_CAM1, 0, 4),
555 DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
556 DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
557 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
558 DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
559 DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
560 DIV(CLK_DIV_PERIPH, "div_periph", "div_core2", DIV_CPU0, 12, 3),
561 DIV(CLK_DIV_COREM1, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
562 DIV(CLK_DIV_COREM0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
563 DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
564 CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
567 DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
568 DIV(CLK_DIV_COPY, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
571 static struct samsung_gate_clock exynos4415_gate_clks[] __initdata = {
573 * NOTE: Following table is sorted by register address in ascending
574 * order and then bitfield shift in descending order, as it is done
575 * in the User's Manual. When adding new entries, please make sure
576 * that the order is preserved, to avoid merge conflicts and make
577 * further work with defined data easier.
580 /* GATE_IP_LEFTBUS */
581 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
582 CLK_IGNORE_UNUSED, 0),
583 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
584 CLK_IGNORE_UNUSED, 0),
585 GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
586 CLK_IGNORE_UNUSED, 0),
587 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
588 CLK_IGNORE_UNUSED, 0),
589 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
590 CLK_IGNORE_UNUSED, 0),
593 GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
595 GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
597 GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
599 GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
601 GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
603 GATE(CLK_MDMA2, "mdma2", "div_aclk_100", GATE_IP_IMAGE, 2, 0, 0),
604 GATE(CLK_ROTATOR, "rotator", "div_aclk_100", GATE_IP_IMAGE, 1, 0, 0),
606 /* GATE_IP_RIGHTBUS */
607 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
608 GATE_IP_RIGHTBUS, 9, CLK_IGNORE_UNUSED, 0),
609 GATE(CLK_ASYNC_MAUDIOX, "async_maudiox", "div_aclk_100",
610 GATE_IP_RIGHTBUS, 7, CLK_IGNORE_UNUSED, 0),
611 GATE(CLK_ASYNC_MFCR, "async_mfcr", "div_aclk_100",
612 GATE_IP_RIGHTBUS, 6, CLK_IGNORE_UNUSED, 0),
613 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
614 GATE_IP_RIGHTBUS, 5, CLK_IGNORE_UNUSED, 0),
615 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
616 GATE_IP_RIGHTBUS, 3, CLK_IGNORE_UNUSED, 0),
617 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100",
618 GATE_IP_RIGHTBUS, 2, CLK_IGNORE_UNUSED, 0),
619 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100",
620 GATE_IP_RIGHTBUS, 1, CLK_IGNORE_UNUSED, 0),
621 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100",
622 GATE_IP_RIGHTBUS, 0, CLK_IGNORE_UNUSED, 0),
625 GATE(CLK_ANTIRBK_APBIF, "antirbk_apbif", "div_aclk_100",
626 GATE_IP_PERIR, 24, CLK_IGNORE_UNUSED, 0),
627 GATE(CLK_EFUSE_WRITER_APBIF, "efuse_writer_apbif", "div_aclk_100",
628 GATE_IP_PERIR, 23, CLK_IGNORE_UNUSED, 0),
629 GATE(CLK_MONOCNT, "monocnt", "div_aclk_100", GATE_IP_PERIR, 22,
630 CLK_IGNORE_UNUSED, 0),
631 GATE(CLK_TZPC6, "tzpc6", "div_aclk_100", GATE_IP_PERIR, 21,
632 CLK_IGNORE_UNUSED, 0),
633 GATE(CLK_PROVISIONKEY1, "provisionkey1", "div_aclk_100",
634 GATE_IP_PERIR, 20, CLK_IGNORE_UNUSED, 0),
635 GATE(CLK_PROVISIONKEY0, "provisionkey0", "div_aclk_100",
636 GATE_IP_PERIR, 19, CLK_IGNORE_UNUSED, 0),
637 GATE(CLK_CMU_ISPPART, "cmu_isppart", "div_aclk_100", GATE_IP_PERIR, 18,
638 CLK_IGNORE_UNUSED, 0),
639 GATE(CLK_TMU_APBIF, "tmu_apbif", "div_aclk_100",
640 GATE_IP_PERIR, 17, 0, 0),
641 GATE(CLK_KEYIF, "keyif", "div_aclk_100", GATE_IP_PERIR, 16, 0, 0),
642 GATE(CLK_RTC, "rtc", "div_aclk_100", GATE_IP_PERIR, 15, 0, 0),
643 GATE(CLK_WDT, "wdt", "div_aclk_100", GATE_IP_PERIR, 14, 0, 0),
644 GATE(CLK_MCT, "mct", "div_aclk_100", GATE_IP_PERIR, 13, 0, 0),
645 GATE(CLK_SECKEY, "seckey", "div_aclk_100", GATE_IP_PERIR, 12,
646 CLK_IGNORE_UNUSED, 0),
647 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk_100", GATE_IP_PERIR, 11,
648 CLK_IGNORE_UNUSED, 0),
649 GATE(CLK_TZPC5, "tzpc5", "div_aclk_100", GATE_IP_PERIR, 10,
650 CLK_IGNORE_UNUSED, 0),
651 GATE(CLK_TZPC4, "tzpc4", "div_aclk_100", GATE_IP_PERIR, 9,
652 CLK_IGNORE_UNUSED, 0),
653 GATE(CLK_TZPC3, "tzpc3", "div_aclk_100", GATE_IP_PERIR, 8,
654 CLK_IGNORE_UNUSED, 0),
655 GATE(CLK_TZPC2, "tzpc2", "div_aclk_100", GATE_IP_PERIR, 7,
656 CLK_IGNORE_UNUSED, 0),
657 GATE(CLK_TZPC1, "tzpc1", "div_aclk_100", GATE_IP_PERIR, 6,
658 CLK_IGNORE_UNUSED, 0),
659 GATE(CLK_TZPC0, "tzpc0", "div_aclk_100", GATE_IP_PERIR, 5,
660 CLK_IGNORE_UNUSED, 0),
661 GATE(CLK_CMU_COREPART, "cmu_corepart", "div_aclk_100", GATE_IP_PERIR, 4,
662 CLK_IGNORE_UNUSED, 0),
663 GATE(CLK_CMU_TOPPART, "cmu_toppart", "div_aclk_100", GATE_IP_PERIR, 3,
664 CLK_IGNORE_UNUSED, 0),
665 GATE(CLK_PMU_APBIF, "pmu_apbif", "div_aclk_100", GATE_IP_PERIR, 2,
666 CLK_IGNORE_UNUSED, 0),
667 GATE(CLK_SYSREG, "sysreg", "div_aclk_100", GATE_IP_PERIR, 1,
668 CLK_IGNORE_UNUSED, 0),
669 GATE(CLK_CHIP_ID, "chip_id", "div_aclk_100", GATE_IP_PERIR, 0,
670 CLK_IGNORE_UNUSED, 0),
672 /* GATE_SCLK_CAM - non-completed */
673 GATE(CLK_SCLK_PXLAYSNC_CSIS1_FIMC, "sclk_pxlasync_csis1_fimc",
674 "div_pxlasync_csis1_fimc", GATE_SCLK_CAM, 11,
675 CLK_SET_RATE_PARENT, 0),
676 GATE(CLK_SCLK_PXLAYSNC_CSIS0_FIMC, "sclk_pxlasync_csis0_fimc",
677 "div_pxlasync_csis0_fimc", GATE_SCLK_CAM,
678 10, CLK_SET_RATE_PARENT, 0),
679 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
680 GATE_SCLK_CAM, 8, CLK_SET_RATE_PARENT, 0),
681 GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1",
682 GATE_SCLK_CAM, 7, CLK_SET_RATE_PARENT, 0),
683 GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0",
684 GATE_SCLK_CAM, 6, CLK_SET_RATE_PARENT, 0),
685 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
686 GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0),
687 GATE(CLK_SCLK_FIMC3_LCLK, "sclk_fimc3_lclk", "div_fimc3_lclk",
688 GATE_SCLK_CAM, 3, CLK_SET_RATE_PARENT, 0),
689 GATE(CLK_SCLK_FIMC2_LCLK, "sclk_fimc2_lclk", "div_fimc2_lclk",
690 GATE_SCLK_CAM, 2, CLK_SET_RATE_PARENT, 0),
691 GATE(CLK_SCLK_FIMC1_LCLK, "sclk_fimc1_lclk", "div_fimc1_lclk",
692 GATE_SCLK_CAM, 1, CLK_SET_RATE_PARENT, 0),
693 GATE(CLK_SCLK_FIMC0_LCLK, "sclk_fimc0_lclk", "div_fimc0_lclk",
694 GATE_SCLK_CAM, 0, CLK_SET_RATE_PARENT, 0),
697 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "div_tv_blk",
698 GATE_SCLK_TV, 3, CLK_SET_RATE_PARENT, 0),
699 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
700 GATE_SCLK_TV, 2, CLK_SET_RATE_PARENT, 0),
701 GATE(CLK_SCLK_MIXER, "sclk_mixer", "div_tv_blk",
702 GATE_SCLK_TV, 0, CLK_SET_RATE_PARENT, 0),
705 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
706 GATE_SCLK_MFC, 0, CLK_SET_RATE_PARENT, 0),
709 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
710 GATE_SCLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
713 GATE(CLK_SCLK_MIPIDPHY4L, "sclk_mipidphy4l", "div_mipi0",
714 GATE_SCLK_LCD, 4, CLK_SET_RATE_PARENT, 0),
715 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi0_pre",
716 GATE_SCLK_LCD, 3, CLK_SET_RATE_PARENT, 0),
717 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_fimd0",
718 GATE_SCLK_LCD, 1, CLK_SET_RATE_PARENT, 0),
719 GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0",
720 GATE_SCLK_LCD, 0, CLK_SET_RATE_PARENT, 0),
722 /* GATE_SCLK_MAUDIO */
723 GATE(CLK_SCLK_PCM0, "sclk_pcm0", "div_pcm0",
724 GATE_SCLK_MAUDIO, 1, CLK_SET_RATE_PARENT, 0),
725 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0",
726 GATE_SCLK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0),
729 GATE(CLK_SCLK_TSADC, "sclk_tsadc", "div_tsadc_pre",
730 GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
731 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
732 GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
733 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
734 GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
735 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
736 GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
737 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
738 GATE_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
740 /* GATE_SCLK_PERIL */
741 GATE(CLK_SCLK_I2S, "sclk_i2s1", "div_i2s1",
742 GATE_SCLK_PERIL, 18, CLK_SET_RATE_PARENT, 0),
743 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "div_pcm2",
744 GATE_SCLK_PERIL, 16, CLK_SET_RATE_PARENT, 0),
745 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "div_pcm1",
746 GATE_SCLK_PERIL, 15, CLK_SET_RATE_PARENT, 0),
747 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2",
748 GATE_SCLK_PERIL, 14, CLK_SET_RATE_PARENT, 0),
749 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1",
750 GATE_SCLK_PERIL, 13, CLK_SET_RATE_PARENT, 0),
751 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
752 GATE_SCLK_PERIL, 10, CLK_SET_RATE_PARENT, 0),
753 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi2_pre",
754 GATE_SCLK_PERIL, 8, CLK_SET_RATE_PARENT, 0),
755 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi1_pre",
756 GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
757 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
758 GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
759 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3",
760 GATE_SCLK_PERIL, 3, CLK_SET_RATE_PARENT, 0),
761 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
762 GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
763 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
764 GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
765 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
766 GATE_SCLK_PERIL, 0, CLK_SET_RATE_PARENT, 0),
769 GATE(CLK_SMMUFIMC_LITE2, "smmufimc_lite2", "div_aclk_160", GATE_IP_CAM,
770 22, CLK_IGNORE_UNUSED, 0),
771 GATE(CLK_FIMC_LITE2, "fimc_lite2", "div_aclk_160", GATE_IP_CAM,
772 20, CLK_IGNORE_UNUSED, 0),
773 GATE(CLK_PIXELASYNCM1, "pixelasyncm1", "div_aclk_160", GATE_IP_CAM,
774 18, CLK_IGNORE_UNUSED, 0),
775 GATE(CLK_PIXELASYNCM0, "pixelasyncm0", "div_aclk_160", GATE_IP_CAM,
776 17, CLK_IGNORE_UNUSED, 0),
777 GATE(CLK_PPMUCAMIF, "ppmucamif", "div_aclk_160", GATE_IP_CAM,
778 16, CLK_IGNORE_UNUSED, 0),
779 GATE(CLK_SMMUJPEG, "smmujpeg", "div_aclk_160", GATE_IP_CAM, 11, 0, 0),
780 GATE(CLK_SMMUFIMC3, "smmufimc3", "div_aclk_160", GATE_IP_CAM, 10, 0, 0),
781 GATE(CLK_SMMUFIMC2, "smmufimc2", "div_aclk_160", GATE_IP_CAM, 9, 0, 0),
782 GATE(CLK_SMMUFIMC1, "smmufimc1", "div_aclk_160", GATE_IP_CAM, 8, 0, 0),
783 GATE(CLK_SMMUFIMC0, "smmufimc0", "div_aclk_160", GATE_IP_CAM, 7, 0, 0),
784 GATE(CLK_JPEG, "jpeg", "div_aclk_160", GATE_IP_CAM, 6, 0, 0),
785 GATE(CLK_CSIS1, "csis1", "div_aclk_160", GATE_IP_CAM, 5, 0, 0),
786 GATE(CLK_CSIS0, "csis0", "div_aclk_160", GATE_IP_CAM, 4, 0, 0),
787 GATE(CLK_FIMC3, "fimc3", "div_aclk_160", GATE_IP_CAM, 3, 0, 0),
788 GATE(CLK_FIMC2, "fimc2", "div_aclk_160", GATE_IP_CAM, 2, 0, 0),
789 GATE(CLK_FIMC1, "fimc1", "div_aclk_160", GATE_IP_CAM, 1, 0, 0),
790 GATE(CLK_FIMC0, "fimc0", "div_aclk_160", GATE_IP_CAM, 0, 0, 0),
793 GATE(CLK_PPMUTV, "ppmutv", "div_aclk_100", GATE_IP_TV, 5, 0, 0),
794 GATE(CLK_SMMUTV, "smmutv", "div_aclk_100", GATE_IP_TV, 4, 0, 0),
795 GATE(CLK_HDMI, "hdmi", "div_aclk_100", GATE_IP_TV, 3, 0, 0),
796 GATE(CLK_MIXER, "mixer", "div_aclk_100", GATE_IP_TV, 1, 0, 0),
797 GATE(CLK_VP, "vp", "div_aclk_100", GATE_IP_TV, 0, 0, 0),
800 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "div_aclk_200", GATE_IP_MFC, 4,
801 CLK_IGNORE_UNUSED, 0),
802 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "div_aclk_200", GATE_IP_MFC, 3,
803 CLK_IGNORE_UNUSED, 0),
804 GATE(CLK_SMMUMFC_R, "smmumfc_r", "div_aclk_200", GATE_IP_MFC, 2, 0, 0),
805 GATE(CLK_SMMUMFC_L, "smmumfc_l", "div_aclk_200", GATE_IP_MFC, 1, 0, 0),
806 GATE(CLK_MFC, "mfc", "div_aclk_200", GATE_IP_MFC, 0, 0, 0),
809 GATE(CLK_PPMUG3D, "ppmug3d", "div_aclk_200", GATE_IP_G3D, 1,
810 CLK_IGNORE_UNUSED, 0),
811 GATE(CLK_G3D, "g3d", "div_aclk_200", GATE_IP_G3D, 0, 0, 0),
814 GATE(CLK_PPMULCD0, "ppmulcd0", "div_aclk_160", GATE_IP_LCD, 5,
815 CLK_IGNORE_UNUSED, 0),
816 GATE(CLK_SMMUFIMD0, "smmufimd0", "div_aclk_160", GATE_IP_LCD, 4, 0, 0),
817 GATE(CLK_DSIM0, "dsim0", "div_aclk_160", GATE_IP_LCD, 3, 0, 0),
818 GATE(CLK_SMIES, "smies", "div_aclk_160", GATE_IP_LCD, 2, 0, 0),
819 GATE(CLK_MIE0, "mie0", "div_aclk_160", GATE_IP_LCD, 1, 0, 0),
820 GATE(CLK_FIMD0, "fimd0", "div_aclk_160", GATE_IP_LCD, 0, 0, 0),
823 GATE(CLK_TSADC, "tsadc", "div_aclk_200", GATE_IP_FSYS, 20, 0, 0),
824 GATE(CLK_PPMUFILE, "ppmufile", "div_aclk_200", GATE_IP_FSYS, 17,
825 CLK_IGNORE_UNUSED, 0),
826 GATE(CLK_NFCON, "nfcon", "div_aclk_200", GATE_IP_FSYS, 16, 0, 0),
827 GATE(CLK_USBDEVICE, "usbdevice", "div_aclk_200", GATE_IP_FSYS, 13,
829 GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
830 GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
831 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
832 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
833 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
834 GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
835 GATE(CLK_PDMA0, "pdma0", "div_aclk_200", GATE_IP_FSYS, 0, 0, 0),
838 GATE(CLK_SPDIF, "spdif", "div_aclk_100", GATE_IP_PERIL, 26, 0, 0),
839 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
840 GATE(CLK_PCM2, "pcm2", "div_aclk_100", GATE_IP_PERIL, 23, 0, 0),
841 GATE(CLK_PCM1, "pcm1", "div_aclk_100", GATE_IP_PERIL, 22, 0, 0),
842 GATE(CLK_I2S1, "i2s1", "div_aclk_100", GATE_IP_PERIL, 20, 0, 0),
843 GATE(CLK_SPI2, "spi2", "div_aclk_100", GATE_IP_PERIL, 18, 0, 0),
844 GATE(CLK_SPI1, "spi1", "div_aclk_100", GATE_IP_PERIL, 17, 0, 0),
845 GATE(CLK_SPI0, "spi0", "div_aclk_100", GATE_IP_PERIL, 16, 0, 0),
846 GATE(CLK_I2CHDMI, "i2chdmi", "div_aclk_100", GATE_IP_PERIL, 14, 0, 0),
847 GATE(CLK_I2C7, "i2c7", "div_aclk_100", GATE_IP_PERIL, 13, 0, 0),
848 GATE(CLK_I2C6, "i2c6", "div_aclk_100", GATE_IP_PERIL, 12, 0, 0),
849 GATE(CLK_I2C5, "i2c5", "div_aclk_100", GATE_IP_PERIL, 11, 0, 0),
850 GATE(CLK_I2C4, "i2c4", "div_aclk_100", GATE_IP_PERIL, 10, 0, 0),
851 GATE(CLK_I2C3, "i2c3", "div_aclk_100", GATE_IP_PERIL, 9, 0, 0),
852 GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
853 GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
854 GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
855 GATE(CLK_UART3, "uart3", "div_aclk_100", GATE_IP_PERIL, 3, 0, 0),
856 GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
857 GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
858 GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
862 * APLL & MPLL & BPLL & ISP_PLL & DISP_PLL & G3D_PLL
864 static struct samsung_pll_rate_table exynos4415_pll_rates[] = {
865 PLL_35XX_RATE(1600000000, 400, 3, 1),
866 PLL_35XX_RATE(1500000000, 250, 2, 1),
867 PLL_35XX_RATE(1400000000, 175, 3, 0),
868 PLL_35XX_RATE(1300000000, 325, 3, 1),
869 PLL_35XX_RATE(1200000000, 400, 4, 1),
870 PLL_35XX_RATE(1100000000, 275, 3, 1),
871 PLL_35XX_RATE(1066000000, 533, 6, 1),
872 PLL_35XX_RATE(1000000000, 250, 3, 1),
873 PLL_35XX_RATE(960000000, 320, 4, 1),
874 PLL_35XX_RATE(900000000, 300, 4, 1),
875 PLL_35XX_RATE(850000000, 425, 6, 1),
876 PLL_35XX_RATE(800000000, 200, 3, 1),
877 PLL_35XX_RATE(700000000, 175, 3, 1),
878 PLL_35XX_RATE(667000000, 667, 12, 1),
879 PLL_35XX_RATE(600000000, 400, 4, 2),
880 PLL_35XX_RATE(550000000, 275, 3, 2),
881 PLL_35XX_RATE(533000000, 533, 6, 2),
882 PLL_35XX_RATE(520000000, 260, 3, 2),
883 PLL_35XX_RATE(500000000, 250, 3, 2),
884 PLL_35XX_RATE(440000000, 220, 3, 2),
885 PLL_35XX_RATE(400000000, 200, 3, 2),
886 PLL_35XX_RATE(350000000, 175, 3, 2),
887 PLL_35XX_RATE(300000000, 300, 3, 3),
888 PLL_35XX_RATE(266000000, 266, 3, 3),
889 PLL_35XX_RATE(200000000, 200, 3, 3),
890 PLL_35XX_RATE(160000000, 160, 3, 3),
891 PLL_35XX_RATE(100000000, 200, 3, 4),
896 static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
897 PLL_36XX_RATE(800000000, 200, 3, 1, 0),
898 PLL_36XX_RATE(288000000, 96, 2, 2, 0),
899 PLL_36XX_RATE(192000000, 128, 2, 3, 0),
900 PLL_36XX_RATE(144000000, 96, 2, 3, 0),
901 PLL_36XX_RATE(96000000, 128, 2, 4, 0),
902 PLL_36XX_RATE(84000000, 112, 2, 4, 0),
903 PLL_36XX_RATE(80750011, 107, 2, 4, 43691),
904 PLL_36XX_RATE(73728004, 98, 2, 4, 19923),
905 PLL_36XX_RATE(67987602, 271, 3, 5, 62285),
906 PLL_36XX_RATE(65911004, 175, 2, 5, 49982),
907 PLL_36XX_RATE(50000000, 200, 3, 5, 0),
908 PLL_36XX_RATE(49152003, 131, 2, 5, 4719),
909 PLL_36XX_RATE(48000000, 128, 2, 5, 0),
910 PLL_36XX_RATE(45250000, 181, 3, 5, 0),
914 static struct samsung_pll_clock exynos4415_plls[] __initdata = {
915 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
916 APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
917 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
918 EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates),
919 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
920 G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates),
921 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
922 ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates),
923 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
924 "fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
927 static struct samsung_cmu_info cmu_info __initdata = {
928 .pll_clks = exynos4415_plls,
929 .nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
930 .mux_clks = exynos4415_mux_clks,
931 .nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
932 .div_clks = exynos4415_div_clks,
933 .nr_div_clks = ARRAY_SIZE(exynos4415_div_clks),
934 .gate_clks = exynos4415_gate_clks,
935 .nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks),
936 .fixed_clks = exynos4415_fixed_rate_clks,
937 .nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks),
938 .fixed_factor_clks = exynos4415_fixed_factor_clks,
939 .nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks),
940 .nr_clk_ids = CLK_NR_CLKS,
941 .clk_regs = exynos4415_cmu_clk_regs,
942 .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs),
945 static void __init exynos4415_cmu_init(struct device_node *np)
947 samsung_cmu_register_one(np, &cmu_info);
949 CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
955 #define MPLL_LOCK 0x008
956 #define MPLL_CON0 0x108
957 #define MPLL_CON1 0x10c
958 #define MPLL_CON2 0x110
959 #define BPLL_LOCK 0x118
960 #define BPLL_CON0 0x218
961 #define BPLL_CON1 0x21c
962 #define BPLL_CON2 0x220
963 #define SRC_DMC 0x300
964 #define DIV_DMC1 0x504
966 static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
979 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
980 PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
981 PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
983 static struct samsung_mux_clock exynos4415_dmc_mux_clks[] __initdata = {
984 MUX(CLK_DMC_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_DMC, 12, 1),
985 MUX(CLK_DMC_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_DMC, 10, 1),
986 MUX(CLK_DMC_MOUT_DPHY, "mout_dphy", mbpll_p, SRC_DMC, 8, 1),
987 MUX(CLK_DMC_MOUT_DMC_BUS, "mout_dmc_bus", mbpll_p, SRC_DMC, 4, 1),
990 static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
991 DIV(CLK_DMC_DIV_DMC, "div_dmc", "div_dmc_pre", DIV_DMC1, 27, 3),
992 DIV(CLK_DMC_DIV_DPHY, "div_dphy", "mout_dphy", DIV_DMC1, 23, 3),
993 DIV(CLK_DMC_DIV_DMC_PRE, "div_dmc_pre", "mout_dmc_bus",
995 DIV(CLK_DMC_DIV_DMCP, "div_dmcp", "div_dmcd", DIV_DMC1, 15, 3),
996 DIV(CLK_DMC_DIV_DMCD, "div_dmcd", "div_dmc", DIV_DMC1, 11, 3),
997 DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
1000 static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = {
1001 PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1002 MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
1003 PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
1004 BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
1007 static struct samsung_cmu_info cmu_dmc_info __initdata = {
1008 .pll_clks = exynos4415_dmc_plls,
1009 .nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
1010 .mux_clks = exynos4415_dmc_mux_clks,
1011 .nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks),
1012 .div_clks = exynos4415_dmc_div_clks,
1013 .nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks),
1014 .nr_clk_ids = NR_CLKS_DMC,
1015 .clk_regs = exynos4415_cmu_dmc_clk_regs,
1016 .nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs),
1019 static void __init exynos4415_cmu_dmc_init(struct device_node *np)
1021 samsung_cmu_register_one(np, &cmu_dmc_info);
1023 CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
1024 exynos4415_cmu_dmc_init);