2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
30 #include <linux/clk-provider.h>
34 #define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
37 /* register positions shared by RK2928, RK3036, RK3066, RK3188 and RK3228 */
38 #define RK2928_PLL_CON(x) ((x) * 0x4)
39 #define RK2928_MODE_CON 0x40
40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
41 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
42 #define RK2928_GLB_SRST_FST 0x100
43 #define RK2928_GLB_SRST_SND 0x104
44 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
45 #define RK2928_MISC_CON 0x134
47 #define RK3036_SDMMC_CON0 0x144
48 #define RK3036_SDMMC_CON1 0x148
49 #define RK3036_SDIO_CON0 0x14c
50 #define RK3036_SDIO_CON1 0x150
51 #define RK3036_EMMC_CON0 0x154
52 #define RK3036_EMMC_CON1 0x158
54 #define RK3228_GLB_SRST_FST 0x1f0
55 #define RK3228_GLB_SRST_SND 0x1f4
56 #define RK3228_SDMMC_CON0 0x1c0
57 #define RK3228_SDMMC_CON1 0x1c4
58 #define RK3228_SDIO_CON0 0x1c8
59 #define RK3228_SDIO_CON1 0x1cc
60 #define RK3228_EMMC_CON0 0x1d8
61 #define RK3228_EMMC_CON1 0x1dc
63 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
64 #define RK3288_MODE_CON 0x50
65 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
66 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
67 #define RK3288_GLB_SRST_FST 0x1b0
68 #define RK3288_GLB_SRST_SND 0x1b4
69 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
70 #define RK3288_MISC_CON 0x1e8
71 #define RK3288_SDMMC_CON0 0x200
72 #define RK3288_SDMMC_CON1 0x204
73 #define RK3288_SDIO0_CON0 0x208
74 #define RK3288_SDIO0_CON1 0x20c
75 #define RK3288_SDIO1_CON0 0x210
76 #define RK3288_SDIO1_CON1 0x214
77 #define RK3288_EMMC_CON0 0x218
78 #define RK3288_EMMC_CON1 0x21c
80 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
81 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
82 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
83 #define RK3368_GLB_SRST_FST 0x280
84 #define RK3368_GLB_SRST_SND 0x284
85 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
86 #define RK3368_MISC_CON 0x380
87 #define RK3368_SDMMC_CON0 0x400
88 #define RK3368_SDMMC_CON1 0x404
89 #define RK3368_SDIO0_CON0 0x408
90 #define RK3368_SDIO0_CON1 0x40c
91 #define RK3368_SDIO1_CON0 0x410
92 #define RK3368_SDIO1_CON1 0x414
93 #define RK3368_EMMC_CON0 0x418
94 #define RK3368_EMMC_CON1 0x41c
96 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
97 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
98 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
99 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
100 #define RK3399_GLB_SRST_FST 0x500
101 #define RK3399_GLB_SRST_SND 0x504
102 #define RK3399_GLB_CNT_TH 0x508
103 #define RK3399_MISC_CON 0x50c
104 #define RK3399_RST_CON 0x510
105 #define RK3399_RST_ST 0x514
106 #define RK3399_SDMMC_CON0 0x580
107 #define RK3399_SDMMC_CON1 0x584
108 #define RK3399_SDIO_CON0 0x588
109 #define RK3399_SDIO_CON1 0x58c
111 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
112 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
113 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
114 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
115 #define RK3399_PMU_RSTNHOLD_CON(x) ((x) * 0x4 + 0x120)
116 #define RK3399_PMU_GATEDIS_CON(x) ((x) * 0x4 + 0x130)
118 enum rockchip_pll_type {
125 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
126 _postdiv2, _dsmpd, _frac) \
130 .postdiv1 = _postdiv1, \
132 .postdiv2 = _postdiv2, \
137 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
143 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
146 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
156 * struct rockchip_clk_provider - information about clock provider
157 * @reg_base: virtual address for the register base.
158 * @clk_data: holds clock related data like clk* and number of clocks.
159 * @cru_node: device-node of the clock-provider
160 * @grf: regmap of the general-register-files syscon
161 * @lock: maintains exclusion between callbacks for a given clock-provider.
163 struct rockchip_clk_provider {
164 void __iomem *reg_base;
165 struct clk_onecell_data clk_data;
166 struct device_node *cru_node;
171 struct rockchip_pll_rate_table {
177 /* for RK3036/RK3399 */
179 unsigned int postdiv1;
181 unsigned int postdiv2;
187 * struct rockchip_pll_clock - information about pll clock
188 * @id: platform specific id of the clock.
189 * @name: name of this pll clock.
190 * @parent_names: name of the parent clock.
191 * @num_parents: number of parents
192 * @flags: optional flags for basic clock.
193 * @con_offset: offset of the register for configuring the PLL.
194 * @mode_offset: offset of the register for configuring the PLL-mode.
195 * @mode_shift: offset inside the mode-register for the mode of this pll.
196 * @lock_shift: offset inside the lock register for the lock status.
197 * @type: Type of PLL to be registered.
198 * @pll_flags: hardware-specific flags
199 * @rate_table: Table of usable pll rates
202 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
203 * rate_table parameters and ajust them if necessary.
205 struct rockchip_pll_clock {
208 const char *const *parent_names;
215 enum rockchip_pll_type type;
217 struct rockchip_pll_rate_table *rate_table;
220 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
222 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
223 _lshift, _pflags, _rtable) \
228 .parent_names = _pnames, \
229 .num_parents = ARRAY_SIZE(_pnames), \
230 .flags = CLK_GET_RATE_NOCACHE | _flags, \
231 .con_offset = _con, \
232 .mode_offset = _mode, \
233 .mode_shift = _mshift, \
234 .lock_shift = _lshift, \
235 .pll_flags = _pflags, \
236 .rate_table = _rtable, \
239 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
240 enum rockchip_pll_type pll_type,
241 const char *name, const char *const *parent_names,
242 u8 num_parents, int con_offset, int grf_lock_offset,
243 int lock_shift, int mode_offset, int mode_shift,
244 struct rockchip_pll_rate_table *rate_table,
245 unsigned long flags, u8 clk_pll_flags);
247 struct rockchip_cpuclk_clksel {
252 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
253 struct rockchip_cpuclk_rate_table {
255 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
259 * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
260 * @core_reg: register offset of the core settings register
261 * @div_core_shift: core divider offset used to divide the pll value
262 * @div_core_mask: core divider mask
263 * @mux_core_alt: mux value to select alternate parent
264 * @mux_core_main: mux value to select main parent of core
265 * @mux_core_shift: offset of the core multiplexer
266 * @mux_core_mask: core multiplexer mask
268 struct rockchip_cpuclk_reg_data {
278 struct clk *rockchip_clk_register_cpuclk(const char *name,
279 const char *const *parent_names, u8 num_parents,
280 const struct rockchip_cpuclk_reg_data *reg_data,
281 const struct rockchip_cpuclk_rate_table *rates,
282 int nrates, void __iomem *reg_base, spinlock_t *lock);
284 struct clk *rockchip_clk_register_mmc(const char *name,
285 const char *const *parent_names, u8 num_parents,
286 void __iomem *reg, int shift);
289 * for COMPOSITE_DDRCLK div_flag,
290 * there may have serval ways to set ddr clock, use
291 * this flag to distinguish them.
292 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
294 #define ROCKCHIP_DDRCLK_SIP 0x01
296 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
297 const char *const *parent_names,
298 u8 num_parents, int mux_offset,
299 int mux_shift, int mux_width,
300 int div_shift, int div_width,
301 int ddr_flags, void __iomem *reg_base,
304 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
306 struct clk *rockchip_clk_register_inverter(const char *name,
307 const char *const *parent_names, u8 num_parents,
308 void __iomem *reg, int shift, int flags,
311 #define PNAME(x) static const char *const x[] __initconst
313 enum rockchip_clk_branch_type {
317 branch_fraction_divider,
325 struct rockchip_clk_branch {
327 enum rockchip_clk_branch_type branch_type;
329 const char *const *parent_names;
339 struct clk_div_table *div_table;
343 struct rockchip_clk_branch *child;
346 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
350 .branch_type = branch_composite, \
352 .parent_names = pnames, \
353 .num_parents = ARRAY_SIZE(pnames), \
355 .muxdiv_offset = mo, \
367 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
371 .branch_type = branch_composite, \
373 .parent_names = (const char *[]){ pname }, \
376 .muxdiv_offset = mo, \
385 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
386 df, dt, go, gs, gf) \
389 .branch_type = branch_composite, \
391 .parent_names = (const char *[]){ pname }, \
394 .muxdiv_offset = mo, \
404 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
408 .branch_type = branch_composite, \
410 .parent_names = pnames, \
411 .num_parents = ARRAY_SIZE(pnames), \
413 .muxdiv_offset = mo, \
422 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
426 .branch_type = branch_composite, \
428 .parent_names = pnames, \
429 .num_parents = ARRAY_SIZE(pnames), \
431 .muxdiv_offset = mo, \
441 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
442 mw, mf, ds, dw, df, dt) \
445 .branch_type = branch_composite, \
447 .parent_names = pnames, \
448 .num_parents = ARRAY_SIZE(pnames), \
450 .muxdiv_offset = mo, \
461 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
464 .branch_type = branch_fraction_divider, \
466 .parent_names = (const char *[]){ pname }, \
469 .muxdiv_offset = mo, \
478 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
481 .branch_type = branch_fraction_divider, \
483 .parent_names = (const char *[]){ pname }, \
486 .muxdiv_offset = mo, \
496 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
499 .branch_type = branch_fraction_divider, \
501 .parent_names = (const char *[]){ pname }, \
504 .muxdiv_offset = mo, \
512 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
516 .branch_type = branch_ddrc, \
518 .parent_names = pnames, \
519 .num_parents = ARRAY_SIZE(pnames), \
521 .muxdiv_offset = mo, \
530 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
533 .branch_type = branch_mux, \
535 .parent_names = pnames, \
536 .num_parents = ARRAY_SIZE(pnames), \
538 .muxdiv_offset = o, \
545 #define DIV(_id, cname, pname, f, o, s, w, df) \
548 .branch_type = branch_divider, \
550 .parent_names = (const char *[]){ pname }, \
553 .muxdiv_offset = o, \
560 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
563 .branch_type = branch_divider, \
565 .parent_names = (const char *[]){ pname }, \
568 .muxdiv_offset = o, \
575 #define GATE(_id, cname, pname, f, o, b, gf) \
578 .branch_type = branch_gate, \
580 .parent_names = (const char *[]){ pname }, \
588 #define MMC(_id, cname, pname, offset, shift) \
591 .branch_type = branch_mmc, \
593 .parent_names = (const char *[]){ pname }, \
595 .muxdiv_offset = offset, \
596 .div_shift = shift, \
599 #define INVERTER(_id, cname, pname, io, is, if) \
602 .branch_type = branch_inverter, \
604 .parent_names = (const char *[]){ pname }, \
606 .muxdiv_offset = io, \
611 #define FACTOR(_id, cname, pname, f, fm, fd) \
614 .branch_type = branch_factor, \
616 .parent_names = (const char *[]){ pname }, \
623 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
626 .branch_type = branch_factor, \
628 .parent_names = (const char *[]){ pname }, \
638 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
639 void __iomem *base, unsigned long nr_clks);
640 void rockchip_clk_of_add_provider(struct device_node *np,
641 struct rockchip_clk_provider *ctx);
642 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
643 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
644 struct clk *clk, unsigned int id);
645 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
646 struct rockchip_clk_branch *list,
647 unsigned int nr_clk);
648 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
649 struct rockchip_pll_clock *pll_list,
650 unsigned int nr_pll, int grf_lock_offset);
651 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
652 unsigned int lookup_id, const char *name,
653 const char *const *parent_names, u8 num_parents,
654 const struct rockchip_cpuclk_reg_data *reg_data,
655 const struct rockchip_cpuclk_rate_table *rates,
657 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
658 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
659 unsigned int reg, void (*cb)(void));
661 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
663 #ifdef CONFIG_RESET_CONTROLLER
664 void rockchip_register_softrst(struct device_node *np,
665 unsigned int num_regs,
666 void __iomem *base, u8 flags);
668 static inline void rockchip_register_softrst(struct device_node *np,
669 unsigned int num_regs,
670 void __iomem *base, u8 flags)