2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
33 #define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16))
36 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
37 #define RK2928_PLL_CON(x) ((x) * 0x4)
38 #define RK2928_MODE_CON 0x40
39 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
40 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
41 #define RK2928_GLB_SRST_FST 0x100
42 #define RK2928_GLB_SRST_SND 0x104
43 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
44 #define RK2928_MISC_CON 0x134
46 #define RK3036_SDMMC_CON0 0x144
47 #define RK3036_SDMMC_CON1 0x148
48 #define RK3036_SDIO_CON0 0x14c
49 #define RK3036_SDIO_CON1 0x150
50 #define RK3036_EMMC_CON0 0x154
51 #define RK3036_EMMC_CON1 0x158
53 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
54 #define RK3288_MODE_CON 0x50
55 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
56 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
57 #define RK3288_GLB_SRST_FST 0x1b0
58 #define RK3288_GLB_SRST_SND 0x1b4
59 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
60 #define RK3288_MISC_CON 0x1e8
61 #define RK3288_SDMMC_CON0 0x200
62 #define RK3288_SDMMC_CON1 0x204
63 #define RK3288_SDIO0_CON0 0x208
64 #define RK3288_SDIO0_CON1 0x20c
65 #define RK3288_SDIO1_CON0 0x210
66 #define RK3288_SDIO1_CON1 0x214
67 #define RK3288_EMMC_CON0 0x218
68 #define RK3288_EMMC_CON1 0x21c
70 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
71 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
72 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
73 #define RK3368_GLB_SRST_FST 0x280
74 #define RK3368_GLB_SRST_SND 0x284
75 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
76 #define RK3368_MISC_CON 0x380
77 #define RK3368_SDMMC_CON0 0x400
78 #define RK3368_SDMMC_CON1 0x404
79 #define RK3368_SDIO0_CON0 0x408
80 #define RK3368_SDIO0_CON1 0x40c
81 #define RK3368_SDIO1_CON0 0x410
82 #define RK3368_SDIO1_CON1 0x414
83 #define RK3368_EMMC_CON0 0x418
84 #define RK3368_EMMC_CON1 0x41c
86 enum rockchip_pll_type {
92 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
93 _postdiv2, _dsmpd, _frac) \
97 .postdiv1 = _postdiv1, \
99 .postdiv2 = _postdiv2, \
104 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
110 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
113 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
122 struct rockchip_pll_rate_table {
130 unsigned int postdiv1;
132 unsigned int postdiv2;
138 * struct rockchip_pll_clock: information about pll clock
139 * @id: platform specific id of the clock.
140 * @name: name of this pll clock.
141 * @parent_name: name of the parent clock.
142 * @flags: optional flags for basic clock.
143 * @con_offset: offset of the register for configuring the PLL.
144 * @mode_offset: offset of the register for configuring the PLL-mode.
145 * @mode_shift: offset inside the mode-register for the mode of this pll.
146 * @lock_shift: offset inside the lock register for the lock status.
147 * @type: Type of PLL to be registered.
148 * @pll_flags: hardware-specific flags
149 * @rate_table: Table of usable pll rates
152 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
153 * rate_table parameters and ajust them if necessary.
155 struct rockchip_pll_clock {
158 const char *const *parent_names;
165 enum rockchip_pll_type type;
167 struct rockchip_pll_rate_table *rate_table;
170 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
172 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
173 _lshift, _pflags, _rtable) \
178 .parent_names = _pnames, \
179 .num_parents = ARRAY_SIZE(_pnames), \
180 .flags = CLK_GET_RATE_NOCACHE | _flags, \
181 .con_offset = _con, \
182 .mode_offset = _mode, \
183 .mode_shift = _mshift, \
184 .lock_shift = _lshift, \
185 .pll_flags = _pflags, \
186 .rate_table = _rtable, \
189 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
190 const char *name, const char *const *parent_names,
191 u8 num_parents, void __iomem *base, int con_offset,
192 int grf_lock_offset, int lock_shift, int reg_mode,
193 int mode_shift, struct rockchip_pll_rate_table *rate_table,
194 u8 clk_pll_flags, spinlock_t *lock);
196 struct rockchip_cpuclk_clksel {
201 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
202 struct rockchip_cpuclk_rate_table {
204 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
208 * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
209 * @core_reg: register offset of the core settings register
210 * @div_core_shift: core divider offset used to divide the pll value
211 * @div_core_mask: core divider mask
212 * @mux_core_alt: mux value to select alternate parent
213 * @mux_core_main: mux value to select main parent of core
214 * @mux_core_shift: offset of the core multiplexer
215 * @mux_core_mask: core multiplexer mask
217 struct rockchip_cpuclk_reg_data {
228 struct clk *rockchip_clk_register_cpuclk(const char *name,
229 const char *const *parent_names, u8 num_parents,
230 const struct rockchip_cpuclk_reg_data *reg_data,
231 const struct rockchip_cpuclk_rate_table *rates,
232 int nrates, void __iomem *reg_base, spinlock_t *lock);
234 struct clk *rockchip_clk_register_mmc(const char *name,
235 const char *const *parent_names, u8 num_parents,
236 void __iomem *reg, int shift);
238 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
240 struct clk *rockchip_clk_register_inverter(const char *name,
241 const char *const *parent_names, u8 num_parents,
242 void __iomem *reg, int shift, int flags,
245 #define PNAME(x) static const char *const x[] __initconst
247 enum rockchip_clk_branch_type {
251 branch_fraction_divider,
258 struct rockchip_clk_branch {
260 enum rockchip_clk_branch_type branch_type;
262 const char *const *parent_names;
272 struct clk_div_table *div_table;
276 struct rockchip_clk_branch *child;
279 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
283 .branch_type = branch_composite, \
285 .parent_names = pnames, \
286 .num_parents = ARRAY_SIZE(pnames), \
288 .muxdiv_offset = mo, \
300 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
304 .branch_type = branch_composite, \
306 .parent_names = (const char *[]){ pname }, \
309 .muxdiv_offset = mo, \
318 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
319 df, dt, go, gs, gf) \
322 .branch_type = branch_composite, \
324 .parent_names = (const char *[]){ pname }, \
327 .muxdiv_offset = mo, \
337 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
341 .branch_type = branch_composite, \
343 .parent_names = pnames, \
344 .num_parents = ARRAY_SIZE(pnames), \
346 .muxdiv_offset = mo, \
355 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
359 .branch_type = branch_composite, \
361 .parent_names = pnames, \
362 .num_parents = ARRAY_SIZE(pnames), \
364 .muxdiv_offset = mo, \
374 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
375 mw, mf, ds, dw, df, dt) \
378 .branch_type = branch_composite, \
380 .parent_names = pnames, \
381 .num_parents = ARRAY_SIZE(pnames), \
383 .muxdiv_offset = mo, \
394 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
397 .branch_type = branch_fraction_divider, \
399 .parent_names = (const char *[]){ pname }, \
402 .muxdiv_offset = mo, \
411 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
414 .branch_type = branch_fraction_divider, \
416 .parent_names = (const char *[]){ pname }, \
419 .muxdiv_offset = mo, \
429 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
432 .branch_type = branch_fraction_divider, \
434 .parent_names = (const char *[]){ pname }, \
437 .muxdiv_offset = mo, \
445 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
448 .branch_type = branch_mux, \
450 .parent_names = pnames, \
451 .num_parents = ARRAY_SIZE(pnames), \
453 .muxdiv_offset = o, \
460 #define DIV(_id, cname, pname, f, o, s, w, df) \
463 .branch_type = branch_divider, \
465 .parent_names = (const char *[]){ pname }, \
468 .muxdiv_offset = o, \
475 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
478 .branch_type = branch_divider, \
480 .parent_names = (const char *[]){ pname }, \
483 .muxdiv_offset = o, \
490 #define GATE(_id, cname, pname, f, o, b, gf) \
493 .branch_type = branch_gate, \
495 .parent_names = (const char *[]){ pname }, \
503 #define MMC(_id, cname, pname, offset, shift) \
506 .branch_type = branch_mmc, \
508 .parent_names = (const char *[]){ pname }, \
510 .muxdiv_offset = offset, \
511 .div_shift = shift, \
514 #define INVERTER(_id, cname, pname, io, is, if) \
517 .branch_type = branch_inverter, \
519 .parent_names = (const char *[]){ pname }, \
521 .muxdiv_offset = io, \
526 #define FACTOR(_id, cname, pname, f, fm, fd) \
529 .branch_type = branch_factor, \
531 .parent_names = (const char *[]){ pname }, \
538 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
541 .branch_type = branch_factor, \
543 .parent_names = (const char *[]){ pname }, \
553 void rockchip_clk_init(struct device_node *np, void __iomem *base,
554 unsigned long nr_clks);
555 struct regmap *rockchip_clk_get_grf(void);
556 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
557 void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
558 unsigned int nr_clk);
559 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
560 unsigned int nr_pll, int grf_lock_offset);
561 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
562 const char *const *parent_names, u8 num_parents,
563 const struct rockchip_cpuclk_reg_data *reg_data,
564 const struct rockchip_cpuclk_rate_table *rates,
566 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
567 void rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void));
569 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
571 #ifdef CONFIG_RESET_CONTROLLER
572 void rockchip_register_softrst(struct device_node *np,
573 unsigned int num_regs,
574 void __iomem *base, u8 flags);
576 static inline void rockchip_register_softrst(struct device_node *np,
577 unsigned int num_regs,
578 void __iomem *base, u8 flags)