2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
30 #include <linux/clk-provider.h>
34 #define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
37 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
38 #define RK2928_PLL_CON(x) ((x) * 0x4)
39 #define RK2928_MODE_CON 0x40
40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
41 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
42 #define RK2928_GLB_SRST_FST 0x100
43 #define RK2928_GLB_SRST_SND 0x104
44 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
45 #define RK2928_MISC_CON 0x134
47 #define RK3036_SDMMC_CON0 0x144
48 #define RK3036_SDMMC_CON1 0x148
49 #define RK3036_SDIO_CON0 0x14c
50 #define RK3036_SDIO_CON1 0x150
51 #define RK3036_EMMC_CON0 0x154
52 #define RK3036_EMMC_CON1 0x158
54 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
55 #define RK3288_MODE_CON 0x50
56 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
57 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
58 #define RK3288_GLB_SRST_FST 0x1b0
59 #define RK3288_GLB_SRST_SND 0x1b4
60 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
61 #define RK3288_MISC_CON 0x1e8
62 #define RK3288_SDMMC_CON0 0x200
63 #define RK3288_SDMMC_CON1 0x204
64 #define RK3288_SDIO0_CON0 0x208
65 #define RK3288_SDIO0_CON1 0x20c
66 #define RK3288_SDIO1_CON0 0x210
67 #define RK3288_SDIO1_CON1 0x214
68 #define RK3288_EMMC_CON0 0x218
69 #define RK3288_EMMC_CON1 0x21c
71 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
72 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
73 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
74 #define RK3368_GLB_SRST_FST 0x280
75 #define RK3368_GLB_SRST_SND 0x284
76 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
77 #define RK3368_MISC_CON 0x380
78 #define RK3368_SDMMC_CON0 0x400
79 #define RK3368_SDMMC_CON1 0x404
80 #define RK3368_SDIO0_CON0 0x408
81 #define RK3368_SDIO0_CON1 0x40c
82 #define RK3368_SDIO1_CON0 0x410
83 #define RK3368_SDIO1_CON1 0x414
84 #define RK3368_EMMC_CON0 0x418
85 #define RK3368_EMMC_CON1 0x41c
87 enum rockchip_pll_type {
94 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
95 _postdiv2, _dsmpd, _frac) \
99 .postdiv1 = _postdiv1, \
101 .postdiv2 = _postdiv2, \
106 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
112 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
115 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
124 #define RK3399_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
125 _postdiv2, _dsmpd, _frac) \
129 .postdiv1 = _postdiv1, \
131 .postdiv2 = _postdiv2, \
137 * struct rockchip_clk_provider - information about clock provider
138 * @reg_base: virtual address for the register base.
139 * @clk_data: holds clock related data like clk* and number of clocks.
140 * @cru_node: device-node of the clock-provider
141 * @grf: regmap of the general-register-files syscon
142 * @lock: maintains exclusion between callbacks for a given clock-provider.
144 struct rockchip_clk_provider {
145 void __iomem *reg_base;
146 struct clk_onecell_data clk_data;
147 struct device_node *cru_node;
152 struct rockchip_pll_rate_table {
158 /* for RK3036/RK3399 */
160 unsigned int postdiv1;
162 unsigned int postdiv2;
168 * struct rockchip_pll_clock - information about pll clock
169 * @id: platform specific id of the clock.
170 * @name: name of this pll clock.
171 * @parent_names: name of the parent clock.
172 * @num_parents: number of parents
173 * @flags: optional flags for basic clock.
174 * @con_offset: offset of the register for configuring the PLL.
175 * @mode_offset: offset of the register for configuring the PLL-mode.
176 * @mode_shift: offset inside the mode-register for the mode of this pll.
177 * @lock_shift: offset inside the lock register for the lock status.
178 * @type: Type of PLL to be registered.
179 * @pll_flags: hardware-specific flags
180 * @rate_table: Table of usable pll rates
183 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
184 * rate_table parameters and ajust them if necessary.
186 struct rockchip_pll_clock {
189 const char *const *parent_names;
196 enum rockchip_pll_type type;
198 struct rockchip_pll_rate_table *rate_table;
201 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
203 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
204 _lshift, _pflags, _rtable) \
209 .parent_names = _pnames, \
210 .num_parents = ARRAY_SIZE(_pnames), \
211 .flags = CLK_GET_RATE_NOCACHE | _flags, \
212 .con_offset = _con, \
213 .mode_offset = _mode, \
214 .mode_shift = _mshift, \
215 .lock_shift = _lshift, \
216 .pll_flags = _pflags, \
217 .rate_table = _rtable, \
220 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
221 enum rockchip_pll_type pll_type,
222 const char *name, const char *const *parent_names,
223 u8 num_parents, int con_offset, int grf_lock_offset,
224 int lock_shift, int mode_offset, int mode_shift,
225 struct rockchip_pll_rate_table *rate_table,
228 struct rockchip_cpuclk_clksel {
233 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
234 struct rockchip_cpuclk_rate_table {
236 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
240 * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
241 * @core_reg: register offset of the core settings register
242 * @div_core_shift: core divider offset used to divide the pll value
243 * @div_core_mask: core divider mask
244 * @mux_core_alt: mux value to select alternate parent
245 * @mux_core_main: mux value to select main parent of core
246 * @mux_core_shift: offset of the core multiplexer
247 * @mux_core_mask: core multiplexer mask
249 struct rockchip_cpuclk_reg_data {
259 struct clk *rockchip_clk_register_cpuclk(const char *name,
260 const char *const *parent_names, u8 num_parents,
261 const struct rockchip_cpuclk_reg_data *reg_data,
262 const struct rockchip_cpuclk_rate_table *rates,
263 int nrates, void __iomem *reg_base, spinlock_t *lock);
265 struct clk *rockchip_clk_register_mmc(const char *name,
266 const char *const *parent_names, u8 num_parents,
267 void __iomem *reg, int shift);
269 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
271 struct clk *rockchip_clk_register_inverter(const char *name,
272 const char *const *parent_names, u8 num_parents,
273 void __iomem *reg, int shift, int flags,
276 #define PNAME(x) static const char *const x[] __initconst
278 enum rockchip_clk_branch_type {
282 branch_fraction_divider,
289 struct rockchip_clk_branch {
291 enum rockchip_clk_branch_type branch_type;
293 const char *const *parent_names;
303 struct clk_div_table *div_table;
307 struct rockchip_clk_branch *child;
310 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
314 .branch_type = branch_composite, \
316 .parent_names = pnames, \
317 .num_parents = ARRAY_SIZE(pnames), \
319 .muxdiv_offset = mo, \
331 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
335 .branch_type = branch_composite, \
337 .parent_names = (const char *[]){ pname }, \
340 .muxdiv_offset = mo, \
349 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
350 df, dt, go, gs, gf) \
353 .branch_type = branch_composite, \
355 .parent_names = (const char *[]){ pname }, \
358 .muxdiv_offset = mo, \
368 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
372 .branch_type = branch_composite, \
374 .parent_names = pnames, \
375 .num_parents = ARRAY_SIZE(pnames), \
377 .muxdiv_offset = mo, \
386 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
390 .branch_type = branch_composite, \
392 .parent_names = pnames, \
393 .num_parents = ARRAY_SIZE(pnames), \
395 .muxdiv_offset = mo, \
405 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
406 mw, mf, ds, dw, df, dt) \
409 .branch_type = branch_composite, \
411 .parent_names = pnames, \
412 .num_parents = ARRAY_SIZE(pnames), \
414 .muxdiv_offset = mo, \
425 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
428 .branch_type = branch_fraction_divider, \
430 .parent_names = (const char *[]){ pname }, \
433 .muxdiv_offset = mo, \
442 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
445 .branch_type = branch_fraction_divider, \
447 .parent_names = (const char *[]){ pname }, \
450 .muxdiv_offset = mo, \
460 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
463 .branch_type = branch_fraction_divider, \
465 .parent_names = (const char *[]){ pname }, \
468 .muxdiv_offset = mo, \
476 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
479 .branch_type = branch_mux, \
481 .parent_names = pnames, \
482 .num_parents = ARRAY_SIZE(pnames), \
484 .muxdiv_offset = o, \
491 #define DIV(_id, cname, pname, f, o, s, w, df) \
494 .branch_type = branch_divider, \
496 .parent_names = (const char *[]){ pname }, \
499 .muxdiv_offset = o, \
506 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
509 .branch_type = branch_divider, \
511 .parent_names = (const char *[]){ pname }, \
514 .muxdiv_offset = o, \
521 #define GATE(_id, cname, pname, f, o, b, gf) \
524 .branch_type = branch_gate, \
526 .parent_names = (const char *[]){ pname }, \
534 #define MMC(_id, cname, pname, offset, shift) \
537 .branch_type = branch_mmc, \
539 .parent_names = (const char *[]){ pname }, \
541 .muxdiv_offset = offset, \
542 .div_shift = shift, \
545 #define INVERTER(_id, cname, pname, io, is, if) \
548 .branch_type = branch_inverter, \
550 .parent_names = (const char *[]){ pname }, \
552 .muxdiv_offset = io, \
557 #define FACTOR(_id, cname, pname, f, fm, fd) \
560 .branch_type = branch_factor, \
562 .parent_names = (const char *[]){ pname }, \
569 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
572 .branch_type = branch_factor, \
574 .parent_names = (const char *[]){ pname }, \
584 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
585 void __iomem *base, unsigned long nr_clks);
586 void rockchip_clk_of_add_provider(struct device_node *np,
587 struct rockchip_clk_provider *ctx);
588 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
589 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
590 struct clk *clk, unsigned int id);
591 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
592 struct rockchip_clk_branch *list,
593 unsigned int nr_clk);
594 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
595 struct rockchip_pll_clock *pll_list,
596 unsigned int nr_pll, int grf_lock_offset);
597 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
598 unsigned int lookup_id, const char *name,
599 const char *const *parent_names, u8 num_parents,
600 const struct rockchip_cpuclk_reg_data *reg_data,
601 const struct rockchip_cpuclk_rate_table *rates,
603 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
604 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
605 unsigned int reg, void (*cb)(void));
607 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
609 #ifdef CONFIG_RESET_CONTROLLER
610 void rockchip_register_softrst(struct device_node *np,
611 unsigned int num_regs,
612 void __iomem *base, u8 flags);
614 static inline void rockchip_register_softrst(struct device_node *np,
615 unsigned int num_regs,
616 void __iomem *base, u8 flags)