2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
30 #include <linux/clk-provider.h>
34 #define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16))
37 /* register positions shared by RK2928, RK3036, RK3066 and RK3188 */
38 #define RK2928_PLL_CON(x) ((x) * 0x4)
39 #define RK2928_MODE_CON 0x40
40 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
41 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
42 #define RK2928_GLB_SRST_FST 0x100
43 #define RK2928_GLB_SRST_SND 0x104
44 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
45 #define RK2928_MISC_CON 0x134
47 #define RK3036_SDMMC_CON0 0x144
48 #define RK3036_SDMMC_CON1 0x148
49 #define RK3036_SDIO_CON0 0x14c
50 #define RK3036_SDIO_CON1 0x150
51 #define RK3036_EMMC_CON0 0x154
52 #define RK3036_EMMC_CON1 0x158
54 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
55 #define RK3288_MODE_CON 0x50
56 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
57 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
58 #define RK3288_GLB_SRST_FST 0x1b0
59 #define RK3288_GLB_SRST_SND 0x1b4
60 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
61 #define RK3288_MISC_CON 0x1e8
62 #define RK3288_SDMMC_CON0 0x200
63 #define RK3288_SDMMC_CON1 0x204
64 #define RK3288_SDIO0_CON0 0x208
65 #define RK3288_SDIO0_CON1 0x20c
66 #define RK3288_SDIO1_CON0 0x210
67 #define RK3288_SDIO1_CON1 0x214
68 #define RK3288_EMMC_CON0 0x218
69 #define RK3288_EMMC_CON1 0x21c
71 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
72 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
73 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
74 #define RK3368_GLB_SRST_FST 0x280
75 #define RK3368_GLB_SRST_SND 0x284
76 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
77 #define RK3368_MISC_CON 0x380
78 #define RK3368_SDMMC_CON0 0x400
79 #define RK3368_SDMMC_CON1 0x404
80 #define RK3368_SDIO0_CON0 0x408
81 #define RK3368_SDIO0_CON1 0x40c
82 #define RK3368_SDIO1_CON0 0x410
83 #define RK3368_SDIO1_CON1 0x414
84 #define RK3368_EMMC_CON0 0x418
85 #define RK3368_EMMC_CON1 0x41c
87 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
88 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
89 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
90 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
91 #define RK3399_GLB_SRST_FST 0x500
92 #define RK3399_GLB_SRST_SND 0x504
93 #define RK3399_GLB_CNT_TH 0x508
94 #define RK3399_MISC_CON 0x50c
95 #define RK3399_RST_CON 0x510
96 #define RK3399_RST_ST 0x514
97 #define RK3399_SDMMC_CON0 0x580
98 #define RK3399_SDMMC_CON1 0x584
99 #define RK3399_SDIO_CON0 0x588
100 #define RK3399_SDIO_CON1 0x58c
102 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
103 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
104 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
105 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
106 #define RK3399_PMU_RSTNHOLD_CON(x) ((x) * 0x4 + 0x120)
107 #define RK3399_PMU_GATEDIS_CON(x) ((x) * 0x4 + 0x130)
109 enum rockchip_pll_type {
116 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
117 _postdiv2, _dsmpd, _frac) \
121 .postdiv1 = _postdiv1, \
123 .postdiv2 = _postdiv2, \
128 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
134 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
137 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
147 * struct rockchip_clk_provider - information about clock provider
148 * @reg_base: virtual address for the register base.
149 * @clk_data: holds clock related data like clk* and number of clocks.
150 * @cru_node: device-node of the clock-provider
151 * @grf: regmap of the general-register-files syscon
152 * @lock: maintains exclusion between callbacks for a given clock-provider.
154 struct rockchip_clk_provider {
155 void __iomem *reg_base;
156 struct clk_onecell_data clk_data;
157 struct device_node *cru_node;
162 struct rockchip_pll_rate_table {
168 /* for RK3036/RK3399 */
170 unsigned int postdiv1;
172 unsigned int postdiv2;
178 * struct rockchip_pll_clock - information about pll clock
179 * @id: platform specific id of the clock.
180 * @name: name of this pll clock.
181 * @parent_names: name of the parent clock.
182 * @num_parents: number of parents
183 * @flags: optional flags for basic clock.
184 * @con_offset: offset of the register for configuring the PLL.
185 * @mode_offset: offset of the register for configuring the PLL-mode.
186 * @mode_shift: offset inside the mode-register for the mode of this pll.
187 * @lock_shift: offset inside the lock register for the lock status.
188 * @type: Type of PLL to be registered.
189 * @pll_flags: hardware-specific flags
190 * @rate_table: Table of usable pll rates
193 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
194 * rate_table parameters and ajust them if necessary.
196 struct rockchip_pll_clock {
199 const char *const *parent_names;
206 enum rockchip_pll_type type;
208 struct rockchip_pll_rate_table *rate_table;
211 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
213 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
214 _lshift, _pflags, _rtable) \
219 .parent_names = _pnames, \
220 .num_parents = ARRAY_SIZE(_pnames), \
221 .flags = CLK_GET_RATE_NOCACHE | _flags, \
222 .con_offset = _con, \
223 .mode_offset = _mode, \
224 .mode_shift = _mshift, \
225 .lock_shift = _lshift, \
226 .pll_flags = _pflags, \
227 .rate_table = _rtable, \
230 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
231 enum rockchip_pll_type pll_type,
232 const char *name, const char *const *parent_names,
233 u8 num_parents, int con_offset, int grf_lock_offset,
234 int lock_shift, int mode_offset, int mode_shift,
235 struct rockchip_pll_rate_table *rate_table,
238 struct rockchip_cpuclk_clksel {
243 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
244 struct rockchip_cpuclk_rate_table {
246 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
250 * struct rockchip_cpuclk_reg_data - describes register offsets and masks of the cpuclock
251 * @core_reg: register offset of the core settings register
252 * @div_core_shift: core divider offset used to divide the pll value
253 * @div_core_mask: core divider mask
254 * @mux_core_alt: mux value to select alternate parent
255 * @mux_core_main: mux value to select main parent of core
256 * @mux_core_shift: offset of the core multiplexer
257 * @mux_core_mask: core multiplexer mask
259 struct rockchip_cpuclk_reg_data {
269 struct clk *rockchip_clk_register_cpuclk(const char *name,
270 const char *const *parent_names, u8 num_parents,
271 const struct rockchip_cpuclk_reg_data *reg_data,
272 const struct rockchip_cpuclk_rate_table *rates,
273 int nrates, void __iomem *reg_base, spinlock_t *lock);
275 struct clk *rockchip_clk_register_mmc(const char *name,
276 const char *const *parent_names, u8 num_parents,
277 void __iomem *reg, int shift);
279 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
281 struct clk *rockchip_clk_register_inverter(const char *name,
282 const char *const *parent_names, u8 num_parents,
283 void __iomem *reg, int shift, int flags,
286 #define PNAME(x) static const char *const x[] __initconst
288 enum rockchip_clk_branch_type {
292 branch_fraction_divider,
299 struct rockchip_clk_branch {
301 enum rockchip_clk_branch_type branch_type;
303 const char *const *parent_names;
313 struct clk_div_table *div_table;
317 struct rockchip_clk_branch *child;
320 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
324 .branch_type = branch_composite, \
326 .parent_names = pnames, \
327 .num_parents = ARRAY_SIZE(pnames), \
329 .muxdiv_offset = mo, \
341 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
345 .branch_type = branch_composite, \
347 .parent_names = (const char *[]){ pname }, \
350 .muxdiv_offset = mo, \
359 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
360 df, dt, go, gs, gf) \
363 .branch_type = branch_composite, \
365 .parent_names = (const char *[]){ pname }, \
368 .muxdiv_offset = mo, \
378 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
382 .branch_type = branch_composite, \
384 .parent_names = pnames, \
385 .num_parents = ARRAY_SIZE(pnames), \
387 .muxdiv_offset = mo, \
396 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
400 .branch_type = branch_composite, \
402 .parent_names = pnames, \
403 .num_parents = ARRAY_SIZE(pnames), \
405 .muxdiv_offset = mo, \
415 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
416 mw, mf, ds, dw, df, dt) \
419 .branch_type = branch_composite, \
421 .parent_names = pnames, \
422 .num_parents = ARRAY_SIZE(pnames), \
424 .muxdiv_offset = mo, \
435 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
438 .branch_type = branch_fraction_divider, \
440 .parent_names = (const char *[]){ pname }, \
443 .muxdiv_offset = mo, \
452 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
455 .branch_type = branch_fraction_divider, \
457 .parent_names = (const char *[]){ pname }, \
460 .muxdiv_offset = mo, \
470 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
473 .branch_type = branch_fraction_divider, \
475 .parent_names = (const char *[]){ pname }, \
478 .muxdiv_offset = mo, \
486 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
489 .branch_type = branch_mux, \
491 .parent_names = pnames, \
492 .num_parents = ARRAY_SIZE(pnames), \
494 .muxdiv_offset = o, \
501 #define DIV(_id, cname, pname, f, o, s, w, df) \
504 .branch_type = branch_divider, \
506 .parent_names = (const char *[]){ pname }, \
509 .muxdiv_offset = o, \
516 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
519 .branch_type = branch_divider, \
521 .parent_names = (const char *[]){ pname }, \
524 .muxdiv_offset = o, \
531 #define GATE(_id, cname, pname, f, o, b, gf) \
534 .branch_type = branch_gate, \
536 .parent_names = (const char *[]){ pname }, \
544 #define MMC(_id, cname, pname, offset, shift) \
547 .branch_type = branch_mmc, \
549 .parent_names = (const char *[]){ pname }, \
551 .muxdiv_offset = offset, \
552 .div_shift = shift, \
555 #define INVERTER(_id, cname, pname, io, is, if) \
558 .branch_type = branch_inverter, \
560 .parent_names = (const char *[]){ pname }, \
562 .muxdiv_offset = io, \
567 #define FACTOR(_id, cname, pname, f, fm, fd) \
570 .branch_type = branch_factor, \
572 .parent_names = (const char *[]){ pname }, \
579 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
582 .branch_type = branch_factor, \
584 .parent_names = (const char *[]){ pname }, \
594 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
595 void __iomem *base, unsigned long nr_clks);
596 void rockchip_clk_of_add_provider(struct device_node *np,
597 struct rockchip_clk_provider *ctx);
598 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx);
599 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
600 struct clk *clk, unsigned int id);
601 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
602 struct rockchip_clk_branch *list,
603 unsigned int nr_clk);
604 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
605 struct rockchip_pll_clock *pll_list,
606 unsigned int nr_pll, int grf_lock_offset);
607 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
608 unsigned int lookup_id, const char *name,
609 const char *const *parent_names, u8 num_parents,
610 const struct rockchip_cpuclk_reg_data *reg_data,
611 const struct rockchip_cpuclk_rate_table *rates,
613 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
614 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
615 unsigned int reg, void (*cb)(void));
617 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
619 #ifdef CONFIG_RESET_CONTROLLER
620 void rockchip_register_softrst(struct device_node *np,
621 unsigned int num_regs,
622 void __iomem *base, u8 flags);
624 static inline void rockchip_register_softrst(struct device_node *np,
625 unsigned int num_regs,
626 void __iomem *base, u8 flags)