2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #ifndef CLK_ROCKCHIP_CLK_H
27 #define CLK_ROCKCHIP_CLK_H
33 #define HIWORD_UPDATE(val, mask, shift) \
34 ((val) << (shift) | (mask) << ((shift) + 16))
36 /* register positions shared by RK2928, RK3066 and RK3188 */
37 #define RK2928_PLL_CON(x) ((x) * 0x4)
38 #define RK2928_MODE_CON 0x40
39 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
40 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
41 #define RK2928_GLB_SRST_FST 0x100
42 #define RK2928_GLB_SRST_SND 0x104
43 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
44 #define RK2928_MISC_CON 0x134
46 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
47 #define RK3288_MODE_CON 0x50
48 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
49 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
50 #define RK3288_GLB_SRST_FST 0x1b0
51 #define RK3288_GLB_SRST_SND 0x1b4
52 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
53 #define RK3288_MISC_CON 0x1e8
54 #define RK3288_SDMMC_CON0 0x200
55 #define RK3288_SDMMC_CON1 0x204
56 #define RK3288_SDIO0_CON0 0x208
57 #define RK3288_SDIO0_CON1 0x20c
58 #define RK3288_SDIO1_CON0 0x210
59 #define RK3288_SDIO1_CON1 0x214
60 #define RK3288_EMMC_CON0 0x218
61 #define RK3288_EMMC_CON1 0x21c
63 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
64 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
65 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
66 #define RK3368_GLB_SRST_FST 0x280
67 #define RK3368_GLB_SRST_SND 0x284
68 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
69 #define RK3368_MISC_CON 0x380
70 #define RK3368_SDMMC_CON0 0x400
71 #define RK3368_SDMMC_CON1 0x404
72 #define RK3368_SDIO0_CON0 0x408
73 #define RK3368_SDIO0_CON1 0x40c
74 #define RK3368_SDIO1_CON0 0x410
75 #define RK3368_SDIO1_CON1 0x414
76 #define RK3368_EMMC_CON0 0x418
77 #define RK3368_EMMC_CON1 0x41c
79 enum rockchip_pll_type {
85 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
86 _postdiv2, _dsmpd, _frac) \
90 .postdiv1 = _postdiv1, \
92 .postdiv2 = _postdiv2, \
97 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
103 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
106 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
115 struct rockchip_pll_rate_table {
123 unsigned int postdiv1;
125 unsigned int postdiv2;
131 * struct rockchip_pll_clock: information about pll clock
132 * @id: platform specific id of the clock.
133 * @name: name of this pll clock.
134 * @parent_name: name of the parent clock.
135 * @flags: optional flags for basic clock.
136 * @con_offset: offset of the register for configuring the PLL.
137 * @mode_offset: offset of the register for configuring the PLL-mode.
138 * @mode_shift: offset inside the mode-register for the mode of this pll.
139 * @lock_shift: offset inside the lock register for the lock status.
140 * @type: Type of PLL to be registered.
141 * @pll_flags: hardware-specific flags
142 * @rate_table: Table of usable pll rates
145 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
146 * rate_table parameters and ajust them if necessary.
148 struct rockchip_pll_clock {
151 const char *const *parent_names;
158 enum rockchip_pll_type type;
160 struct rockchip_pll_rate_table *rate_table;
163 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
165 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
166 _lshift, _pflags, _rtable) \
171 .parent_names = _pnames, \
172 .num_parents = ARRAY_SIZE(_pnames), \
173 .flags = CLK_GET_RATE_NOCACHE | _flags, \
174 .con_offset = _con, \
175 .mode_offset = _mode, \
176 .mode_shift = _mshift, \
177 .lock_shift = _lshift, \
178 .pll_flags = _pflags, \
179 .rate_table = _rtable, \
182 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
183 const char *name, const char *const *parent_names,
184 u8 num_parents, void __iomem *base, int con_offset,
185 int grf_lock_offset, int lock_shift, int reg_mode,
186 int mode_shift, struct rockchip_pll_rate_table *rate_table,
187 u8 clk_pll_flags, spinlock_t *lock);
189 struct rockchip_cpuclk_clksel {
194 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 2
195 struct rockchip_cpuclk_rate_table {
197 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
201 * struct rockchip_cpuclk_reg_data: describes register offsets and masks of the cpuclock
202 * @core_reg: register offset of the core settings register
203 * @div_core_shift: core divider offset used to divide the pll value
204 * @div_core_mask: core divider mask
205 * @mux_core_shift: offset of the core multiplexer
207 struct rockchip_cpuclk_reg_data {
215 struct clk *rockchip_clk_register_cpuclk(const char *name,
216 const char *const *parent_names, u8 num_parents,
217 const struct rockchip_cpuclk_reg_data *reg_data,
218 const struct rockchip_cpuclk_rate_table *rates,
219 int nrates, void __iomem *reg_base, spinlock_t *lock);
221 struct clk *rockchip_clk_register_mmc(const char *name,
222 const char *const *parent_names, u8 num_parents,
223 void __iomem *reg, int shift);
225 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
227 struct clk *rockchip_clk_register_inverter(const char *name,
228 const char *const *parent_names, u8 num_parents,
229 void __iomem *reg, int shift, int flags,
232 #define PNAME(x) static const char *const x[] __initconst
234 enum rockchip_clk_branch_type {
238 branch_fraction_divider,
244 struct rockchip_clk_branch {
246 enum rockchip_clk_branch_type branch_type;
248 const char *const *parent_names;
258 struct clk_div_table *div_table;
264 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
268 .branch_type = branch_composite, \
270 .parent_names = pnames, \
271 .num_parents = ARRAY_SIZE(pnames), \
273 .muxdiv_offset = mo, \
285 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
289 .branch_type = branch_composite, \
291 .parent_names = (const char *[]){ pname }, \
294 .muxdiv_offset = mo, \
303 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
304 df, dt, go, gs, gf) \
307 .branch_type = branch_composite, \
309 .parent_names = (const char *[]){ pname }, \
312 .muxdiv_offset = mo, \
322 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
326 .branch_type = branch_composite, \
328 .parent_names = pnames, \
329 .num_parents = ARRAY_SIZE(pnames), \
331 .muxdiv_offset = mo, \
340 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
344 .branch_type = branch_composite, \
346 .parent_names = pnames, \
347 .num_parents = ARRAY_SIZE(pnames), \
349 .muxdiv_offset = mo, \
359 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
360 mw, mf, ds, dw, df, dt) \
363 .branch_type = branch_composite, \
365 .parent_names = pnames, \
366 .num_parents = ARRAY_SIZE(pnames), \
368 .muxdiv_offset = mo, \
379 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
382 .branch_type = branch_fraction_divider, \
384 .parent_names = (const char *[]){ pname }, \
387 .muxdiv_offset = mo, \
396 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
399 .branch_type = branch_mux, \
401 .parent_names = pnames, \
402 .num_parents = ARRAY_SIZE(pnames), \
404 .muxdiv_offset = o, \
411 #define DIV(_id, cname, pname, f, o, s, w, df) \
414 .branch_type = branch_divider, \
416 .parent_names = (const char *[]){ pname }, \
419 .muxdiv_offset = o, \
426 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
429 .branch_type = branch_divider, \
431 .parent_names = (const char *[]){ pname }, \
434 .muxdiv_offset = o, \
441 #define GATE(_id, cname, pname, f, o, b, gf) \
444 .branch_type = branch_gate, \
446 .parent_names = (const char *[]){ pname }, \
454 #define MMC(_id, cname, pname, offset, shift) \
457 .branch_type = branch_mmc, \
459 .parent_names = (const char *[]){ pname }, \
461 .muxdiv_offset = offset, \
462 .div_shift = shift, \
465 #define INVERTER(_id, cname, pname, io, is, if) \
468 .branch_type = branch_inverter, \
470 .parent_names = (const char *[]){ pname }, \
472 .muxdiv_offset = io, \
477 void rockchip_clk_init(struct device_node *np, void __iomem *base,
478 unsigned long nr_clks);
479 struct regmap *rockchip_clk_get_grf(void);
480 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
481 void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
482 unsigned int nr_clk);
483 void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
484 unsigned int nr_pll, int grf_lock_offset);
485 void rockchip_clk_register_armclk(unsigned int lookup_id, const char *name,
486 const char *const *parent_names, u8 num_parents,
487 const struct rockchip_cpuclk_reg_data *reg_data,
488 const struct rockchip_cpuclk_rate_table *rates,
490 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
491 void rockchip_register_restart_notifier(unsigned int reg);
493 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
495 #ifdef CONFIG_RESET_CONTROLLER
496 void rockchip_register_softrst(struct device_node *np,
497 unsigned int num_regs,
498 void __iomem *base, u8 flags);
500 static inline void rockchip_register_softrst(struct device_node *np,
501 unsigned int num_regs,
502 void __iomem *base, u8 flags)