2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/slab.h>
27 #include <linux/clk.h>
28 #include <linux/clk-provider.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
31 #include <linux/reboot.h>
35 * Register a clock branch.
36 * Most clock branches have a form like
42 * sometimes without one of those components.
44 static struct clk *rockchip_clk_register_branch(const char *name,
45 const char *const *parent_names, u8 num_parents, void __iomem *base,
46 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
47 u8 div_shift, u8 div_width, u8 div_flags,
48 struct clk_div_table *div_table, int gate_offset,
49 u8 gate_shift, u8 gate_flags, unsigned long flags,
53 struct clk_mux *mux = NULL;
54 struct clk_gate *gate = NULL;
55 struct clk_divider *div = NULL;
56 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
59 if (num_parents > 1) {
60 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
62 return ERR_PTR(-ENOMEM);
64 mux->reg = base + muxdiv_offset;
65 mux->shift = mux_shift;
66 mux->mask = BIT(mux_width) - 1;
67 mux->flags = mux_flags;
69 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
73 if (gate_offset >= 0) {
74 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
78 gate->flags = gate_flags;
79 gate->reg = base + gate_offset;
80 gate->bit_idx = gate_shift;
82 gate_ops = &clk_gate_ops;
86 div = kzalloc(sizeof(*div), GFP_KERNEL);
90 div->flags = div_flags;
91 div->reg = base + muxdiv_offset;
92 div->shift = div_shift;
93 div->width = div_width;
95 div->table = div_table;
96 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
101 clk = clk_register_composite(NULL, name, parent_names, num_parents,
102 mux ? &mux->hw : NULL, mux_ops,
103 div ? &div->hw : NULL, div_ops,
104 gate ? &gate->hw : NULL, gate_ops,
112 return ERR_PTR(-ENOMEM);
115 struct rockchip_clk_frac {
116 struct notifier_block clk_nb;
117 struct clk_fractional_divider div;
118 struct clk_gate gate;
121 const struct clk_ops *mux_ops;
124 bool rate_change_remuxed;
128 #define to_rockchip_clk_frac_nb(nb) \
129 container_of(nb, struct rockchip_clk_frac, clk_nb)
131 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
132 unsigned long event, void *data)
134 struct clk_notifier_data *ndata = data;
135 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
136 struct clk_mux *frac_mux = &frac->mux;
139 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
140 __func__, event, ndata->old_rate, ndata->new_rate);
141 if (event == PRE_RATE_CHANGE) {
142 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
143 if (frac->rate_change_idx != frac->mux_frac_idx) {
144 frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
145 frac->rate_change_remuxed = 1;
147 } else if (event == POST_RATE_CHANGE) {
149 * The POST_RATE_CHANGE notifier runs directly after the
150 * divider clock is set in clk_change_rate, so we'll have
151 * remuxed back to the original parent before clk_change_rate
152 * reaches the mux itself.
154 if (frac->rate_change_remuxed) {
155 frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
156 frac->rate_change_remuxed = 0;
160 return notifier_from_errno(ret);
163 static struct clk *rockchip_clk_register_frac_branch(
164 struct rockchip_clk_provider *ctx, const char *name,
165 const char *const *parent_names, u8 num_parents,
166 void __iomem *base, int muxdiv_offset, u8 div_flags,
167 int gate_offset, u8 gate_shift, u8 gate_flags,
168 unsigned long flags, struct rockchip_clk_branch *child,
171 struct rockchip_clk_frac *frac;
173 struct clk_gate *gate = NULL;
174 struct clk_fractional_divider *div = NULL;
175 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
177 if (muxdiv_offset < 0)
178 return ERR_PTR(-EINVAL);
180 if (child && child->branch_type != branch_mux) {
181 pr_err("%s: fractional child clock for %s can only be a mux\n",
183 return ERR_PTR(-EINVAL);
186 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
188 return ERR_PTR(-ENOMEM);
190 if (gate_offset >= 0) {
192 gate->flags = gate_flags;
193 gate->reg = base + gate_offset;
194 gate->bit_idx = gate_shift;
196 gate_ops = &clk_gate_ops;
200 div->flags = div_flags;
201 div->reg = base + muxdiv_offset;
204 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
207 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
209 div_ops = &clk_fractional_divider_ops;
211 clk = clk_register_composite(NULL, name, parent_names, num_parents,
214 gate ? &gate->hw : NULL, gate_ops,
215 flags | CLK_SET_RATE_UNGATE);
222 struct clk_mux *frac_mux = &frac->mux;
223 struct clk_init_data init;
227 frac->mux_frac_idx = -1;
228 for (i = 0; i < child->num_parents; i++) {
229 if (!strcmp(name, child->parent_names[i])) {
230 pr_debug("%s: found fractional parent in mux at pos %d\n",
232 frac->mux_frac_idx = i;
237 frac->mux_ops = &clk_mux_ops;
238 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
240 frac_mux->reg = base + child->muxdiv_offset;
241 frac_mux->shift = child->mux_shift;
242 frac_mux->mask = BIT(child->mux_width) - 1;
243 frac_mux->flags = child->mux_flags;
244 frac_mux->lock = lock;
245 frac_mux->hw.init = &init;
247 init.name = child->name;
248 init.flags = child->flags | CLK_SET_RATE_PARENT;
249 init.ops = frac->mux_ops;
250 init.parent_names = child->parent_names;
251 init.num_parents = child->num_parents;
253 mux_clk = clk_register(NULL, &frac_mux->hw);
257 rockchip_clk_add_lookup(ctx, mux_clk, child->id);
259 /* notifier on the fraction divider to catch rate changes */
260 if (frac->mux_frac_idx >= 0) {
261 ret = clk_notifier_register(clk, &frac->clk_nb);
263 pr_err("%s: failed to register clock notifier for %s\n",
266 pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
267 __func__, name, child->name);
274 static struct clk *rockchip_clk_register_factor_branch(const char *name,
275 const char *const *parent_names, u8 num_parents,
276 void __iomem *base, unsigned int mult, unsigned int div,
277 int gate_offset, u8 gate_shift, u8 gate_flags,
278 unsigned long flags, spinlock_t *lock)
281 struct clk_gate *gate = NULL;
282 struct clk_fixed_factor *fix = NULL;
284 /* without gate, register a simple factor clock */
285 if (gate_offset == 0) {
286 return clk_register_fixed_factor(NULL, name,
287 parent_names[0], flags, mult,
291 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
293 return ERR_PTR(-ENOMEM);
295 gate->flags = gate_flags;
296 gate->reg = base + gate_offset;
297 gate->bit_idx = gate_shift;
300 fix = kzalloc(sizeof(*fix), GFP_KERNEL);
303 return ERR_PTR(-ENOMEM);
309 clk = clk_register_composite(NULL, name, parent_names, num_parents,
311 &fix->hw, &clk_fixed_factor_ops,
312 &gate->hw, &clk_gate_ops, flags);
321 struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
322 void __iomem *base, unsigned long nr_clks)
324 struct rockchip_clk_provider *ctx;
325 struct clk **clk_table;
328 ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
330 pr_err("%s: Could not allocate clock provider context\n",
332 return ERR_PTR(-ENOMEM);
335 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
337 pr_err("%s: Could not allocate clock lookup table\n",
342 for (i = 0; i < nr_clks; ++i)
343 clk_table[i] = ERR_PTR(-ENOENT);
345 ctx->reg_base = base;
346 ctx->clk_data.clks = clk_table;
347 ctx->clk_data.clk_num = nr_clks;
349 ctx->grf = ERR_PTR(-EPROBE_DEFER);
350 spin_lock_init(&ctx->lock);
356 return ERR_PTR(-ENOMEM);
359 void __init rockchip_clk_of_add_provider(struct device_node *np,
360 struct rockchip_clk_provider *ctx)
362 if (of_clk_add_provider(np, of_clk_src_onecell_get,
364 pr_err("%s: could not register clk provider\n", __func__);
367 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx)
369 if (IS_ERR(ctx->grf))
370 ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf");
374 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
375 struct clk *clk, unsigned int id)
377 if (ctx->clk_data.clks && id)
378 ctx->clk_data.clks[id] = clk;
381 void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
382 struct rockchip_pll_clock *list,
383 unsigned int nr_pll, int grf_lock_offset)
388 for (idx = 0; idx < nr_pll; idx++, list++) {
389 clk = rockchip_clk_register_pll(ctx, list->type, list->name,
390 list->parent_names, list->num_parents,
391 list->con_offset, grf_lock_offset,
392 list->lock_shift, list->mode_offset,
393 list->mode_shift, list->rate_table,
394 list->flags, list->pll_flags);
396 pr_err("%s: failed to register clock %s\n", __func__,
401 rockchip_clk_add_lookup(ctx, clk, list->id);
405 void __init rockchip_clk_register_branches(
406 struct rockchip_clk_provider *ctx,
407 struct rockchip_clk_branch *list,
410 struct clk *clk = NULL;
414 for (idx = 0; idx < nr_clk; idx++, list++) {
417 /* catch simple muxes */
418 switch (list->branch_type) {
420 clk = clk_register_mux(NULL, list->name,
421 list->parent_names, list->num_parents,
422 flags, ctx->reg_base + list->muxdiv_offset,
423 list->mux_shift, list->mux_width,
424 list->mux_flags, &ctx->lock);
428 clk = clk_register_divider_table(NULL,
429 list->name, list->parent_names[0],
430 flags, ctx->reg_base + list->muxdiv_offset,
431 list->div_shift, list->div_width,
432 list->div_flags, list->div_table,
435 clk = clk_register_divider(NULL, list->name,
436 list->parent_names[0], flags,
437 ctx->reg_base + list->muxdiv_offset,
438 list->div_shift, list->div_width,
439 list->div_flags, &ctx->lock);
441 case branch_fraction_divider:
442 clk = rockchip_clk_register_frac_branch(ctx, list->name,
443 list->parent_names, list->num_parents,
444 ctx->reg_base, list->muxdiv_offset, list->div_flags,
445 list->gate_offset, list->gate_shift,
446 list->gate_flags, flags, list->child,
450 flags |= CLK_SET_RATE_PARENT;
452 clk = clk_register_gate(NULL, list->name,
453 list->parent_names[0], flags,
454 ctx->reg_base + list->gate_offset,
455 list->gate_shift, list->gate_flags, &ctx->lock);
457 case branch_composite:
458 clk = rockchip_clk_register_branch(list->name,
459 list->parent_names, list->num_parents,
460 ctx->reg_base, list->muxdiv_offset, list->mux_shift,
461 list->mux_width, list->mux_flags,
462 list->div_shift, list->div_width,
463 list->div_flags, list->div_table,
464 list->gate_offset, list->gate_shift,
465 list->gate_flags, flags, &ctx->lock);
468 clk = rockchip_clk_register_mmc(
470 list->parent_names, list->num_parents,
471 ctx->reg_base + list->muxdiv_offset,
475 case branch_inverter:
476 clk = rockchip_clk_register_inverter(
477 list->name, list->parent_names,
479 ctx->reg_base + list->muxdiv_offset,
480 list->div_shift, list->div_flags, &ctx->lock);
483 clk = rockchip_clk_register_factor_branch(
484 list->name, list->parent_names,
485 list->num_parents, ctx->reg_base,
486 list->div_shift, list->div_width,
487 list->gate_offset, list->gate_shift,
488 list->gate_flags, flags, &ctx->lock);
491 clk = rockchip_clk_register_ddrclk(
492 list->name, list->flags,
493 list->parent_names, list->num_parents,
494 list->muxdiv_offset, list->mux_shift,
495 list->mux_width, list->div_shift,
496 list->div_width, list->div_flags,
497 ctx->reg_base, &ctx->lock);
501 /* none of the cases above matched */
503 pr_err("%s: unknown clock type %d\n",
504 __func__, list->branch_type);
509 pr_err("%s: failed to register clock %s: %ld\n",
510 __func__, list->name, PTR_ERR(clk));
514 rockchip_clk_add_lookup(ctx, clk, list->id);
518 void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
519 unsigned int lookup_id,
520 const char *name, const char *const *parent_names,
522 const struct rockchip_cpuclk_reg_data *reg_data,
523 const struct rockchip_cpuclk_rate_table *rates,
528 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
529 reg_data, rates, nrates, ctx->reg_base,
532 pr_err("%s: failed to register clock %s: %ld\n",
533 __func__, name, PTR_ERR(clk));
537 rockchip_clk_add_lookup(ctx, clk, lookup_id);
540 void __init rockchip_clk_protect_critical(const char *const clocks[],
545 /* Protect the clocks that needs to stay on */
546 for (i = 0; i < nclocks; i++) {
547 struct clk *clk = __clk_lookup(clocks[i]);
550 clk_prepare_enable(clk);
554 static void __iomem *rst_base;
555 static unsigned int reg_restart;
556 static void (*cb_restart)(void);
557 static int rockchip_restart_notify(struct notifier_block *this,
558 unsigned long mode, void *cmd)
563 writel(0xfdb9, rst_base + reg_restart);
567 static struct notifier_block rockchip_restart_handler = {
568 .notifier_call = rockchip_restart_notify,
572 void __init rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
573 unsigned int reg, void (*cb)(void))
577 rst_base = ctx->reg_base;
580 ret = register_restart_handler(&rockchip_restart_handler);
582 pr_err("%s: cannot register restart handler, %d\n",