drivers/clk/rockchip/clk.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * based on
   6  *
   7  * samsung/clk.c
   8  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   9  * Copyright (c) 2013 Linaro Ltd.
  10  * Author: Thomas Abraham <thomas.ab@samsung.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/regmap.h>
  28 #include "clk.h"
  29
  30 /**
  31  * Register a clock branch.
  32  * Most clock branches have a form like
  33  *
  34  * src1 --|--\
  35  *        |M |--[GATE]-[DIV]-
  36  * src2 --|--/
  37  *
  38  * sometimes without one of those components.
  39  */
  40 static struct clk *rockchip_clk_register_branch(const char *name,
  41                 const char **parent_names, u8 num_parents, void __iomem *base,
  42                 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
  43                 u8 div_shift, u8 div_width, u8 div_flags,
  44                 struct clk_div_table *div_table, int gate_offset,
  45                 u8 gate_shift, u8 gate_flags, unsigned long flags,
  46                 spinlock_t *lock)
  47 {
  48         struct clk *clk;
  49         struct clk_mux *mux = NULL;
  50         struct clk_gate *gate = NULL;
  51         struct clk_divider *div = NULL;
  52         const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
  53                              *gate_ops = NULL;
  54
  55         if (num_parents > 1) {
  56                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  57                 if (!mux)
  58                         return ERR_PTR(-ENOMEM);
  59
  60                 mux->reg = base + muxdiv_offset;
  61                 mux->shift = mux_shift;
  62                 mux->mask = BIT(mux_width) - 1;
  63                 mux->flags = mux_flags;
  64                 mux->lock = lock;
  65                 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
  66                                                         : &clk_mux_ops;
  67         }
  68
  69         if (gate_offset >= 0) {
  70                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  71                 if (!gate)
  72                         return ERR_PTR(-ENOMEM);
  73
  74                 gate->flags = gate_flags;
  75                 gate->reg = base + gate_offset;
  76                 gate->bit_idx = gate_shift;
  77                 gate->lock = lock;
  78                 gate_ops = &clk_gate_ops;
  79         }
  80
  81         if (div_width > 0) {
  82                 div = kzalloc(sizeof(*div), GFP_KERNEL);
  83                 if (!div)
  84                         return ERR_PTR(-ENOMEM);
  85
  86                 div->flags = div_flags;
  87                 div->reg = base + muxdiv_offset;
  88                 div->shift = div_shift;
  89                 div->width = div_width;
  90                 div->lock = lock;
  91                 div->table = div_table;
  92                 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
  93                                                 ? &clk_divider_ro_ops
  94                                                 : &clk_divider_ops;
  95         }
  96
  97         clk = clk_register_composite(NULL, name, parent_names, num_parents,
  98                                      mux ? &mux->hw : NULL, mux_ops,
  99                                      div ? &div->hw : NULL, div_ops,
 100                                      gate ? &gate->hw : NULL, gate_ops,
 101                                      flags);
 102
 103         return clk;
 104 }
 105
 106 static struct clk *rockchip_clk_register_frac_branch(const char *name,
 107                 const char **parent_names, u8 num_parents, void __iomem *base,
 108                 int muxdiv_offset, u8 div_flags,
 109                 int gate_offset, u8 gate_shift, u8 gate_flags,
 110                 unsigned long flags, spinlock_t *lock)
 111 {
 112         struct clk *clk;
 113         struct clk_gate *gate = NULL;
 114         struct clk_fractional_divider *div = NULL;
 115         const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
 116
 117         if (gate_offset >= 0) {
 118                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 119                 if (!gate)
 120                         return ERR_PTR(-ENOMEM);
 121
 122                 gate->flags = gate_flags;
 123                 gate->reg = base + gate_offset;
 124                 gate->bit_idx = gate_shift;
 125                 gate->lock = lock;
 126                 gate_ops = &clk_gate_ops;
 127         }
 128
 129         if (muxdiv_offset < 0)
 130                 return ERR_PTR(-EINVAL);
 131
 132         div = kzalloc(sizeof(*div), GFP_KERNEL);
 133         if (!div)
 134                 return ERR_PTR(-ENOMEM);
 135
 136         div->flags = div_flags;
 137         div->reg = base + muxdiv_offset;
 138         div->mshift = 16;
 139         div->mmask = 0xffff0000;
 140         div->nshift = 0;
 141         div->nmask = 0xffff;
 142         div->lock = lock;
 143         div_ops = &clk_fractional_divider_ops;
 144
 145         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 146                                      NULL, NULL,
 147                                      &div->hw, div_ops,
 148                                      gate ? &gate->hw : NULL, gate_ops,
 149                                      flags);
 150
 151         return clk;
 152 }
 153
 154 static DEFINE_SPINLOCK(clk_lock);
 155 static struct clk **clk_table;
 156 static void __iomem *reg_base;
 157 static struct clk_onecell_data clk_data;
 158 static struct device_node *cru_node;
 159 static struct regmap *grf;
 160
 161 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
 162                               unsigned long nr_clks)
 163 {
 164         reg_base = base;
 165         cru_node = np;
 166         grf = ERR_PTR(-EPROBE_DEFER);
 167
 168         clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
 169         if (!clk_table)
 170                 pr_err("%s: could not allocate clock lookup table\n", __func__);
 171
 172         clk_data.clks = clk_table;
 173         clk_data.clk_num = nr_clks;
 174         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 175 }
 176
 177 struct regmap *rockchip_clk_get_grf(void)
 178 {
 179         if (IS_ERR(grf))
 180                 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
 181         return grf;
 182 }
 183
 184 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
 185 {
 186         if (clk_table && id)
 187                 clk_table[id] = clk;
 188 }
 189
 190 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
 191                                 unsigned int nr_pll, int grf_lock_offset)
 192 {
 193         struct clk *clk;
 194         int idx;
 195
 196         for (idx = 0; idx < nr_pll; idx++, list++) {
 197                 clk = rockchip_clk_register_pll(list->type, list->name,
 198                                 list->parent_names, list->num_parents,
 199                                 reg_base, list->con_offset, grf_lock_offset,
 200                                 list->lock_shift, list->mode_offset,
 201                                 list->mode_shift, list->rate_table, &clk_lock);
 202                 if (IS_ERR(clk)) {
 203                         pr_err("%s: failed to register clock %s\n", __func__,
 204                                 list->name);
 205                         continue;
 206                 }
 207
 208                 rockchip_clk_add_lookup(clk, list->id);
 209         }
 210 }
 211
 212 void __init rockchip_clk_register_branches(
 213                                       struct rockchip_clk_branch *list,
 214                                       unsigned int nr_clk)
 215 {
 216         struct clk *clk = NULL;
 217         unsigned int idx;
 218         unsigned long flags;
 219
 220         for (idx = 0; idx < nr_clk; idx++, list++) {
 221                 flags = list->flags;
 222
 223                 /* catch simple muxes */
 224                 switch (list->branch_type) {
 225                 case branch_mux:
 226                         clk = clk_register_mux(NULL, list->name,
 227                                 list->parent_names, list->num_parents,
 228                                 flags, reg_base + list->muxdiv_offset,
 229                                 list->mux_shift, list->mux_width,
 230                                 list->mux_flags, &clk_lock);
 231                         break;
 232                 case branch_divider:
 233                         if (list->div_table)
 234                                 clk = clk_register_divider_table(NULL,
 235                                         list->name, list->parent_names[0],
 236                                         flags, reg_base + list->muxdiv_offset,
 237                                         list->div_shift, list->div_width,
 238                                         list->div_flags, list->div_table,
 239                                         &clk_lock);
 240                         else
 241                                 clk = clk_register_divider(NULL, list->name,
 242                                         list->parent_names[0], flags,
 243                                         reg_base + list->muxdiv_offset,
 244                                         list->div_shift, list->div_width,
 245                                         list->div_flags, &clk_lock);
 246                         break;
 247                 case branch_fraction_divider:
 248                         /* keep all gates untouched for now */
 249                         flags |= CLK_IGNORE_UNUSED;
 250
 251                         clk = rockchip_clk_register_frac_branch(list->name,
 252                                 list->parent_names, list->num_parents,
 253                                 reg_base, list->muxdiv_offset, list->div_flags,
 254                                 list->gate_offset, list->gate_shift,
 255                                 list->gate_flags, flags, &clk_lock);
 256                         break;
 257                 case branch_gate:
 258                         flags |= CLK_SET_RATE_PARENT;
 259
 260                         /* keep all gates untouched for now */
 261                         flags |= CLK_IGNORE_UNUSED;
 262
 263                         clk = clk_register_gate(NULL, list->name,
 264                                 list->parent_names[0], flags,
 265                                 reg_base + list->gate_offset,
 266                                 list->gate_shift, list->gate_flags, &clk_lock);
 267                         break;
 268                 case branch_composite:
 269                         /* keep all gates untouched for now */
 270                         flags |= CLK_IGNORE_UNUSED;
 271
 272                         clk = rockchip_clk_register_branch(list->name,
 273                                 list->parent_names, list->num_parents,
 274                                 reg_base, list->muxdiv_offset, list->mux_shift,
 275                                 list->mux_width, list->mux_flags,
 276                                 list->div_shift, list->div_width,
 277                                 list->div_flags, list->div_table,
 278                                 list->gate_offset, list->gate_shift,
 279                                 list->gate_flags, flags, &clk_lock);
 280                         break;
 281                 }
 282
 283                 /* none of the cases above matched */
 284                 if (!clk) {
 285                         pr_err("%s: unknown clock type %d\n",
 286                                __func__, list->branch_type);
 287                         continue;
 288                 }
 289
 290                 if (IS_ERR(clk)) {
 291                         pr_err("%s: failed to register clock %s: %ld\n",
 292                                __func__, list->name, PTR_ERR(clk));
 293                         continue;
 294                 }
 295
 296                 rockchip_clk_add_lookup(clk, list->id);
 297         }
 298 }
 299
 300 void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks)
 301 {
 302         int i;
 303
 304         /* Protect the clocks that needs to stay on */
 305         for (i = 0; i < nclocks; i++) {
 306                 struct clk *clk = __clk_lookup(clocks[i]);
 307
 308                 if (clk)
 309                         clk_prepare_enable(clk);
 310         }
 311 }