2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
6 * Author: Xing Zheng <zhengxing@rock-chips.com>
11 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
12 * Copyright (c) 2013 Linaro Ltd.
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/slab.h>
27 #include <linux/clk.h>
28 #include <linux/clk-provider.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
31 #include <linux/reboot.h>
35 * Register a clock branch.
36 * Most clock branches have a form like
42 * sometimes without one of those components.
44 static struct clk *rockchip_clk_register_branch(const char *name,
45 const char *const *parent_names, u8 num_parents, void __iomem *base,
46 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
47 u8 div_shift, u8 div_width, u8 div_flags,
48 struct clk_div_table *div_table, int gate_offset,
49 u8 gate_shift, u8 gate_flags, unsigned long flags,
53 struct clk_mux *mux = NULL;
54 struct clk_gate *gate = NULL;
55 struct clk_divider *div = NULL;
56 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
59 if (num_parents > 1) {
60 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
62 return ERR_PTR(-ENOMEM);
64 mux->reg = base + muxdiv_offset;
65 mux->shift = mux_shift;
66 mux->mask = BIT(mux_width) - 1;
67 mux->flags = mux_flags;
69 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
73 if (gate_offset >= 0) {
74 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
76 return ERR_PTR(-ENOMEM);
78 gate->flags = gate_flags;
79 gate->reg = base + gate_offset;
80 gate->bit_idx = gate_shift;
82 gate_ops = &clk_gate_ops;
86 div = kzalloc(sizeof(*div), GFP_KERNEL);
88 return ERR_PTR(-ENOMEM);
90 div->flags = div_flags;
91 div->reg = base + muxdiv_offset;
92 div->shift = div_shift;
93 div->width = div_width;
95 div->table = div_table;
96 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
101 clk = clk_register_composite(NULL, name, parent_names, num_parents,
102 mux ? &mux->hw : NULL, mux_ops,
103 div ? &div->hw : NULL, div_ops,
104 gate ? &gate->hw : NULL, gate_ops,
110 struct rockchip_clk_frac {
111 struct notifier_block clk_nb;
112 struct clk_fractional_divider div;
113 struct clk_gate gate;
116 const struct clk_ops *mux_ops;
119 bool rate_change_remuxed;
123 #define to_rockchip_clk_frac_nb(nb) \
124 container_of(nb, struct rockchip_clk_frac, clk_nb)
126 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
127 unsigned long event, void *data)
129 struct clk_notifier_data *ndata = data;
130 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
131 struct clk_mux *frac_mux = &frac->mux;
134 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
135 __func__, event, ndata->old_rate, ndata->new_rate);
136 if (event == PRE_RATE_CHANGE) {
137 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
138 if (frac->rate_change_idx != frac->mux_frac_idx) {
139 frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
140 frac->rate_change_remuxed = 1;
142 } else if (event == POST_RATE_CHANGE) {
144 * The POST_RATE_CHANGE notifier runs directly after the
145 * divider clock is set in clk_change_rate, so we'll have
146 * remuxed back to the original parent before clk_change_rate
147 * reaches the mux itself.
149 if (frac->rate_change_remuxed) {
150 frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
151 frac->rate_change_remuxed = 0;
155 return notifier_from_errno(ret);
158 static struct clk *rockchip_clk_register_frac_branch(
159 struct rockchip_clk_provider *ctx, const char *name,
160 const char *const *parent_names, u8 num_parents,
161 void __iomem *base, int muxdiv_offset, u8 div_flags,
162 int gate_offset, u8 gate_shift, u8 gate_flags,
163 unsigned long flags, struct rockchip_clk_branch *child,
166 struct rockchip_clk_frac *frac;
168 struct clk_gate *gate = NULL;
169 struct clk_fractional_divider *div = NULL;
170 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
172 if (muxdiv_offset < 0)
173 return ERR_PTR(-EINVAL);
175 if (child && child->branch_type != branch_mux) {
176 pr_err("%s: fractional child clock for %s can only be a mux\n",
178 return ERR_PTR(-EINVAL);
181 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
183 return ERR_PTR(-ENOMEM);
185 if (gate_offset >= 0) {
187 gate->flags = gate_flags;
188 gate->reg = base + gate_offset;
189 gate->bit_idx = gate_shift;
191 gate_ops = &clk_gate_ops;
195 div->flags = div_flags;
196 div->reg = base + muxdiv_offset;
199 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
202 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
204 div_ops = &clk_fractional_divider_ops;
206 clk = clk_register_composite(NULL, name, parent_names, num_parents,
209 gate ? &gate->hw : NULL, gate_ops,
210 flags | CLK_SET_RATE_UNGATE);
217 struct clk_mux *frac_mux = &frac->mux;
218 struct clk_init_data init;
222 frac->mux_frac_idx = -1;
223 for (i = 0; i < child->num_parents; i++) {
224 if (!strcmp(name, child->parent_names[i])) {
225 pr_debug("%s: found fractional parent in mux at pos %d\n",
227 frac->mux_frac_idx = i;
232 frac->mux_ops = &clk_mux_ops;
233 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
235 frac_mux->reg = base + child->muxdiv_offset;
236 frac_mux->shift = child->mux_shift;
237 frac_mux->mask = BIT(child->mux_width) - 1;
238 frac_mux->flags = child->mux_flags;
239 frac_mux->lock = lock;
240 frac_mux->hw.init = &init;
242 init.name = child->name;
243 init.flags = child->flags | CLK_SET_RATE_PARENT;
244 init.ops = frac->mux_ops;
245 init.parent_names = child->parent_names;
246 init.num_parents = child->num_parents;
248 mux_clk = clk_register(NULL, &frac_mux->hw);
252 rockchip_clk_add_lookup(ctx, mux_clk, child->id);
254 /* notifier on the fraction divider to catch rate changes */
255 if (frac->mux_frac_idx >= 0) {
256 ret = clk_notifier_register(clk, &frac->clk_nb);
258 pr_err("%s: failed to register clock notifier for %s\n",
261 pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
262 __func__, name, child->name);
269 static struct clk *rockchip_clk_register_factor_branch(const char *name,
270 const char *const *parent_names, u8 num_parents,
271 void __iomem *base, unsigned int mult, unsigned int div,
272 int gate_offset, u8 gate_shift, u8 gate_flags,
273 unsigned long flags, spinlock_t *lock)
276 struct clk_gate *gate = NULL;
277 struct clk_fixed_factor *fix = NULL;
279 /* without gate, register a simple factor clock */
280 if (gate_offset == 0) {
281 return clk_register_fixed_factor(NULL, name,
282 parent_names[0], flags, mult,
286 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
288 return ERR_PTR(-ENOMEM);
290 gate->flags = gate_flags;
291 gate->reg = base + gate_offset;
292 gate->bit_idx = gate_shift;
295 fix = kzalloc(sizeof(*fix), GFP_KERNEL);
298 return ERR_PTR(-ENOMEM);
304 clk = clk_register_composite(NULL, name, parent_names, num_parents,
306 &fix->hw, &clk_fixed_factor_ops,
307 &gate->hw, &clk_gate_ops, flags);
316 struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
317 void __iomem *base, unsigned long nr_clks)
319 struct rockchip_clk_provider *ctx;
320 struct clk **clk_table;
323 ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
325 pr_err("%s: Could not allocate clock provider context\n",
327 return ERR_PTR(-ENOMEM);
330 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
332 pr_err("%s: Could not allocate clock lookup table\n",
337 for (i = 0; i < nr_clks; ++i)
338 clk_table[i] = ERR_PTR(-ENOENT);
340 ctx->reg_base = base;
341 ctx->clk_data.clks = clk_table;
342 ctx->clk_data.clk_num = nr_clks;
344 ctx->grf = ERR_PTR(-EPROBE_DEFER);
345 spin_lock_init(&ctx->lock);
351 return ERR_PTR(-ENOMEM);
354 void __init rockchip_clk_of_add_provider(struct device_node *np,
355 struct rockchip_clk_provider *ctx)
357 if (of_clk_add_provider(np, of_clk_src_onecell_get,
359 pr_err("%s: could not register clk provider\n", __func__);
362 struct regmap *rockchip_clk_get_grf(struct rockchip_clk_provider *ctx)
364 if (IS_ERR(ctx->grf))
365 ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node, "rockchip,grf");
369 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
370 struct clk *clk, unsigned int id)
372 if (ctx->clk_data.clks && id)
373 ctx->clk_data.clks[id] = clk;
376 void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
377 struct rockchip_pll_clock *list,
378 unsigned int nr_pll, int grf_lock_offset)
383 for (idx = 0; idx < nr_pll; idx++, list++) {
384 clk = rockchip_clk_register_pll(ctx, list->type, list->name,
385 list->parent_names, list->num_parents,
386 list->con_offset, grf_lock_offset,
387 list->lock_shift, list->mode_offset,
388 list->mode_shift, list->rate_table,
391 pr_err("%s: failed to register clock %s\n", __func__,
396 rockchip_clk_add_lookup(ctx, clk, list->id);
400 void __init rockchip_clk_register_branches(
401 struct rockchip_clk_provider *ctx,
402 struct rockchip_clk_branch *list,
405 struct clk *clk = NULL;
409 for (idx = 0; idx < nr_clk; idx++, list++) {
412 /* catch simple muxes */
413 switch (list->branch_type) {
415 clk = clk_register_mux(NULL, list->name,
416 list->parent_names, list->num_parents,
417 flags, ctx->reg_base + list->muxdiv_offset,
418 list->mux_shift, list->mux_width,
419 list->mux_flags, &ctx->lock);
423 clk = clk_register_divider_table(NULL,
424 list->name, list->parent_names[0],
425 flags, ctx->reg_base + list->muxdiv_offset,
426 list->div_shift, list->div_width,
427 list->div_flags, list->div_table,
430 clk = clk_register_divider(NULL, list->name,
431 list->parent_names[0], flags,
432 ctx->reg_base + list->muxdiv_offset,
433 list->div_shift, list->div_width,
434 list->div_flags, &ctx->lock);
436 case branch_fraction_divider:
437 clk = rockchip_clk_register_frac_branch(ctx, list->name,
438 list->parent_names, list->num_parents,
439 ctx->reg_base, list->muxdiv_offset, list->div_flags,
440 list->gate_offset, list->gate_shift,
441 list->gate_flags, flags, list->child,
445 flags |= CLK_SET_RATE_PARENT;
447 clk = clk_register_gate(NULL, list->name,
448 list->parent_names[0], flags,
449 ctx->reg_base + list->gate_offset,
450 list->gate_shift, list->gate_flags, &ctx->lock);
452 case branch_composite:
453 clk = rockchip_clk_register_branch(list->name,
454 list->parent_names, list->num_parents,
455 ctx->reg_base, list->muxdiv_offset, list->mux_shift,
456 list->mux_width, list->mux_flags,
457 list->div_shift, list->div_width,
458 list->div_flags, list->div_table,
459 list->gate_offset, list->gate_shift,
460 list->gate_flags, flags, &ctx->lock);
463 clk = rockchip_clk_register_mmc(
465 list->parent_names, list->num_parents,
466 ctx->reg_base + list->muxdiv_offset,
470 case branch_inverter:
471 clk = rockchip_clk_register_inverter(
472 list->name, list->parent_names,
474 ctx->reg_base + list->muxdiv_offset,
475 list->div_shift, list->div_flags, &ctx->lock);
478 clk = rockchip_clk_register_factor_branch(
479 list->name, list->parent_names,
480 list->num_parents, ctx->reg_base,
481 list->div_shift, list->div_width,
482 list->gate_offset, list->gate_shift,
483 list->gate_flags, flags, &ctx->lock);
487 /* none of the cases above matched */
489 pr_err("%s: unknown clock type %d\n",
490 __func__, list->branch_type);
495 pr_err("%s: failed to register clock %s: %ld\n",
496 __func__, list->name, PTR_ERR(clk));
500 rockchip_clk_add_lookup(ctx, clk, list->id);
504 void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
505 unsigned int lookup_id,
506 const char *name, const char *const *parent_names,
508 const struct rockchip_cpuclk_reg_data *reg_data,
509 const struct rockchip_cpuclk_rate_table *rates,
514 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
515 reg_data, rates, nrates, ctx->reg_base,
518 pr_err("%s: failed to register clock %s: %ld\n",
519 __func__, name, PTR_ERR(clk));
523 rockchip_clk_add_lookup(ctx, clk, lookup_id);
526 void __init rockchip_clk_protect_critical(const char *const clocks[],
531 /* Protect the clocks that needs to stay on */
532 for (i = 0; i < nclocks; i++) {
533 struct clk *clk = __clk_lookup(clocks[i]);
536 clk_prepare_enable(clk);
540 static void __iomem *rst_base;
541 static unsigned int reg_restart;
542 static void (*cb_restart)(void);
543 static int rockchip_restart_notify(struct notifier_block *this,
544 unsigned long mode, void *cmd)
549 writel(0xfdb9, rst_base + reg_restart);
553 static struct notifier_block rockchip_restart_handler = {
554 .notifier_call = rockchip_restart_notify,
558 void __init rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
559 unsigned int reg, void (*cb)(void))
563 rst_base = ctx->reg_base;
566 ret = register_restart_handler(&rockchip_restart_handler);
568 pr_err("%s: cannot register restart handler, %d\n",