2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #include <linux/slab.h>
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/regmap.h>
28 #include <linux/reboot.h>
32 * Register a clock branch.
33 * Most clock branches have a form like
39 * sometimes without one of those components.
41 static struct clk *rockchip_clk_register_branch(const char *name,
42 const char *const *parent_names, u8 num_parents, void __iomem *base,
43 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
44 u8 div_shift, u8 div_width, u8 div_flags,
45 struct clk_div_table *div_table, int gate_offset,
46 u8 gate_shift, u8 gate_flags, unsigned long flags,
50 struct clk_mux *mux = NULL;
51 struct clk_gate *gate = NULL;
52 struct clk_divider *div = NULL;
53 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
56 if (num_parents > 1) {
57 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
59 return ERR_PTR(-ENOMEM);
61 mux->reg = base + muxdiv_offset;
62 mux->shift = mux_shift;
63 mux->mask = BIT(mux_width) - 1;
64 mux->flags = mux_flags;
66 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
70 if (gate_offset >= 0) {
71 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
73 return ERR_PTR(-ENOMEM);
75 gate->flags = gate_flags;
76 gate->reg = base + gate_offset;
77 gate->bit_idx = gate_shift;
79 gate_ops = &clk_gate_ops;
83 div = kzalloc(sizeof(*div), GFP_KERNEL);
85 return ERR_PTR(-ENOMEM);
87 div->flags = div_flags;
88 div->reg = base + muxdiv_offset;
89 div->shift = div_shift;
90 div->width = div_width;
92 div->table = div_table;
93 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
98 clk = clk_register_composite(NULL, name, parent_names, num_parents,
99 mux ? &mux->hw : NULL, mux_ops,
100 div ? &div->hw : NULL, div_ops,
101 gate ? &gate->hw : NULL, gate_ops,
107 struct rockchip_clk_frac {
108 struct notifier_block clk_nb;
109 struct clk_fractional_divider div;
110 struct clk_gate gate;
113 const struct clk_ops *mux_ops;
116 bool rate_change_remuxed;
120 #define to_rockchip_clk_frac_nb(nb) \
121 container_of(nb, struct rockchip_clk_frac, clk_nb)
123 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
124 unsigned long event, void *data)
126 struct clk_notifier_data *ndata = data;
127 struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
128 struct clk_mux *frac_mux = &frac->mux;
131 pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
132 __func__, event, ndata->old_rate, ndata->new_rate);
133 if (event == PRE_RATE_CHANGE) {
134 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
135 if (frac->rate_change_idx != frac->mux_frac_idx) {
136 frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
137 frac->rate_change_remuxed = 1;
139 } else if (event == POST_RATE_CHANGE) {
141 * The POST_RATE_CHANGE notifier runs directly after the
142 * divider clock is set in clk_change_rate, so we'll have
143 * remuxed back to the original parent before clk_change_rate
144 * reaches the mux itself.
146 if (frac->rate_change_remuxed) {
147 frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
148 frac->rate_change_remuxed = 0;
152 return notifier_from_errno(ret);
155 static struct clk *rockchip_clk_register_frac_branch(const char *name,
156 const char *const *parent_names, u8 num_parents,
157 void __iomem *base, int muxdiv_offset, u8 div_flags,
158 int gate_offset, u8 gate_shift, u8 gate_flags,
159 unsigned long flags, struct rockchip_clk_branch *child,
162 struct rockchip_clk_frac *frac;
164 struct clk_gate *gate = NULL;
165 struct clk_fractional_divider *div = NULL;
166 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
168 if (muxdiv_offset < 0)
169 return ERR_PTR(-EINVAL);
171 if (child && child->branch_type != branch_mux) {
172 pr_err("%s: fractional child clock for %s can only be a mux\n",
174 return ERR_PTR(-EINVAL);
177 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
179 return ERR_PTR(-ENOMEM);
181 if (gate_offset >= 0) {
183 gate->flags = gate_flags;
184 gate->reg = base + gate_offset;
185 gate->bit_idx = gate_shift;
187 gate_ops = &clk_gate_ops;
191 div->flags = div_flags;
192 div->reg = base + muxdiv_offset;
195 div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
198 div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
200 div_ops = &clk_fractional_divider_ops;
202 clk = clk_register_composite(NULL, name, parent_names, num_parents,
205 gate ? &gate->hw : NULL, gate_ops,
206 flags | CLK_SET_RATE_UNGATE);
213 struct clk_mux *frac_mux = &frac->mux;
214 struct clk_init_data init;
218 frac->mux_frac_idx = -1;
219 for (i = 0; i < child->num_parents; i++) {
220 if (!strcmp(name, child->parent_names[i])) {
221 pr_debug("%s: found fractional parent in mux at pos %d\n",
223 frac->mux_frac_idx = i;
228 frac->mux_ops = &clk_mux_ops;
229 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
231 frac_mux->reg = base + child->muxdiv_offset;
232 frac_mux->shift = child->mux_shift;
233 frac_mux->mask = BIT(child->mux_width) - 1;
234 frac_mux->flags = child->mux_flags;
235 frac_mux->lock = lock;
236 frac_mux->hw.init = &init;
238 init.name = child->name;
239 init.flags = child->flags | CLK_SET_RATE_PARENT;
240 init.ops = frac->mux_ops;
241 init.parent_names = child->parent_names;
242 init.num_parents = child->num_parents;
244 mux_clk = clk_register(NULL, &frac_mux->hw);
248 rockchip_clk_add_lookup(mux_clk, child->id);
250 /* notifier on the fraction divider to catch rate changes */
251 if (frac->mux_frac_idx >= 0) {
252 ret = clk_notifier_register(clk, &frac->clk_nb);
254 pr_err("%s: failed to register clock notifier for %s\n",
257 pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
258 __func__, name, child->name);
265 static DEFINE_SPINLOCK(clk_lock);
266 static struct clk **clk_table;
267 static void __iomem *reg_base;
268 static struct clk_onecell_data clk_data;
269 static struct device_node *cru_node;
270 static struct regmap *grf;
272 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
273 unsigned long nr_clks)
277 grf = ERR_PTR(-EPROBE_DEFER);
279 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
281 pr_err("%s: could not allocate clock lookup table\n", __func__);
283 clk_data.clks = clk_table;
284 clk_data.clk_num = nr_clks;
285 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
288 struct regmap *rockchip_clk_get_grf(void)
291 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
295 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
301 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
302 unsigned int nr_pll, int grf_lock_offset)
307 for (idx = 0; idx < nr_pll; idx++, list++) {
308 clk = rockchip_clk_register_pll(list->type, list->name,
309 list->parent_names, list->num_parents,
310 reg_base, list->con_offset, grf_lock_offset,
311 list->lock_shift, list->mode_offset,
312 list->mode_shift, list->rate_table,
313 list->pll_flags, &clk_lock);
315 pr_err("%s: failed to register clock %s\n", __func__,
320 rockchip_clk_add_lookup(clk, list->id);
324 void __init rockchip_clk_register_branches(
325 struct rockchip_clk_branch *list,
328 struct clk *clk = NULL;
332 for (idx = 0; idx < nr_clk; idx++, list++) {
335 /* catch simple muxes */
336 switch (list->branch_type) {
338 clk = clk_register_mux(NULL, list->name,
339 list->parent_names, list->num_parents,
340 flags, reg_base + list->muxdiv_offset,
341 list->mux_shift, list->mux_width,
342 list->mux_flags, &clk_lock);
346 clk = clk_register_divider_table(NULL,
347 list->name, list->parent_names[0],
348 flags, reg_base + list->muxdiv_offset,
349 list->div_shift, list->div_width,
350 list->div_flags, list->div_table,
353 clk = clk_register_divider(NULL, list->name,
354 list->parent_names[0], flags,
355 reg_base + list->muxdiv_offset,
356 list->div_shift, list->div_width,
357 list->div_flags, &clk_lock);
359 case branch_fraction_divider:
360 clk = rockchip_clk_register_frac_branch(list->name,
361 list->parent_names, list->num_parents,
362 reg_base, list->muxdiv_offset, list->div_flags,
363 list->gate_offset, list->gate_shift,
364 list->gate_flags, flags, list->child,
368 flags |= CLK_SET_RATE_PARENT;
370 clk = clk_register_gate(NULL, list->name,
371 list->parent_names[0], flags,
372 reg_base + list->gate_offset,
373 list->gate_shift, list->gate_flags, &clk_lock);
375 case branch_composite:
376 clk = rockchip_clk_register_branch(list->name,
377 list->parent_names, list->num_parents,
378 reg_base, list->muxdiv_offset, list->mux_shift,
379 list->mux_width, list->mux_flags,
380 list->div_shift, list->div_width,
381 list->div_flags, list->div_table,
382 list->gate_offset, list->gate_shift,
383 list->gate_flags, flags, &clk_lock);
386 clk = rockchip_clk_register_mmc(
388 list->parent_names, list->num_parents,
389 reg_base + list->muxdiv_offset,
393 case branch_inverter:
394 clk = rockchip_clk_register_inverter(
395 list->name, list->parent_names,
397 reg_base + list->muxdiv_offset,
398 list->div_shift, list->div_flags, &clk_lock);
402 /* none of the cases above matched */
404 pr_err("%s: unknown clock type %d\n",
405 __func__, list->branch_type);
410 pr_err("%s: failed to register clock %s: %ld\n",
411 __func__, list->name, PTR_ERR(clk));
415 rockchip_clk_add_lookup(clk, list->id);
419 void __init rockchip_clk_register_armclk(unsigned int lookup_id,
420 const char *name, const char *const *parent_names,
422 const struct rockchip_cpuclk_reg_data *reg_data,
423 const struct rockchip_cpuclk_rate_table *rates,
428 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
429 reg_data, rates, nrates, reg_base,
432 pr_err("%s: failed to register clock %s: %ld\n",
433 __func__, name, PTR_ERR(clk));
437 rockchip_clk_add_lookup(clk, lookup_id);
440 void __init rockchip_clk_protect_critical(const char *const clocks[],
445 /* Protect the clocks that needs to stay on */
446 for (i = 0; i < nclocks; i++) {
447 struct clk *clk = __clk_lookup(clocks[i]);
450 clk_prepare_enable(clk);
454 static unsigned int reg_restart;
455 static int rockchip_restart_notify(struct notifier_block *this,
456 unsigned long mode, void *cmd)
458 writel(0xfdb9, reg_base + reg_restart);
462 static struct notifier_block rockchip_restart_handler = {
463 .notifier_call = rockchip_restart_notify,
467 void __init rockchip_register_restart_notifier(unsigned int reg)
472 ret = register_restart_handler(&rockchip_restart_handler);
474 pr_err("%s: cannot register restart handler, %d\n",