drivers/clk/rockchip/clk.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * based on
   6  *
   7  * samsung/clk.c
   8  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   9  * Copyright (c) 2013 Linaro Ltd.
  10  * Author: Thomas Abraham <thomas.ab@samsung.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/mfd/syscon.h>
  27 #include <linux/regmap.h>
  28 #include <linux/reboot.h>
  29 #include "clk.h"
  30
  31 /**
  32  * Register a clock branch.
  33  * Most clock branches have a form like
  34  *
  35  * src1 --|--\
  36  *        |M |--[GATE]-[DIV]-
  37  * src2 --|--/
  38  *
  39  * sometimes without one of those components.
  40  */
  41 static struct clk *rockchip_clk_register_branch(const char *name,
  42                 const char *const *parent_names, u8 num_parents, void __iomem *base,
  43                 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
  44                 u8 div_shift, u8 div_width, u8 div_flags,
  45                 struct clk_div_table *div_table, int gate_offset,
  46                 u8 gate_shift, u8 gate_flags, unsigned long flags,
  47                 spinlock_t *lock)
  48 {
  49         struct clk *clk;
  50         struct clk_mux *mux = NULL;
  51         struct clk_gate *gate = NULL;
  52         struct clk_divider *div = NULL;
  53         const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
  54                              *gate_ops = NULL;
  55
  56         if (num_parents > 1) {
  57                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  58                 if (!mux)
  59                         return ERR_PTR(-ENOMEM);
  60
  61                 mux->reg = base + muxdiv_offset;
  62                 mux->shift = mux_shift;
  63                 mux->mask = BIT(mux_width) - 1;
  64                 mux->flags = mux_flags;
  65                 mux->lock = lock;
  66                 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
  67                                                         : &clk_mux_ops;
  68         }
  69
  70         if (gate_offset >= 0) {
  71                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  72                 if (!gate)
  73                         return ERR_PTR(-ENOMEM);
  74
  75                 gate->flags = gate_flags;
  76                 gate->reg = base + gate_offset;
  77                 gate->bit_idx = gate_shift;
  78                 gate->lock = lock;
  79                 gate_ops = &clk_gate_ops;
  80         }
  81
  82         if (div_width > 0) {
  83                 div = kzalloc(sizeof(*div), GFP_KERNEL);
  84                 if (!div)
  85                         return ERR_PTR(-ENOMEM);
  86
  87                 div->flags = div_flags;
  88                 div->reg = base + muxdiv_offset;
  89                 div->shift = div_shift;
  90                 div->width = div_width;
  91                 div->lock = lock;
  92                 div->table = div_table;
  93                 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
  94                                                 ? &clk_divider_ro_ops
  95                                                 : &clk_divider_ops;
  96         }
  97
  98         clk = clk_register_composite(NULL, name, parent_names, num_parents,
  99                                      mux ? &mux->hw : NULL, mux_ops,
 100                                      div ? &div->hw : NULL, div_ops,
 101                                      gate ? &gate->hw : NULL, gate_ops,
 102                                      flags);
 103
 104         return clk;
 105 }
 106
 107 struct rockchip_clk_frac {
 108         struct notifier_block                   clk_nb;
 109         struct clk_fractional_divider           div;
 110         struct clk_gate                         gate;
 111
 112         struct clk_mux                          mux;
 113         const struct clk_ops                    *mux_ops;
 114         int                                     mux_frac_idx;
 115
 116         bool                                    rate_change_remuxed;
 117         int                                     rate_change_idx;
 118 };
 119
 120 #define to_rockchip_clk_frac_nb(nb) \
 121                         container_of(nb, struct rockchip_clk_frac, clk_nb)
 122
 123 static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 124                                          unsigned long event, void *data)
 125 {
 126         struct clk_notifier_data *ndata = data;
 127         struct rockchip_clk_frac *frac = to_rockchip_clk_frac_nb(nb);
 128         struct clk_mux *frac_mux = &frac->mux;
 129         int ret = 0;
 130
 131         pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
 132                  __func__, event, ndata->old_rate, ndata->new_rate);
 133         if (event == PRE_RATE_CHANGE) {
 134                 frac->rate_change_idx = frac->mux_ops->get_parent(&frac_mux->hw);
 135                 if (frac->rate_change_idx != frac->mux_frac_idx) {
 136                         frac->mux_ops->set_parent(&frac_mux->hw, frac->mux_frac_idx);
 137                         frac->rate_change_remuxed = 1;
 138                 }
 139         } else if (event == POST_RATE_CHANGE) {
 140                 /*
 141                  * The POST_RATE_CHANGE notifier runs directly after the
 142                  * divider clock is set in clk_change_rate, so we'll have
 143                  * remuxed back to the original parent before clk_change_rate
 144                  * reaches the mux itself.
 145                  */
 146                 if (frac->rate_change_remuxed) {
 147                         frac->mux_ops->set_parent(&frac_mux->hw, frac->rate_change_idx);
 148                         frac->rate_change_remuxed = 0;
 149                 }
 150         }
 151
 152         return notifier_from_errno(ret);
 153 }
 154
 155 static struct clk *rockchip_clk_register_frac_branch(const char *name,
 156                 const char *const *parent_names, u8 num_parents,
 157                 void __iomem *base, int muxdiv_offset, u8 div_flags,
 158                 int gate_offset, u8 gate_shift, u8 gate_flags,
 159                 unsigned long flags, struct rockchip_clk_branch *child,
 160                 spinlock_t *lock)
 161 {
 162         struct rockchip_clk_frac *frac;
 163         struct clk *clk;
 164         struct clk_gate *gate = NULL;
 165         struct clk_fractional_divider *div = NULL;
 166         const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
 167
 168         if (muxdiv_offset < 0)
 169                 return ERR_PTR(-EINVAL);
 170
 171         if (child && child->branch_type != branch_mux) {
 172                 pr_err("%s: fractional child clock for %s can only be a mux\n",
 173                        __func__, name);
 174                 return ERR_PTR(-EINVAL);
 175         }
 176
 177         frac = kzalloc(sizeof(*frac), GFP_KERNEL);
 178         if (!frac)
 179                 return ERR_PTR(-ENOMEM);
 180
 181         if (gate_offset >= 0) {
 182                 gate = &frac->gate;
 183                 gate->flags = gate_flags;
 184                 gate->reg = base + gate_offset;
 185                 gate->bit_idx = gate_shift;
 186                 gate->lock = lock;
 187                 gate_ops = &clk_gate_ops;
 188         }
 189
 190         div = &frac->div;
 191         div->flags = div_flags;
 192         div->reg = base + muxdiv_offset;
 193         div->mshift = 16;
 194         div->mwidth = 16;
 195         div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
 196         div->nshift = 0;
 197         div->nwidth = 16;
 198         div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
 199         div->lock = lock;
 200         div_ops = &clk_fractional_divider_ops;
 201
 202         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 203                                      NULL, NULL,
 204                                      &div->hw, div_ops,
 205                                      gate ? &gate->hw : NULL, gate_ops,
 206                                      flags | CLK_SET_RATE_UNGATE);
 207         if (IS_ERR(clk)) {
 208                 kfree(frac);
 209                 return clk;
 210         }
 211
 212         if (child) {
 213                 struct clk_mux *frac_mux = &frac->mux;
 214                 struct clk_init_data init;
 215                 struct clk *mux_clk;
 216                 int i, ret;
 217
 218                 frac->mux_frac_idx = -1;
 219                 for (i = 0; i < child->num_parents; i++) {
 220                         if (!strcmp(name, child->parent_names[i])) {
 221                                 pr_debug("%s: found fractional parent in mux at pos %d\n",
 222                                          __func__, i);
 223                                 frac->mux_frac_idx = i;
 224                                 break;
 225                         }
 226                 }
 227
 228                 frac->mux_ops = &clk_mux_ops;
 229                 frac->clk_nb.notifier_call = rockchip_clk_frac_notifier_cb;
 230
 231                 frac_mux->reg = base + child->muxdiv_offset;
 232                 frac_mux->shift = child->mux_shift;
 233                 frac_mux->mask = BIT(child->mux_width) - 1;
 234                 frac_mux->flags = child->mux_flags;
 235                 frac_mux->lock = lock;
 236                 frac_mux->hw.init = &init;
 237
 238                 init.name = child->name;
 239                 init.flags = child->flags | CLK_SET_RATE_PARENT;
 240                 init.ops = frac->mux_ops;
 241                 init.parent_names = child->parent_names;
 242                 init.num_parents = child->num_parents;
 243
 244                 mux_clk = clk_register(NULL, &frac_mux->hw);
 245                 if (IS_ERR(mux_clk))
 246                         return clk;
 247
 248                 rockchip_clk_add_lookup(mux_clk, child->id);
 249
 250                 /* notifier on the fraction divider to catch rate changes */
 251                 if (frac->mux_frac_idx >= 0) {
 252                         ret = clk_notifier_register(clk, &frac->clk_nb);
 253                         if (ret)
 254                                 pr_err("%s: failed to register clock notifier for %s\n",
 255                                                 __func__, name);
 256                 } else {
 257                         pr_warn("%s: could not find %s as parent of %s, rate changes may not work\n",
 258                                 __func__, name, child->name);
 259                 }
 260         }
 261
 262         return clk;
 263 }
 264
 265 static struct clk *rockchip_clk_register_factor_branch(const char *name,
 266                 const char *const *parent_names, u8 num_parents,
 267                 void __iomem *base, unsigned int mult, unsigned int div,
 268                 int gate_offset, u8 gate_shift, u8 gate_flags,
 269                 unsigned long flags, spinlock_t *lock)
 270 {
 271         struct clk *clk;
 272         struct clk_gate *gate = NULL;
 273         struct clk_fixed_factor *fix = NULL;
 274
 275         /* without gate, register a simple factor clock */
 276         if (gate_offset == 0) {
 277                 return clk_register_fixed_factor(NULL, name,
 278                                 parent_names[0], flags, mult,
 279                                 div);
 280         }
 281
 282         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 283         if (!gate)
 284                 return ERR_PTR(-ENOMEM);
 285
 286         gate->flags = gate_flags;
 287         gate->reg = base + gate_offset;
 288         gate->bit_idx = gate_shift;
 289         gate->lock = lock;
 290
 291         fix = kzalloc(sizeof(*fix), GFP_KERNEL);
 292         if (!fix) {
 293                 kfree(gate);
 294                 return ERR_PTR(-ENOMEM);
 295         }
 296
 297         fix->mult = mult;
 298         fix->div = div;
 299
 300         clk = clk_register_composite(NULL, name, parent_names, num_parents,
 301                                      NULL, NULL,
 302                                      &fix->hw, &clk_fixed_factor_ops,
 303                                      &gate->hw, &clk_gate_ops, flags);
 304         if (IS_ERR(clk)) {
 305                 kfree(fix);
 306                 kfree(gate);
 307         }
 308
 309         return clk;
 310 }
 311
 312 static DEFINE_SPINLOCK(clk_lock);
 313 static struct clk **clk_table;
 314 static void __iomem *reg_base;
 315 static struct clk_onecell_data clk_data;
 316 static struct device_node *cru_node;
 317 static struct regmap *grf;
 318
 319 void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
 320                               unsigned long nr_clks)
 321 {
 322         reg_base = base;
 323         cru_node = np;
 324         grf = ERR_PTR(-EPROBE_DEFER);
 325
 326         clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
 327         if (!clk_table)
 328                 pr_err("%s: could not allocate clock lookup table\n", __func__);
 329
 330         clk_data.clks = clk_table;
 331         clk_data.clk_num = nr_clks;
 332         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 333 }
 334
 335 struct regmap *rockchip_clk_get_grf(void)
 336 {
 337         if (IS_ERR(grf))
 338                 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
 339         return grf;
 340 }
 341
 342 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
 343 {
 344         if (clk_table && id)
 345                 clk_table[id] = clk;
 346 }
 347
 348 void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
 349                                 unsigned int nr_pll, int grf_lock_offset)
 350 {
 351         struct clk *clk;
 352         int idx;
 353
 354         for (idx = 0; idx < nr_pll; idx++, list++) {
 355                 clk = rockchip_clk_register_pll(list->type, list->name,
 356                                 list->parent_names, list->num_parents,
 357                                 reg_base, list->con_offset, grf_lock_offset,
 358                                 list->lock_shift, list->mode_offset,
 359                                 list->mode_shift, list->rate_table,
 360                                 list->pll_flags, &clk_lock);
 361                 if (IS_ERR(clk)) {
 362                         pr_err("%s: failed to register clock %s\n", __func__,
 363                                 list->name);
 364                         continue;
 365                 }
 366
 367                 rockchip_clk_add_lookup(clk, list->id);
 368         }
 369 }
 370
 371 void __init rockchip_clk_register_branches(
 372                                       struct rockchip_clk_branch *list,
 373                                       unsigned int nr_clk)
 374 {
 375         struct clk *clk = NULL;
 376         unsigned int idx;
 377         unsigned long flags;
 378
 379         for (idx = 0; idx < nr_clk; idx++, list++) {
 380                 flags = list->flags;
 381
 382                 /* catch simple muxes */
 383                 switch (list->branch_type) {
 384                 case branch_mux:
 385                         clk = clk_register_mux(NULL, list->name,
 386                                 list->parent_names, list->num_parents,
 387                                 flags, reg_base + list->muxdiv_offset,
 388                                 list->mux_shift, list->mux_width,
 389                                 list->mux_flags, &clk_lock);
 390                         break;
 391                 case branch_divider:
 392                         if (list->div_table)
 393                                 clk = clk_register_divider_table(NULL,
 394                                         list->name, list->parent_names[0],
 395                                         flags, reg_base + list->muxdiv_offset,
 396                                         list->div_shift, list->div_width,
 397                                         list->div_flags, list->div_table,
 398                                         &clk_lock);
 399                         else
 400                                 clk = clk_register_divider(NULL, list->name,
 401                                         list->parent_names[0], flags,
 402                                         reg_base + list->muxdiv_offset,
 403                                         list->div_shift, list->div_width,
 404                                         list->div_flags, &clk_lock);
 405                         break;
 406                 case branch_fraction_divider:
 407                         clk = rockchip_clk_register_frac_branch(list->name,
 408                                 list->parent_names, list->num_parents,
 409                                 reg_base, list->muxdiv_offset, list->div_flags,
 410                                 list->gate_offset, list->gate_shift,
 411                                 list->gate_flags, flags, list->child,
 412                                 &clk_lock);
 413                         break;
 414                 case branch_gate:
 415                         flags |= CLK_SET_RATE_PARENT;
 416
 417                         clk = clk_register_gate(NULL, list->name,
 418                                 list->parent_names[0], flags,
 419                                 reg_base + list->gate_offset,
 420                                 list->gate_shift, list->gate_flags, &clk_lock);
 421                         break;
 422                 case branch_composite:
 423                         clk = rockchip_clk_register_branch(list->name,
 424                                 list->parent_names, list->num_parents,
 425                                 reg_base, list->muxdiv_offset, list->mux_shift,
 426                                 list->mux_width, list->mux_flags,
 427                                 list->div_shift, list->div_width,
 428                                 list->div_flags, list->div_table,
 429                                 list->gate_offset, list->gate_shift,
 430                                 list->gate_flags, flags, &clk_lock);
 431                         break;
 432                 case branch_mmc:
 433                         clk = rockchip_clk_register_mmc(
 434                                 list->name,
 435                                 list->parent_names, list->num_parents,
 436                                 reg_base + list->muxdiv_offset,
 437                                 list->div_shift
 438                         );
 439                         break;
 440                 case branch_inverter:
 441                         clk = rockchip_clk_register_inverter(
 442                                 list->name, list->parent_names,
 443                                 list->num_parents,
 444                                 reg_base + list->muxdiv_offset,
 445                                 list->div_shift, list->div_flags, &clk_lock);
 446                         break;
 447                 case branch_factor:
 448                         clk = rockchip_clk_register_factor_branch(
 449                                 list->name, list->parent_names,
 450                                 list->num_parents, reg_base,
 451                                 list->div_shift, list->div_width,
 452                                 list->gate_offset, list->gate_shift,
 453                                 list->gate_flags, flags, &clk_lock);
 454                         break;
 455                 }
 456
 457                 /* none of the cases above matched */
 458                 if (!clk) {
 459                         pr_err("%s: unknown clock type %d\n",
 460                                __func__, list->branch_type);
 461                         continue;
 462                 }
 463
 464                 if (IS_ERR(clk)) {
 465                         pr_err("%s: failed to register clock %s: %ld\n",
 466                                __func__, list->name, PTR_ERR(clk));
 467                         continue;
 468                 }
 469
 470                 rockchip_clk_add_lookup(clk, list->id);
 471         }
 472 }
 473
 474 void __init rockchip_clk_register_armclk(unsigned int lookup_id,
 475                         const char *name, const char *const *parent_names,
 476                         u8 num_parents,
 477                         const struct rockchip_cpuclk_reg_data *reg_data,
 478                         const struct rockchip_cpuclk_rate_table *rates,
 479                         int nrates)
 480 {
 481         struct clk *clk;
 482
 483         clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
 484                                            reg_data, rates, nrates, reg_base,
 485                                            &clk_lock);
 486         if (IS_ERR(clk)) {
 487                 pr_err("%s: failed to register clock %s: %ld\n",
 488                        __func__, name, PTR_ERR(clk));
 489                 return;
 490         }
 491
 492         rockchip_clk_add_lookup(clk, lookup_id);
 493 }
 494
 495 void __init rockchip_clk_protect_critical(const char *const clocks[],
 496                                           int nclocks)
 497 {
 498         int i;
 499
 500         /* Protect the clocks that needs to stay on */
 501         for (i = 0; i < nclocks; i++) {
 502                 struct clk *clk = __clk_lookup(clocks[i]);
 503
 504                 if (clk)
 505                         clk_prepare_enable(clk);
 506         }
 507 }
 508
 509 static unsigned int reg_restart;
 510 static void (*cb_restart)(void);
 511 static int rockchip_restart_notify(struct notifier_block *this,
 512                                    unsigned long mode, void *cmd)
 513 {
 514         if (cb_restart)
 515                 cb_restart();
 516
 517         writel(0xfdb9, reg_base + reg_restart);
 518         return NOTIFY_DONE;
 519 }
 520
 521 static struct notifier_block rockchip_restart_handler = {
 522         .notifier_call = rockchip_restart_notify,
 523         .priority = 128,
 524 };
 525
 526 void __init rockchip_register_restart_notifier(unsigned int reg, void (*cb)(void))
 527 {
 528         int ret;
 529
 530         reg_restart = reg;
 531         cb_restart = cb;
 532         ret = register_restart_handler(&rockchip_restart_handler);
 533         if (ret)
 534                 pr_err("%s: cannot register restart handler, %d\n",
 535                        __func__, ret);
 536 }