drivers/clk/rockchip/clk-rk3399.c

   1 /*
   2  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
   3  * Author: Xing Zheng <zhengxing@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include <dt-bindings/clock/rk3399-cru.h>
  22 #include "clk.h"
  23
  24 #define RK3399_PMUGRF_SOC_CON0                  0x180
  25 #define RK3399_PMUCRU_PCLK_GATE_MASK            0x1
  26 #define RK3399_PMUCRU_PCLK_GATE_SHIFT           4
  27 #define RK3399_PMUCRU_PCLK_ALIVE_MASK           0x1
  28 #define RK3399_PMUCRU_PCLK_ALIVE_SHIFT          6
  29
  30 enum rk3399_plls {
  31         lpll, bpll, dpll, cpll, gpll, npll, vpll,
  32 };
  33
  34 enum rk3399_pmu_plls {
  35         ppll,
  36 };
  37
  38 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
  39         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  40         RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
  41         RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
  44         RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
  45         RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
  46         RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
  47         RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
  48         RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
  49         RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
  50         RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
  51         RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
  52         RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
  53         RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
  54         RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
  55         RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
  56         RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
  57         RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
  58         RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
  59         RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
  60         RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
  61         RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
  62         RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
  63         RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
  64         RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
  65         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  66         RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  67         RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  68         RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  69         RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  70         RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  71         RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  72         RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  73         RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  74         RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  75         RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  76         RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  77         RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  78         RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  79         RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  80         RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  81         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  82         RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  83         RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  84         RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  85         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  86         RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  87         RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
  88         RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
  89         RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
  90         RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
  91         RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
  92         RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
  93         RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
  94         RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
  95         RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
  96         RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
  97         RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
  98         RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
  99         RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
 100         RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
 101         RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
 102         RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
 103         RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
 104         RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
 105         RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
 106         RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
 107         { /* sentinel */ },
 108 };
 109
 110 /* CRU parents */
 111 PNAME(mux_pll_p)                                = { "xin24m", "xin32k" };
 112
 113 PNAME(mux_armclkl_p)                            = { "clk_core_l_lpll_src",
 114                                                     "clk_core_l_bpll_src",
 115                                                     "clk_core_l_dpll_src",
 116                                                     "clk_core_l_gpll_src" };
 117 PNAME(mux_armclkb_p)                            = { "clk_core_b_lpll_src",
 118                                                     "clk_core_b_bpll_src",
 119                                                     "clk_core_b_dpll_src",
 120                                                     "clk_core_b_gpll_src" };
 121 PNAME(mux_ddrc_p)                               = { "clk_ddrc_lpll_src",
 122                                                     "clk_ddrc_bpll_src",
 123                                                     "clk_ddrc_dpll_src",
 124                                                     "clk_ddrc_gpll_src" };
 125 PNAME(mux_aclk_cci_p)                           = { "cpll_aclk_cci_src",
 126                                                     "gpll_aclk_cci_src",
 127                                                     "npll_aclk_cci_src",
 128                                                     "vpll_aclk_cci_src" };
 129 PNAME(mux_cci_trace_p)                          = { "cpll_cci_trace", "gpll_cci_trace" };
 130 PNAME(mux_cs_p)                                 = { "cpll_cs", "gpll_cs", "npll_cs"};
 131 PNAME(mux_aclk_perihp_p)                        = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
 132
 133 PNAME(mux_pll_src_cpll_gpll_p)                  = { "cpll", "gpll" };
 134 PNAME(mux_pll_src_cpll_gpll_npll_p)             = { "cpll", "gpll", "npll" };
 135 PNAME(mux_pll_src_cpll_gpll_ppll_p)             = { "cpll", "gpll", "ppll" };
 136 PNAME(mux_pll_src_cpll_gpll_upll_p)             = { "cpll", "gpll", "upll" };
 137 PNAME(mux_pll_src_npll_cpll_gpll_p)             = { "npll", "cpll", "gpll" };
 138 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p)        = { "cpll", "gpll", "npll", "ppll" };
 139 PNAME(mux_pll_src_cpll_gpll_npll_24m_p)         = { "cpll", "gpll", "npll", "xin24m" };
 140 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p)  = { "cpll", "gpll", "npll", "clk_usbphy_480m" };
 141 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p)        = { "ppll", "cpll", "gpll", "npll", "upll" };
 142 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p)    = { "cpll", "gpll", "npll", "upll", "xin24m" };
 143 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
 144
 145 PNAME(mux_pll_src_vpll_cpll_gpll_p)             = { "vpll", "cpll", "gpll" };
 146 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p)        = { "vpll", "cpll", "gpll", "npll" };
 147 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p)         = { "vpll", "cpll", "gpll", "xin24m" };
 148
 149 PNAME(mux_dclk_vop0_p)                          = { "dclk_vop0_div", "dclk_vop0_frac" };
 150 PNAME(mux_dclk_vop1_p)                          = { "dclk_vop1_div", "dclk_vop1_frac" };
 151
 152 PNAME(mux_clk_cif_p)                            = { "clk_cifout_div", "xin24m" };
 153
 154 PNAME(mux_pll_src_24m_usbphy480m_p)             = { "xin24m", "clk_usbphy_480m" };
 155 PNAME(mux_pll_src_24m_pciephy_p)                = { "xin24m", "clk_pciephy_ref100m" };
 156 PNAME(mux_pll_src_24m_32k_cpll_gpll_p)          = { "xin24m", "xin32k", "cpll", "gpll" };
 157 PNAME(mux_pciecore_cru_phy_p)                   = { "clk_pcie_core_cru", "clk_pcie_core_phy" };
 158
 159 PNAME(mux_aclk_emmc_p)                          = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" };
 160
 161 PNAME(mux_aclk_perilp0_p)                       = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
 162
 163 PNAME(mux_fclk_cm0s_p)                          = { "cpll_fclk_cm0s_src", "gpll_fclk_cm0s_src" };
 164
 165 PNAME(mux_hclk_perilp1_p)                       = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
 166
 167 PNAME(mux_clk_testout1_p)                       = { "clk_testout1_pll_src", "xin24m" };
 168 PNAME(mux_clk_testout2_p)                       = { "clk_testout2_pll_src", "xin24m" };
 169
 170 PNAME(mux_usbphy_480m_p)                        = { "clk_usbphy0_480m_src", "clk_usbphy1_480m_src" };
 171 PNAME(mux_aclk_gmac_p)                          = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" };
 172 PNAME(mux_rmii_p)                               = { "clk_gmac", "clkin_gmac" };
 173 PNAME(mux_spdif_p)                              = { "clk_spdif_div", "clk_spdif_frac",
 174                                                     "clkin_i2s", "xin12m" };
 175 PNAME(mux_i2s0_p)                               = { "clk_i2s0_div", "clk_i2s0_frac",
 176                                                     "clkin_i2s", "xin12m" };
 177 PNAME(mux_i2s1_p)                               = { "clk_i2s1_div", "clk_i2s1_frac",
 178                                                     "clkin_i2s", "xin12m" };
 179 PNAME(mux_i2s2_p)                               = { "clk_i2s2_div", "clk_i2s2_frac",
 180                                                     "clkin_i2s", "xin12m" };
 181 PNAME(mux_i2sch_p)                              = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
 182 PNAME(mux_i2sout_p)                             = { "clk_i2sout_src", "xin12m" };
 183
 184 PNAME(mux_uart0_p)                              = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
 185 PNAME(mux_uart1_p)                              = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
 186 PNAME(mux_uart2_p)                              = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
 187 PNAME(mux_uart3_p)                              = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
 188
 189 /* PMU CRU parents */
 190 PNAME(mux_ppll_24m_p)                           = { "ppll", "xin24m" };
 191 PNAME(mux_24m_ppll_p)                           = { "xin24m", "ppll" };
 192 PNAME(mux_fclk_cm0s_pmu_ppll_p)                 = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
 193 PNAME(mux_wifi_div_frac_p)                      = { "clk_wifi_div", "clk_wifi_frac" };
 194 PNAME(mux_uart4_div_frac_p)                     = { "clk_uart4_div", "clk_uart4_frac" };
 195 PNAME(mux_clk_testout2_2io_p)                   = { "clk_testout2", "clk_32k_suspend_pmu" };
 196
 197 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
 198         [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
 199                      RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
 200         [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
 201                      RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
 202         [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
 203                      RK3399_PLL_CON(19), 8, 31, 0, NULL),
 204         [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
 205                      RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 206         [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
 207                      RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 208         [npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
 209                      RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 210         [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
 211                      RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 212 };
 213
 214 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
 215         [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
 216                      RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
 217 };
 218
 219 #define MFLAGS CLK_MUX_HIWORD_MASK
 220 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 221 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 222 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 223
 224 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
 225         MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 226                         RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
 227
 228 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
 229         MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 230                         RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
 231
 232 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
 233         MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 234                         RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
 235
 236 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
 237         MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 238                         RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
 239
 240 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
 241         MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
 242                         RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
 243
 244 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
 245         MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
 246                         RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
 247
 248 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
 249         MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_div_frac_p, CLK_SET_RATE_PARENT,
 250                         RK3399_CLKSEL_CON(1), 14, 1, MFLAGS);
 251
 252 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
 253         .core_reg = RK3399_CLKSEL_CON(0),
 254         .div_core_shift = 0,
 255         .div_core_mask = 0x1f,
 256         .mux_core_alt = 3,
 257         .mux_core_main = 0,
 258         .mux_core_shift = 6,
 259         .mux_core_mask = 0x3,
 260 };
 261
 262 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
 263         .core_reg = RK3399_CLKSEL_CON(2),
 264         .div_core_shift = 0,
 265         .div_core_mask = 0x1f,
 266         .mux_core_alt = 3,
 267         .mux_core_main = 1,
 268         .mux_core_shift = 6,
 269         .mux_core_mask = 0x3,
 270 };
 271
 272 #define RK3399_DIV_ACLKM_MASK           0x1f
 273 #define RK3399_DIV_ACLKM_SHIFT          8
 274 #define RK3399_DIV_ATCLK_MASK           0x1f
 275 #define RK3399_DIV_ATCLK_SHIFT          0
 276 #define RK3399_DIV_PCLK_DBG_MASK        0x1f
 277 #define RK3399_DIV_PCLK_DBG_SHIFT       8
 278
 279 #define RK3399_CLKSEL0(_offs, _aclkm)                                   \
 280         {                                                               \
 281                 .reg = RK3399_CLKSEL_CON(0 + _offs),                    \
 282                 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK,     \
 283                                 RK3399_DIV_ACLKM_SHIFT),                \
 284         }
 285 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg)                            \
 286         {                                                               \
 287                 .reg = RK3399_CLKSEL_CON(1 + _offs),                    \
 288                 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK,     \
 289                                 RK3399_DIV_ATCLK_SHIFT) |               \
 290                        HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK,   \
 291                                 RK3399_DIV_PCLK_DBG_SHIFT),             \
 292         }
 293
 294 /* cluster_l: aclkm in clksel0, rest in clksel1 */
 295 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg)              \
 296         {                                                               \
 297                 .prate = _prate##U,                                     \
 298                 .divs = {                                               \
 299                         RK3399_CLKSEL0(0, _aclkm),                      \
 300                         RK3399_CLKSEL1(0, _atclk, _pdbg),               \
 301                 },                                                      \
 302         }
 303
 304 /* cluster_b: aclkm in clksel2, rest in clksel3 */
 305 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg)              \
 306         {                                                               \
 307                 .prate = _prate##U,                                     \
 308                 .divs = {                                               \
 309                         RK3399_CLKSEL0(2, _aclkm),                      \
 310                         RK3399_CLKSEL1(2, _atclk, _pdbg),               \
 311                 },                                                      \
 312         }
 313
 314 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
 315         RK3399_CPUCLKL_RATE(1800000000, 2, 8, 8),
 316         RK3399_CPUCLKL_RATE(1704000000, 2, 8, 8),
 317         RK3399_CPUCLKL_RATE(1608000000, 2, 7, 7),
 318         RK3399_CPUCLKL_RATE(1512000000, 2, 7, 7),
 319         RK3399_CPUCLKL_RATE(1488000000, 2, 6, 6),
 320         RK3399_CPUCLKL_RATE(1416000000, 2, 6, 6),
 321         RK3399_CPUCLKL_RATE(1200000000, 2, 5, 5),
 322         RK3399_CPUCLKL_RATE(1008000000, 2, 5, 5),
 323         RK3399_CPUCLKL_RATE( 816000000, 2, 4, 4),
 324         RK3399_CPUCLKL_RATE( 696000000, 2, 3, 3),
 325         RK3399_CPUCLKL_RATE( 600000000, 2, 3, 3),
 326         RK3399_CPUCLKL_RATE( 408000000, 2, 2, 2),
 327         RK3399_CPUCLKL_RATE( 312000000, 2, 2, 2),
 328 };
 329
 330 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
 331         RK3399_CPUCLKB_RATE(2184000000, 2, 11, 11),
 332         RK3399_CPUCLKB_RATE(2088000000, 2, 10, 10),
 333         RK3399_CPUCLKB_RATE(2040000000, 2, 10, 10),
 334         RK3399_CPUCLKB_RATE(1992000000, 2, 9, 9),
 335         RK3399_CPUCLKB_RATE(1896000000, 2, 9, 9),
 336         RK3399_CPUCLKB_RATE(1800000000, 2, 8, 8),
 337         RK3399_CPUCLKB_RATE(1704000000, 2, 8, 8),
 338         RK3399_CPUCLKB_RATE(1608000000, 2, 7, 7),
 339         RK3399_CPUCLKB_RATE(1512000000, 2, 6, 6),
 340         RK3399_CPUCLKB_RATE(1488000000, 2, 5, 5),
 341         RK3399_CPUCLKB_RATE(1416000000, 2, 5, 5),
 342         RK3399_CPUCLKB_RATE(1200000000, 2, 4, 4),
 343         RK3399_CPUCLKB_RATE(1008000000, 2, 4, 4),
 344         RK3399_CPUCLKB_RATE( 816000000, 2, 3, 3),
 345         RK3399_CPUCLKB_RATE( 696000000, 2, 3, 3),
 346         RK3399_CPUCLKB_RATE( 600000000, 2, 2, 2),
 347         RK3399_CPUCLKB_RATE( 408000000, 2, 2, 2),
 348         RK3399_CPUCLKB_RATE( 312000000, 2, 2, 2),
 349 };
 350
 351 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 352         /*
 353          * CRU Clock-Architecture
 354          */
 355
 356         /* usbphy */
 357         GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
 358                         RK3399_CLKGATE_CON(6), 5, GFLAGS),
 359         GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
 360                         RK3399_CLKGATE_CON(6), 6, GFLAGS),
 361
 362         GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
 363                         RK3399_CLKGATE_CON(13), 12, GFLAGS),
 364         GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
 365                         RK3399_CLKGATE_CON(13), 12, GFLAGS),
 366         MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
 367                         RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
 368
 369         MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
 370                         RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
 371
 372         COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, CLK_IGNORE_UNUSED,
 373                         RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
 374                         RK3399_CLKGATE_CON(6), 4, GFLAGS),
 375
 376         COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 377                         RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
 378                         RK3399_CLKGATE_CON(12), 0, GFLAGS),
 379         GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
 380                         RK3399_CLKGATE_CON(30), 0, GFLAGS),
 381         GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLK_IGNORE_UNUSED,
 382                         RK3399_CLKGATE_CON(30), 1, GFLAGS),
 383         GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLK_IGNORE_UNUSED,
 384                         RK3399_CLKGATE_CON(30), 2, GFLAGS),
 385         GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLK_IGNORE_UNUSED,
 386                         RK3399_CLKGATE_CON(30), 3, GFLAGS),
 387         GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLK_IGNORE_UNUSED,
 388                         RK3399_CLKGATE_CON(30), 4, GFLAGS),
 389
 390         GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLK_IGNORE_UNUSED,
 391                         RK3399_CLKGATE_CON(12), 1, GFLAGS),
 392         GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLK_IGNORE_UNUSED,
 393                         RK3399_CLKGATE_CON(12), 2, GFLAGS),
 394
 395         COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
 396                         RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
 397                         RK3399_CLKGATE_CON(12), 3, GFLAGS),
 398
 399         COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, CLK_IGNORE_UNUSED,
 400                         RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
 401                         RK3399_CLKGATE_CON(12), 4, GFLAGS),
 402
 403         COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
 404                         RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
 405                         RK3399_CLKGATE_CON(13), 4, GFLAGS),
 406
 407         COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
 408                         RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
 409                         RK3399_CLKGATE_CON(13), 5, GFLAGS),
 410
 411         COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, CLK_IGNORE_UNUSED,
 412                         RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
 413                         RK3399_CLKGATE_CON(13), 6, GFLAGS),
 414
 415         COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, CLK_IGNORE_UNUSED,
 416                         RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
 417                         RK3399_CLKGATE_CON(13), 7, GFLAGS),
 418
 419         /* little core */
 420         GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
 421                         RK3399_CLKGATE_CON(0), 0, GFLAGS),
 422         GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
 423                         RK3399_CLKGATE_CON(0), 1, GFLAGS),
 424         GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
 425                         RK3399_CLKGATE_CON(0), 2, GFLAGS),
 426         GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
 427                         RK3399_CLKGATE_CON(0), 3, GFLAGS),
 428
 429         COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
 430                         RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 431                         RK3399_CLKGATE_CON(0), 4, GFLAGS),
 432         COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
 433                         RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 434                         RK3399_CLKGATE_CON(0), 5, GFLAGS),
 435         COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
 436                         RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 437                         RK3399_CLKGATE_CON(0), 6, GFLAGS),
 438
 439         GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
 440                         RK3399_CLKGATE_CON(14), 12, GFLAGS),
 441         GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
 442                         RK3399_CLKGATE_CON(14), 13, GFLAGS),
 443
 444         GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
 445                         RK3399_CLKGATE_CON(14), 9, GFLAGS),
 446         GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
 447                         RK3399_CLKGATE_CON(14), 10, GFLAGS),
 448         GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
 449                         RK3399_CLKGATE_CON(14), 11, GFLAGS),
 450         GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
 451                         RK3399_CLKGATE_CON(0), 7, GFLAGS),
 452
 453         /* big core */
 454         GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
 455                         RK3399_CLKGATE_CON(1), 0, GFLAGS),
 456         GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
 457                         RK3399_CLKGATE_CON(1), 1, GFLAGS),
 458         GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
 459                         RK3399_CLKGATE_CON(1), 2, GFLAGS),
 460         GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
 461                         RK3399_CLKGATE_CON(1), 3, GFLAGS),
 462
 463         COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
 464                         RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 465                         RK3399_CLKGATE_CON(1), 4, GFLAGS),
 466         COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
 467                         RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 468                         RK3399_CLKGATE_CON(1), 5, GFLAGS),
 469         COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
 470                         RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 471                         RK3399_CLKGATE_CON(1), 6, GFLAGS),
 472
 473         GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
 474                         RK3399_CLKGATE_CON(14), 5, GFLAGS),
 475         GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
 476                         RK3399_CLKGATE_CON(14), 6, GFLAGS),
 477
 478         GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
 479                         RK3399_CLKGATE_CON(14), 1, GFLAGS),
 480         GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
 481                         RK3399_CLKGATE_CON(14), 3, GFLAGS),
 482         GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
 483                         RK3399_CLKGATE_CON(14), 4, GFLAGS),
 484
 485         DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0,
 486                         RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
 487
 488         GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
 489                         RK3399_CLKGATE_CON(14), 2, GFLAGS),
 490
 491         GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
 492                         RK3399_CLKGATE_CON(1), 7, GFLAGS),
 493
 494         /* gmac */
 495         GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
 496                         RK3399_CLKGATE_CON(6), 9, GFLAGS),
 497         GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
 498                         RK3399_CLKGATE_CON(6), 8, GFLAGS),
 499         COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, CLK_IGNORE_UNUSED,
 500                         RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
 501                         RK3399_CLKGATE_CON(6), 10, GFLAGS),
 502
 503         GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
 504                         RK3399_CLKGATE_CON(32), 0, GFLAGS),
 505         GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
 506                         RK3399_CLKGATE_CON(32), 1, GFLAGS),
 507         GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
 508                         RK3399_CLKGATE_CON(32), 4, GFLAGS),
 509
 510         COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
 511                         RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
 512                         RK3399_CLKGATE_CON(6), 11, GFLAGS),
 513         GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
 514                         RK3399_CLKGATE_CON(32), 2, GFLAGS),
 515         GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
 516                         RK3399_CLKGATE_CON(32), 3, GFLAGS),
 517
 518         COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 519                         RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
 520                         RK3399_CLKGATE_CON(5), 5, GFLAGS),
 521
 522         MUX(0, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
 523                         RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
 524         GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLK_IGNORE_UNUSED,
 525                         RK3399_CLKGATE_CON(5), 6, GFLAGS),
 526         GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLK_IGNORE_UNUSED,
 527                         RK3399_CLKGATE_CON(5), 7, GFLAGS),
 528         GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLK_IGNORE_UNUSED,
 529                         RK3399_CLKGATE_CON(5), 8, GFLAGS),
 530         GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLK_IGNORE_UNUSED,
 531                         RK3399_CLKGATE_CON(5), 9, GFLAGS),
 532
 533         /* spdif */
 534         COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 535                         RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
 536                         RK3399_CLKGATE_CON(8), 13, GFLAGS),
 537         COMPOSITE_FRAC(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
 538                         RK3399_CLKSEL_CON(99), 0,
 539                         RK3399_CLKGATE_CON(8), 14, GFLAGS),
 540         COMPOSITE_NODIV(SCLK_SPDIF_8CH, "clk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
 541                         RK3399_CLKSEL_CON(32), 13, 2, MFLAGS,
 542                         RK3399_CLKGATE_CON(8), 15, GFLAGS),
 543
 544         COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 545                         RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
 546                         RK3399_CLKGATE_CON(10), 6, GFLAGS),
 547         /* i2s */
 548         COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 549                         RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
 550                         RK3399_CLKGATE_CON(8), 3, GFLAGS),
 551         COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
 552                         RK3399_CLKSEL_CON(96), 0,
 553                         RK3399_CLKGATE_CON(8), 4, GFLAGS),
 554         MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
 555                         RK3399_CLKSEL_CON(28), 8, 2, MFLAGS),
 556         GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_IGNORE_UNUSED,
 557                         RK3399_CLKGATE_CON(8), 5, GFLAGS),
 558
 559         COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 560                         RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
 561                         RK3399_CLKGATE_CON(8), 6, GFLAGS),
 562         COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
 563                         RK3399_CLKSEL_CON(97), 0,
 564                         RK3399_CLKGATE_CON(8), 7, GFLAGS),
 565         MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
 566                         RK3399_CLKSEL_CON(29), 8, 2, MFLAGS),
 567         GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_IGNORE_UNUSED,
 568                         RK3399_CLKGATE_CON(8), 8, GFLAGS),
 569
 570         COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 571                         RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
 572                         RK3399_CLKGATE_CON(8), 9, GFLAGS),
 573         COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
 574                         RK3399_CLKSEL_CON(98), 0,
 575                         RK3399_CLKGATE_CON(8), 10, GFLAGS),
 576         MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
 577                         RK3399_CLKSEL_CON(30), 8, 2, MFLAGS),
 578         GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_IGNORE_UNUSED,
 579                         RK3399_CLKGATE_CON(8), 11, GFLAGS),
 580
 581         MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
 582                         RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
 583         COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, 0,
 584                         RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
 585                         RK3399_CLKGATE_CON(8), 12, GFLAGS),
 586
 587         /* uart */
 588         MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
 589                         RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
 590         COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
 591                         RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
 592                         RK3399_CLKGATE_CON(9), 0, GFLAGS),
 593         COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
 594                         RK3399_CLKSEL_CON(100), 0,
 595                         RK3399_CLKGATE_CON(9), 1, GFLAGS,
 596                         &rk3399_uart0_fracmux),
 597
 598         MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
 599                         RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
 600         COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
 601                         RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
 602                         RK3399_CLKGATE_CON(9), 2, GFLAGS),
 603         COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
 604                         RK3399_CLKSEL_CON(101), 0,
 605                         RK3399_CLKGATE_CON(9), 3, GFLAGS,
 606                         &rk3399_uart1_fracmux),
 607         COMPOSITE_NOMUX(0, "clk_uart2_src", "clk_uart_src", 0,
 608                         RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
 609                         RK3399_CLKGATE_CON(9), 4, GFLAGS),
 610         COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
 611                         RK3399_CLKSEL_CON(102), 0,
 612                         RK3399_CLKGATE_CON(9), 5, GFLAGS,
 613                         &rk3399_uart2_fracmux),
 614         COMPOSITE_NOMUX(0, "clk_uart3_src", "clk_uart_src", 0,
 615                         RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
 616                         RK3399_CLKGATE_CON(9), 6, GFLAGS),
 617         COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
 618                         RK3399_CLKSEL_CON(103), 0,
 619                         RK3399_CLKGATE_CON(9), 7, GFLAGS,
 620                         &rk3399_uart3_fracmux),
 621
 622         COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 623                         RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
 624                         RK3399_CLKGATE_CON(3), 4, GFLAGS),
 625
 626         GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
 627                         RK3399_CLKGATE_CON(18), 10, GFLAGS),
 628         GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
 629                         RK3399_CLKGATE_CON(18), 12, GFLAGS),
 630         GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
 631                         RK3399_CLKGATE_CON(18), 15, GFLAGS),
 632         GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
 633                         RK3399_CLKGATE_CON(19), 2, GFLAGS),
 634
 635         GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
 636                         RK3399_CLKGATE_CON(4), 11, GFLAGS),
 637         GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
 638                         RK3399_CLKGATE_CON(3), 5, GFLAGS),
 639         GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
 640                         RK3399_CLKGATE_CON(3), 6, GFLAGS),
 641
 642         /* cci */
 643         GATE(0, "cpll_cci", "cpll", CLK_IGNORE_UNUSED,
 644                         RK3399_CLKGATE_CON(2), 0, GFLAGS),
 645         GATE(0, "gpll_cci", "gpll", CLK_IGNORE_UNUSED,
 646                         RK3399_CLKGATE_CON(2), 1, GFLAGS),
 647         GATE(0, "npll_cci", "npll", CLK_IGNORE_UNUSED,
 648                         RK3399_CLKGATE_CON(2), 2, GFLAGS),
 649         GATE(0, "vpll_cci", "vpll", CLK_IGNORE_UNUSED,
 650                         RK3399_CLKGATE_CON(2), 3, GFLAGS),
 651
 652         COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
 653                         RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
 654                         RK3399_CLKGATE_CON(2), 4, GFLAGS),
 655
 656         GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 657                         RK3399_CLKGATE_CON(15), 0, GFLAGS),
 658         GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 659                         RK3399_CLKGATE_CON(15), 1, GFLAGS),
 660         GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 661                         RK3399_CLKGATE_CON(15), 2, GFLAGS),
 662         GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 663                         RK3399_CLKGATE_CON(15), 3, GFLAGS),
 664         GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 665                         RK3399_CLKGATE_CON(15), 4, GFLAGS),
 666         GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
 667                         RK3399_CLKGATE_CON(15), 7, GFLAGS),
 668
 669         GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
 670                         RK3399_CLKGATE_CON(2), 5, GFLAGS),
 671         GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
 672                         RK3399_CLKGATE_CON(2), 6, GFLAGS),
 673         COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
 674                         RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
 675                         RK3399_CLKGATE_CON(2), 7, GFLAGS),
 676
 677         GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
 678                         RK3399_CLKGATE_CON(2), 8, GFLAGS),
 679         GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
 680                         RK3399_CLKGATE_CON(2), 9, GFLAGS),
 681         GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
 682                         RK3399_CLKGATE_CON(2), 10, GFLAGS),
 683         COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
 684                         RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
 685         GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
 686                         RK3399_CLKGATE_CON(15), 5, GFLAGS),
 687         GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
 688                         RK3399_CLKGATE_CON(15), 6, GFLAGS),
 689
 690         /* vcodec */
 691         COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 692                         RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
 693                         RK3399_CLKGATE_CON(4), 0, GFLAGS),
 694         COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
 695                         RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
 696                         RK3399_CLKGATE_CON(4), 1, GFLAGS),
 697         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
 698                         RK3399_CLKGATE_CON(17), 2, GFLAGS),
 699         GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
 700                         RK3399_CLKGATE_CON(17), 3, GFLAGS),
 701
 702         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
 703                         RK3399_CLKGATE_CON(17), 0, GFLAGS),
 704         GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
 705                         RK3399_CLKGATE_CON(17), 1, GFLAGS),
 706
 707         /* vdu */
 708         COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 709                         RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
 710                         RK3399_CLKGATE_CON(4), 4, GFLAGS),
 711         COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 712                         RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
 713                         RK3399_CLKGATE_CON(4), 5, GFLAGS),
 714
 715         COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
 716                         RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
 717                         RK3399_CLKGATE_CON(4), 2, GFLAGS),
 718         COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
 719                         RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
 720                         RK3399_CLKGATE_CON(4), 3, GFLAGS),
 721         GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
 722                         RK3399_CLKGATE_CON(17), 10, GFLAGS),
 723         GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
 724                         RK3399_CLKGATE_CON(17), 11, GFLAGS),
 725
 726         GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
 727                         RK3399_CLKGATE_CON(17), 8, GFLAGS),
 728         GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
 729                         RK3399_CLKGATE_CON(17), 9, GFLAGS),
 730
 731         /* iep */
 732         COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
 733                         RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
 734                         RK3399_CLKGATE_CON(4), 6, GFLAGS),
 735         COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
 736                         RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
 737                         RK3399_CLKGATE_CON(4), 7, GFLAGS),
 738         GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", CLK_IGNORE_UNUSED,
 739                         RK3399_CLKGATE_CON(16), 2, GFLAGS),
 740         GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
 741                         RK3399_CLKGATE_CON(16), 3, GFLAGS),
 742
 743         GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", CLK_IGNORE_UNUSED,
 744                         RK3399_CLKGATE_CON(16), 0, GFLAGS),
 745         GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
 746                         RK3399_CLKGATE_CON(16), 1, GFLAGS),
 747
 748         /* rga */
 749         COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
 750                         RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
 751                         RK3399_CLKGATE_CON(4), 10, GFLAGS),
 752
 753         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,
 754                         RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
 755                         RK3399_CLKGATE_CON(4), 8, GFLAGS),
 756         COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
 757                         RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
 758                         RK3399_CLKGATE_CON(4), 9, GFLAGS),
 759         GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", CLK_IGNORE_UNUSED,
 760                         RK3399_CLKGATE_CON(16), 10, GFLAGS),
 761         GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
 762                         RK3399_CLKGATE_CON(16), 11, GFLAGS),
 763
 764         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", CLK_IGNORE_UNUSED,
 765                         RK3399_CLKGATE_CON(16), 8, GFLAGS),
 766         GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
 767                         RK3399_CLKGATE_CON(16), 9, GFLAGS),
 768
 769         /* center */
 770         COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 771                         RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
 772                         RK3399_CLKGATE_CON(3), 7, GFLAGS),
 773         GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
 774                         RK3399_CLKGATE_CON(19), 0, GFLAGS),
 775         GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
 776                         RK3399_CLKGATE_CON(19), 1, GFLAGS),
 777
 778         /* gpu */
 779         COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 780                         RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
 781                         RK3399_CLKGATE_CON(13), 0, GFLAGS),
 782         GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
 783                         RK3399_CLKGATE_CON(30), 8, GFLAGS),
 784         GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
 785                         RK3399_CLKGATE_CON(30), 10, GFLAGS),
 786         GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", CLK_IGNORE_UNUSED,
 787                         RK3399_CLKGATE_CON(30), 11, GFLAGS),
 788         GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", CLK_IGNORE_UNUSED,
 789                         RK3399_CLKGATE_CON(13), 1, GFLAGS),
 790
 791         /* perihp */
 792         GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
 793                         RK3399_CLKGATE_CON(5), 0, GFLAGS),
 794         GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
 795                         RK3399_CLKGATE_CON(5), 1, GFLAGS),
 796         COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
 797                         RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
 798                         RK3399_CLKGATE_CON(5), 2, GFLAGS),
 799         COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
 800                         RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
 801                         RK3399_CLKGATE_CON(5), 3, GFLAGS),
 802         COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 0,
 803                         RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
 804                         RK3399_CLKGATE_CON(5), 4, GFLAGS),
 805
 806         GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
 807                         RK3399_CLKGATE_CON(20), 2, GFLAGS),
 808         GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
 809                         RK3399_CLKGATE_CON(20), 10, GFLAGS),
 810         GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
 811                         RK3399_CLKGATE_CON(20), 12, GFLAGS),
 812
 813         GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", CLK_IGNORE_UNUSED,
 814                         RK3399_CLKGATE_CON(20), 5, GFLAGS),
 815         GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
 816                         RK3399_CLKGATE_CON(20), 6, GFLAGS),
 817         GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", CLK_IGNORE_UNUSED,
 818                         RK3399_CLKGATE_CON(20), 7, GFLAGS),
 819         GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLK_IGNORE_UNUSED,
 820                         RK3399_CLKGATE_CON(20), 8, GFLAGS),
 821         GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", CLK_IGNORE_UNUSED,
 822                         RK3399_CLKGATE_CON(20), 9, GFLAGS),
 823         GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
 824                         RK3399_CLKGATE_CON(20), 13, GFLAGS),
 825         GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
 826                         RK3399_CLKGATE_CON(20), 15, GFLAGS),
 827
 828         GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
 829                         RK3399_CLKGATE_CON(20), 4, GFLAGS),
 830         GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLK_IGNORE_UNUSED,
 831                         RK3399_CLKGATE_CON(20), 11, GFLAGS),
 832         GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
 833                         RK3399_CLKGATE_CON(20), 14, GFLAGS),
 834         GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", CLK_IGNORE_UNUSED,
 835                         RK3399_CLKGATE_CON(31), 8, GFLAGS),
 836
 837         /* sdio & sdmmc */
 838         COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 839                         RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
 840                         RK3399_CLKGATE_CON(12), 13, GFLAGS),
 841         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLK_IGNORE_UNUSED,
 842                         RK3399_CLKGATE_CON(33), 8, GFLAGS),
 843         GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
 844                         RK3399_CLKGATE_CON(33), 9, GFLAGS),
 845
 846         COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
 847                         RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
 848                         RK3399_CLKGATE_CON(6), 0, GFLAGS),
 849
 850         COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, CLK_IGNORE_UNUSED,
 851                         RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
 852                         RK3399_CLKGATE_CON(6), 1, GFLAGS),
 853
 854         MMC(SCLK_SDMMC_DRV,     "emmc_drv",    "clk_sdmmc", RK3399_SDMMC_CON0, 1),
 855         MMC(SCLK_SDMMC_SAMPLE,  "emmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
 856
 857         MMC(SCLK_SDIO_DRV,      "sdio_drv",    "clk_sdio",  RK3399_SDIO_CON0,  1),
 858         MMC(SCLK_SDIO_SAMPLE,   "sdio_sample", "clk_sdio",  RK3399_SDIO_CON1,  1),
 859
 860         /* pcie */
 861         COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, CLK_IGNORE_UNUSED,
 862                         RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
 863                         RK3399_CLKGATE_CON(6), 2, GFLAGS),
 864
 865         COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED,
 866                         RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
 867                         RK3399_CLKGATE_CON(12), 6, GFLAGS),
 868         MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
 869                         RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
 870
 871         COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
 872                         RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
 873                         RK3399_CLKGATE_CON(6), 3, GFLAGS),
 874         MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
 875                         RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
 876
 877         /* emmc */
 878         COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, CLK_IGNORE_UNUSED,
 879                         RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
 880                         RK3399_CLKGATE_CON(6), 14, GFLAGS),
 881
 882         GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
 883                         RK3399_CLKGATE_CON(6), 12, GFLAGS),
 884         GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
 885                         RK3399_CLKGATE_CON(6), 13, GFLAGS),
 886         COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
 887                         RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
 888         GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
 889                         RK3399_CLKGATE_CON(32), 8, GFLAGS),
 890         GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
 891                         RK3399_CLKGATE_CON(32), 9, GFLAGS),
 892         GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
 893                         RK3399_CLKGATE_CON(32), 10, GFLAGS),
 894
 895         /* perilp0 */
 896         GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
 897                         RK3399_CLKGATE_CON(7), 1, GFLAGS),
 898         GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
 899                         RK3399_CLKGATE_CON(7), 0, GFLAGS),
 900         COMPOSITE(0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
 901                         RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
 902                         RK3399_CLKGATE_CON(7), 2, GFLAGS),
 903         COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
 904                         RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
 905                         RK3399_CLKGATE_CON(7), 3, GFLAGS),
 906         COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
 907                         RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
 908                         RK3399_CLKGATE_CON(7), 4, GFLAGS),
 909
 910         /* aclk_perilp0 gates */
 911         GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
 912         GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
 913         GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
 914         GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
 915         GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
 916         GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
 917         GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
 918         GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
 919         GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
 920         GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
 921         GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
 922         GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 7, GFLAGS),
 923
 924         /* hclk_perilp0 gates */
 925         GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
 926         GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 5, GFLAGS),
 927         GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 6, GFLAGS),
 928         GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 14, GFLAGS),
 929         GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 15, GFLAGS),
 930         GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
 931
 932         /* pclk_perilp0 gates */
 933         GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
 934
 935         /* crypto */
 936         COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
 937                         RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
 938                         RK3399_CLKGATE_CON(7), 7, GFLAGS),
 939
 940         COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
 941                         RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
 942                         RK3399_CLKGATE_CON(7), 8, GFLAGS),
 943
 944         /* cm0s_perilp */
 945         GATE(0, "cpll_fclk_cm0s_src", "cpll", CLK_IGNORE_UNUSED,
 946                         RK3399_CLKGATE_CON(7), 6, GFLAGS),
 947         GATE(0, "gpll_fclk_cm0s_src", "gpll", CLK_IGNORE_UNUSED,
 948                         RK3399_CLKGATE_CON(7), 5, GFLAGS),
 949         COMPOSITE(0, "fclk_cm0s", mux_fclk_cm0s_p, CLK_IGNORE_UNUSED,
 950                         RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
 951                         RK3399_CLKGATE_CON(7), 9, GFLAGS),
 952
 953         /* fclk_cm0s gates */
 954         GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 8, GFLAGS),
 955         GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 9, GFLAGS),
 956         GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 10, GFLAGS),
 957         GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 11, GFLAGS),
 958         GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
 959
 960         /* perilp1 */
 961         GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
 962                         RK3399_CLKGATE_CON(8), 1, GFLAGS),
 963         GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
 964                         RK3399_CLKGATE_CON(8), 0, GFLAGS),
 965         COMPOSITE_NOGATE(0, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
 966                         RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
 967         COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
 968                         RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
 969                         RK3399_CLKGATE_CON(8), 2, GFLAGS),
 970
 971         /* hclk_perilp1 gates */
 972         GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
 973         GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
 974         GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 0, GFLAGS),
 975         GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 1, GFLAGS),
 976         GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 2, GFLAGS),
 977         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 3, GFLAGS),
 978         GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 4, GFLAGS),
 979         GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 5, GFLAGS),
 980         GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
 981
 982         /* pclk_perilp1 gates */
 983         GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
 984         GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
 985         GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
 986         GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
 987         GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
 988         GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
 989         GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
 990         GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
 991         GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
 992         GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
 993         GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
 994         GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
 995         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
 996         GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
 997         GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
 998         GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
 999         GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1000         GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1001         GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1002         GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1003         GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1004
1005         /* saradc */
1006         COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1007                         RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1008                         RK3399_CLKGATE_CON(9), 11, GFLAGS),
1009
1010         /* tsadc */
1011         COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, CLK_IGNORE_UNUSED,
1012                         RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1013                         RK3399_CLKGATE_CON(9), 10, GFLAGS),
1014
1015         /* cif_testout */
1016         MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1017                         RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1018         COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1019                         RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1020                         RK3399_CLKGATE_CON(13), 14, GFLAGS),
1021
1022         MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1023                         RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1024         COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1025                         RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1026                         RK3399_CLKGATE_CON(13), 15, GFLAGS),
1027
1028         /* vio */
1029         COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1030                         RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1031                         RK3399_CLKGATE_CON(11), 10, GFLAGS),
1032         COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1033                         RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1034                         RK3399_CLKGATE_CON(11), 1, GFLAGS),
1035
1036         GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1037                         RK3399_CLKGATE_CON(29), 0, GFLAGS),
1038
1039         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", CLK_IGNORE_UNUSED,
1040                         RK3399_CLKGATE_CON(29), 1, GFLAGS),
1041         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", CLK_IGNORE_UNUSED,
1042                         RK3399_CLKGATE_CON(29), 2, GFLAGS),
1043         GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1044                         RK3399_CLKGATE_CON(29), 12, GFLAGS),
1045
1046         /* hdcp */
1047         COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1048                         RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1049                         RK3399_CLKGATE_CON(11), 12, GFLAGS),
1050         COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1051                         RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1052                         RK3399_CLKGATE_CON(11), 3, GFLAGS),
1053         COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", CLK_IGNORE_UNUSED,
1054                         RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1055                         RK3399_CLKGATE_CON(11), 10, GFLAGS),
1056
1057         GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1058                         RK3399_CLKGATE_CON(29), 4, GFLAGS),
1059         GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", CLK_IGNORE_UNUSED,
1060                         RK3399_CLKGATE_CON(29), 10, GFLAGS),
1061
1062         GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1063                         RK3399_CLKGATE_CON(29), 5, GFLAGS),
1064         GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", CLK_IGNORE_UNUSED,
1065                         RK3399_CLKGATE_CON(29), 9, GFLAGS),
1066
1067         GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1068                         RK3399_CLKGATE_CON(29), 3, GFLAGS),
1069         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1070                         RK3399_CLKGATE_CON(29), 6, GFLAGS),
1071         GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLK_IGNORE_UNUSED,
1072                         RK3399_CLKGATE_CON(29), 7, GFLAGS),
1073         GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", CLK_IGNORE_UNUSED,
1074                         RK3399_CLKGATE_CON(29), 8, GFLAGS),
1075         GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", CLK_IGNORE_UNUSED,
1076                         RK3399_CLKGATE_CON(29), 11, GFLAGS),
1077
1078         /* edp */
1079         COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1080                         RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1081                         RK3399_CLKGATE_CON(11), 8, GFLAGS),
1082
1083         COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1084                         RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1085                         RK3399_CLKGATE_CON(11), 11, GFLAGS),
1086         GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1087                         RK3399_CLKGATE_CON(32), 12, GFLAGS),
1088         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLK_IGNORE_UNUSED,
1089                         RK3399_CLKGATE_CON(32), 13, GFLAGS),
1090
1091         /* hdmi */
1092         GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLK_IGNORE_UNUSED,
1093                         RK3399_CLKGATE_CON(11), 6, GFLAGS),
1094
1095         COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, CLK_IGNORE_UNUSED,
1096                         RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1097                         RK3399_CLKGATE_CON(11), 7, GFLAGS),
1098
1099         /* vop0 */
1100         COMPOSITE(0, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1101                         RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1102                         RK3399_CLKGATE_CON(10), 8, GFLAGS),
1103         COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1104                         RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1105                         RK3399_CLKGATE_CON(10), 9, GFLAGS),
1106
1107         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1108                         RK3399_CLKGATE_CON(28), 3, GFLAGS),
1109         GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1110                         RK3399_CLKGATE_CON(28), 1, GFLAGS),
1111
1112         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1113                         RK3399_CLKGATE_CON(28), 2, GFLAGS),
1114         GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1115                         RK3399_CLKGATE_CON(28), 0, GFLAGS),
1116
1117         COMPOSITE(0, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1118                         RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1119                         RK3399_CLKGATE_CON(10), 12, GFLAGS),
1120
1121         COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1122                         RK3399_CLKSEL_CON(106), 0,
1123                         &rk3399_dclk_vop0_fracmux),
1124
1125         COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1126                         RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1127                         RK3399_CLKGATE_CON(10), 14, GFLAGS),
1128
1129         /* vop1 */
1130         COMPOSITE(0, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1131                         RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1132                         RK3399_CLKGATE_CON(10), 10, GFLAGS),
1133         COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1134                         RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1135                         RK3399_CLKGATE_CON(10), 11, GFLAGS),
1136
1137         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1138                         RK3399_CLKGATE_CON(28), 7, GFLAGS),
1139         GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1140                         RK3399_CLKGATE_CON(28), 5, GFLAGS),
1141
1142         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1143                         RK3399_CLKGATE_CON(28), 6, GFLAGS),
1144         GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1145                         RK3399_CLKGATE_CON(28), 4, GFLAGS),
1146
1147         COMPOSITE(0, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, CLK_IGNORE_UNUSED,
1148                         RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1149                         RK3399_CLKGATE_CON(10), 13, GFLAGS),
1150
1151         COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1152                         RK3399_CLKSEL_CON(107), 0,
1153                         &rk3399_dclk_vop1_fracmux),
1154
1155         COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1156                         RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1157                         RK3399_CLKGATE_CON(10), 15, GFLAGS),
1158
1159         /* isp */
1160         COMPOSITE(0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1161                         RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1162                         RK3399_CLKGATE_CON(12), 8, GFLAGS),
1163         COMPOSITE_NOMUX(0, "hclk_isp0", "aclk_isp0", 0,
1164                         RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1165                         RK3399_CLKGATE_CON(12), 9, GFLAGS),
1166
1167         GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1168                         RK3399_CLKGATE_CON(27), 1, GFLAGS),
1169         GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1170                         RK3399_CLKGATE_CON(27), 5, GFLAGS),
1171         GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", CLK_IGNORE_UNUSED,
1172                         RK3399_CLKGATE_CON(27), 7, GFLAGS),
1173
1174         GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1175                         RK3399_CLKGATE_CON(27), 0, GFLAGS),
1176         GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", CLK_IGNORE_UNUSED,
1177                         RK3399_CLKGATE_CON(27), 4, GFLAGS),
1178
1179         COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1180                         RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1181                         RK3399_CLKGATE_CON(11), 4, GFLAGS),
1182
1183         COMPOSITE(SCLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1184                         RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1185                         RK3399_CLKGATE_CON(12), 10, GFLAGS),
1186         COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,
1187                         RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1188                         RK3399_CLKGATE_CON(12), 11, GFLAGS),
1189
1190         GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1191                         RK3399_CLKGATE_CON(27), 3, GFLAGS),
1192
1193         GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1194                         RK3399_CLKGATE_CON(27), 2, GFLAGS),
1195         GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", CLK_IGNORE_UNUSED,
1196                         RK3399_CLKGATE_CON(27), 8, GFLAGS),
1197
1198         COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1199                         RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1200                         RK3399_CLKGATE_CON(11), 5, GFLAGS),
1201
1202         /*
1203          * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1204          * so we ignore the mux and make clocks nodes as following,
1205          *
1206          * pclkin_cifinv --|-------\
1207          *                 |GSC20_9|-- pclkin_cifmux
1208          * pclkin_cif    --|-------/
1209          */
1210         GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cifmux", CLK_IGNORE_UNUSED,
1211                         RK3399_CLKGATE_CON(27), 6, GFLAGS),
1212
1213         /* cif */
1214         COMPOSITE(0, "clk_cifout_div", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
1215                         RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, 0, 5, DFLAGS,
1216                         RK3399_CLKGATE_CON(10), 7, GFLAGS),
1217         MUX(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT,
1218                         RK3399_CLKSEL_CON(56), 5, 1, MFLAGS),
1219
1220         /* gic */
1221         COMPOSITE(0, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1222                         RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1223                         RK3399_CLKGATE_CON(12), 12, GFLAGS),
1224
1225         GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1226         GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1227         GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1228         GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1229         GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1230         GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1231
1232         /* alive */
1233         /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1234         DIV(0, "pclk_alive", "gpll", 0,
1235                         RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1236
1237         GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1238         GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1239         GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1240         GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1241         GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1242
1243         GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1244         GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1245         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1246         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1247         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1248         GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1249         GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1250         GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1251         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1252
1253         GATE(0, "clk_mipidphy_ref", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1254         GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1255
1256         GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1257         GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1258         GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1259         GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1260
1261         /* testout */
1262         MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1263                         RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1264         COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1265                         RK3399_CLKSEL_CON(105), 0,
1266                         RK3399_CLKGATE_CON(13), 9, GFLAGS),
1267
1268         DIV(0, "clk_test_24m", "xin24m", 0,
1269                         RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1270
1271         /* spi */
1272         COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1273                         RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1274                         RK3399_CLKGATE_CON(9), 12, GFLAGS),
1275
1276         COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1277                         RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1278                         RK3399_CLKGATE_CON(9), 13, GFLAGS),
1279
1280         COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1281                         RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1282                         RK3399_CLKGATE_CON(9), 14, GFLAGS),
1283
1284         COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1285                         RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1286                         RK3399_CLKGATE_CON(9), 15, GFLAGS),
1287
1288         COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1289                         RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1290                         RK3399_CLKGATE_CON(13), 13, GFLAGS),
1291
1292         /* i2c */
1293         COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1294                         RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1295                         RK3399_CLKGATE_CON(10), 0, GFLAGS),
1296
1297         COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1298                         RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1299                         RK3399_CLKGATE_CON(10), 2, GFLAGS),
1300
1301         COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1302                         RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1303                         RK3399_CLKGATE_CON(10), 4, GFLAGS),
1304
1305         COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1306                         RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1307                         RK3399_CLKGATE_CON(10), 1, GFLAGS),
1308
1309         COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1310                         RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1311                         RK3399_CLKGATE_CON(10), 3, GFLAGS),
1312
1313         COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1314                         RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1315                         RK3399_CLKGATE_CON(10), 5, GFLAGS),
1316
1317         /* timer */
1318         GATE(SCLK_TIMER00, "clk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1319         GATE(SCLK_TIMER01, "clk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1320         GATE(SCLK_TIMER02, "clk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1321         GATE(SCLK_TIMER03, "clk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1322         GATE(SCLK_TIMER04, "clk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1323         GATE(SCLK_TIMER05, "clk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1324         GATE(SCLK_TIMER06, "clk_timer06", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1325         GATE(SCLK_TIMER07, "clk_timer07", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1326         GATE(SCLK_TIMER08, "clk_timer08", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1327         GATE(SCLK_TIMER09, "clk_timer09", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1328         GATE(SCLK_TIMER10, "clk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1329         GATE(SCLK_TIMER11, "clk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1330
1331         /* clk_test */
1332         /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1333         COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1334                         RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1335                         RK3368_CLKGATE_CON(13), 11, GFLAGS),
1336 };
1337
1338 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1339         /*
1340          * PMU CRU Clock-Architecture
1341          */
1342
1343         GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IGNORE_UNUSED,
1344                         RK3399_CLKGATE_CON(0), 1, GFLAGS),
1345
1346         COMPOSITE_NOGATE(0, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, CLK_IGNORE_UNUSED,
1347                         RK3399_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1348
1349         COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1350                         RK3399_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1351                         RK3399_CLKGATE_CON(0), 2, GFLAGS),
1352
1353         COMPOSITE_NOGATE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1354                         RK3399_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS),
1355
1356         COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1357                         RK3399_CLKSEL_CON(7), 0,
1358                         &rk3399_pmuclk_wifi_fracmux),
1359
1360         MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1361                         RK3399_CLKSEL_CON(1), 15, 1, MFLAGS),
1362
1363         COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1364                         RK3399_CLKSEL_CON(2), 0, 7, DFLAGS,
1365                         RK3399_CLKGATE_CON(0), 9, GFLAGS),
1366
1367         COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1368                         RK3399_CLKSEL_CON(3), 0, 7, DFLAGS,
1369                         RK3399_CLKGATE_CON(0), 11, GFLAGS),
1370
1371         COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1372                         RK3399_CLKSEL_CON(2), 8, 7, DFLAGS,
1373                         RK3399_CLKGATE_CON(0), 10, GFLAGS),
1374
1375         DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1376                         RK3399_CLKSEL_CON(4), 0, 10, DFLAGS),
1377         MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1378                         RK3399_CLKSEL_CON(4), 15, 1, MFLAGS),
1379
1380         COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, CLK_IGNORE_UNUSED,
1381                         RK3399_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1382                         RK3399_CLKGATE_CON(0), 5, GFLAGS),
1383
1384         COMPOSITE_FRAC(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1385                         RK3399_CLKSEL_CON(6), 0,
1386                         RK3399_CLKGATE_CON(0), 6, GFLAGS),
1387
1388         MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_div_frac_p, CLK_IGNORE_UNUSED,
1389                         RK3399_CLKSEL_CON(5), 8, 2, MFLAGS),
1390
1391         /* pmu clock gates */
1392         GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 3, GFLAGS),
1393         GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 4, GFLAGS),
1394
1395         GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(0), 7, GFLAGS),
1396
1397         GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 0, GFLAGS),
1398         GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 1, GFLAGS),
1399         GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 2, GFLAGS),
1400         GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 3, GFLAGS),
1401         GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 4, GFLAGS),
1402         GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 5, GFLAGS),
1403         GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 6, GFLAGS),
1404         GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 7, GFLAGS),
1405         GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 8, GFLAGS),
1406         GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 9, GFLAGS),
1407         GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 10, GFLAGS),
1408         GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 11, GFLAGS),
1409         GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 12, GFLAGS),
1410         GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 13, GFLAGS),
1411         GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 14, GFLAGS),
1412         GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(1), 15, GFLAGS),
1413
1414         GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 0, GFLAGS),
1415         GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 1, GFLAGS),
1416         GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 2, GFLAGS),
1417         GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 3, GFLAGS),
1418         GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(2), 5, GFLAGS),
1419 };
1420
1421 static const char *const rk3399_critical_clocks[] __initconst = {
1422         "aclk_cci_pre",
1423         "pclk_pmu_src",
1424 };
1425
1426 static void __init rk3399_clk_init(struct device_node *np)
1427 {
1428         struct rockchip_clk_provider *ctx;
1429         void __iomem *reg_base;
1430
1431         reg_base = of_iomap(np, 0);
1432         if (!reg_base) {
1433                 pr_err("%s: could not map cru region\n", __func__);
1434                 return;
1435         }
1436
1437         ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1438         if (IS_ERR(ctx)) {
1439                 pr_err("%s: rockchip clk init failed\n", __func__);
1440                 return;
1441         }
1442
1443         rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1444                                    ARRAY_SIZE(rk3399_pll_clks), -1);
1445
1446         rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1447                                   ARRAY_SIZE(rk3399_clk_branches));
1448
1449         rockchip_clk_protect_critical(rk3399_critical_clocks,
1450                                       ARRAY_SIZE(rk3399_critical_clocks));
1451
1452         rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1453                         mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1454                         &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1455                         ARRAY_SIZE(rk3399_cpuclkl_rates));
1456
1457         rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1458                         mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1459                         &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1460                         ARRAY_SIZE(rk3399_cpuclkb_rates));
1461
1462         rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1463                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1464
1465         rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1466
1467         rockchip_clk_of_add_provider(np, ctx);
1468 }
1469 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1470
1471 static void __init rk3399_pmu_clk_init(struct device_node *np)
1472 {
1473         struct rockchip_clk_provider *ctx;
1474         void __iomem *reg_base;
1475         struct regmap *grf;
1476
1477         reg_base = of_iomap(np, 0);
1478         if (!reg_base) {
1479                 pr_err("%s: could not map cru pmu region\n", __func__);
1480                 return;
1481         }
1482
1483         ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1484         if (IS_ERR(ctx)) {
1485                 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1486                 return;
1487         }
1488
1489         grf = rockchip_clk_get_grf(ctx);
1490         if (IS_ERR(grf)) {
1491                 pr_err("%s: pmugrf regmap not available\n", __func__);
1492                 return;
1493         }
1494
1495         /* enable pclk_pmc_src gate */
1496         regmap_write(grf, RK3399_PMUGRF_SOC_CON0,
1497                           HIWORD_UPDATE(0, RK3399_PMUCRU_PCLK_GATE_MASK,
1498                                         RK3399_PMUCRU_PCLK_GATE_SHIFT));
1499
1500         /* enable pclk_alive_gpll_src gate */
1501         regmap_write(grf, RK3399_PMUGRF_SOC_CON0,
1502                           HIWORD_UPDATE(0, RK3399_PMUCRU_PCLK_ALIVE_MASK,
1503                                         RK3399_PMUCRU_PCLK_ALIVE_SHIFT));
1504
1505         rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1506                                    ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1507
1508         rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1509                                   ARRAY_SIZE(rk3399_clk_pmu_branches));
1510
1511         rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1512                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
1513
1514         rockchip_clk_of_add_provider(np, ctx);
1515 }
1516 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);