2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
28 enum rk3399_pmu_plls {
32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
80 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
81 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
82 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
92 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
95 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
96 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
97 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
98 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
99 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
100 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
101 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
102 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
103 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
104 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
105 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
106 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
107 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
111 static struct rockchip_pll_rate_table rk3399_vpll_rates[] = {
112 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
113 RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912), /* vco = 2970000000 */
114 RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804), /* vco = 2967032965 */
115 RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912), /* vco = 2970000000 */
116 RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807), /* vco = 2967032970 */
117 RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640), /* vco = 3118500000 */
118 RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800), /* vco = 2967032960 */
119 RK3036_PLL_RATE( 74250000, 1, 129, 7, 6, 0, 15728640), /* vco = 3118500000 */
120 RK3036_PLL_RATE( 74175824, 1, 129, 7, 6, 0, 13550823), /* vco = 3115384608 */
121 RK3036_PLL_RATE( 65000000, 1, 113, 7, 6, 0, 12582912), /* vco = 2730000000 */
122 RK3036_PLL_RATE( 59340659, 1, 121, 7, 7, 0, 2581098), /* vco = 2907692291 */
123 RK3036_PLL_RATE( 54000000, 1, 110, 7, 7, 0, 4194304), /* vco = 2646000000 */
124 RK3036_PLL_RATE( 27000000, 1, 55, 7, 7, 0, 2097152), /* vco = 1323000000 */
125 RK3036_PLL_RATE( 26973027, 1, 55, 7, 7, 0, 1173232), /* vco = 1321678323 */
130 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
132 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
133 "clk_core_l_bpll_src",
134 "clk_core_l_dpll_src",
135 "clk_core_l_gpll_src" };
136 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
137 "clk_core_b_bpll_src",
138 "clk_core_b_dpll_src",
139 "clk_core_b_gpll_src" };
140 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
143 "vpll_aclk_cci_src" };
144 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
146 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
148 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
149 "gpll_aclk_perihp_src" };
151 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
152 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
153 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
154 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
155 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
156 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
158 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
160 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
162 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
164 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
166 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
167 "ppll", "upll", "xin24m" };
169 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
171 * We hope to be able to HDMI/DP can obtain better signal quality,
172 * therefore, we move VOP pwm and aclk clocks to other PLLs, let
173 * HDMI/DP phyclock can monopolize VPLL.
175 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p) = { "dummy_vpll", "cpll", "gpll",
177 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p) = { "dummy_vpll", "cpll", "gpll",
180 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
181 "dummy_dclk_vop0_frac" };
182 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
183 "dummy_dclk_vop1_frac" };
185 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
187 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
188 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
189 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
191 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
192 "clk_pcie_core_phy" };
194 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
195 "gpll_aclk_emmc_src" };
197 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
198 "gpll_aclk_perilp0_src" };
200 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
201 "gpll_fclk_cm0s_src" };
203 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
204 "gpll_hclk_perilp1_src" };
206 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
207 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
209 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
210 "clk_usbphy1_480m_src" };
211 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
212 "gpll_aclk_gmac_src" };
213 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
214 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
215 "clkin_i2s", "xin12m" };
216 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
217 "clkin_i2s", "xin12m" };
218 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
219 "clkin_i2s", "xin12m" };
220 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
221 "clkin_i2s", "xin12m" };
222 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
224 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
226 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
227 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
228 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
229 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
231 /* PMU CRU parents */
232 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
233 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
234 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
235 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
236 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
238 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
240 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
241 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
242 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
243 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
244 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
245 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
246 RK3399_PLL_CON(19), 8, 31, 0, NULL),
247 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
248 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
249 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
250 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
251 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
252 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
253 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
254 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_vpll_rates),
257 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
258 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
259 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
262 #define MFLAGS CLK_MUX_HIWORD_MASK
263 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
264 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
265 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
267 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
268 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
269 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
271 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
272 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
273 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
275 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
276 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
277 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
279 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
280 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
281 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
283 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
284 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
285 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
287 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
288 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
289 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
291 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
292 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
293 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
295 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
296 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
297 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
299 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
300 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
301 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
303 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
304 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
305 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
307 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
308 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT | CLK_KEEP_REQ_RATE,
309 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
311 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
312 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
313 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
315 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
316 .core_reg = RK3399_CLKSEL_CON(0),
318 .div_core_mask = 0x1f,
322 .mux_core_mask = 0x3,
325 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
326 .core_reg = RK3399_CLKSEL_CON(2),
328 .div_core_mask = 0x1f,
332 .mux_core_mask = 0x3,
335 #define RK3399_DIV_ACLKM_MASK 0x1f
336 #define RK3399_DIV_ACLKM_SHIFT 8
337 #define RK3399_DIV_ATCLK_MASK 0x1f
338 #define RK3399_DIV_ATCLK_SHIFT 0
339 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
340 #define RK3399_DIV_PCLK_DBG_SHIFT 8
342 #define RK3399_CLKSEL0(_offs, _aclkm) \
344 .reg = RK3399_CLKSEL_CON(0 + _offs), \
345 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
346 RK3399_DIV_ACLKM_SHIFT), \
348 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
350 .reg = RK3399_CLKSEL_CON(1 + _offs), \
351 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
352 RK3399_DIV_ATCLK_SHIFT) | \
353 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
354 RK3399_DIV_PCLK_DBG_SHIFT), \
357 /* cluster_l: aclkm in clksel0, rest in clksel1 */
358 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
360 .prate = _prate##U, \
362 RK3399_CLKSEL0(0, _aclkm), \
363 RK3399_CLKSEL1(0, _atclk, _pdbg), \
367 /* cluster_b: aclkm in clksel2, rest in clksel3 */
368 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
370 .prate = _prate##U, \
372 RK3399_CLKSEL0(2, _aclkm), \
373 RK3399_CLKSEL1(2, _atclk, _pdbg), \
377 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
378 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
379 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
380 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
381 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
382 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
383 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
384 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
385 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
386 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
387 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
388 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
389 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
390 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
391 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
392 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
395 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
396 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
397 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
398 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
399 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
400 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
401 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
402 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
403 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
404 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
405 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
406 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
407 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
408 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
409 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
410 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
411 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
412 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
413 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
414 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
415 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
416 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
419 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
421 * CRU Clock-Architecture
425 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
426 RK3399_CLKGATE_CON(6), 5, GFLAGS),
427 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
428 RK3399_CLKGATE_CON(6), 6, GFLAGS),
430 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
431 RK3399_CLKGATE_CON(13), 12, GFLAGS),
432 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
433 RK3399_CLKGATE_CON(13), 12, GFLAGS),
434 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
435 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
437 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
438 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
440 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
441 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
442 RK3399_CLKGATE_CON(6), 4, GFLAGS),
444 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
445 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
446 RK3399_CLKGATE_CON(12), 0, GFLAGS),
447 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
448 RK3399_CLKGATE_CON(30), 0, GFLAGS),
449 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
450 RK3399_CLKGATE_CON(30), 1, GFLAGS),
451 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
452 RK3399_CLKGATE_CON(30), 2, GFLAGS),
453 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
454 RK3399_CLKGATE_CON(30), 3, GFLAGS),
455 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
456 RK3399_CLKGATE_CON(30), 4, GFLAGS),
458 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
459 RK3399_CLKGATE_CON(12), 1, GFLAGS),
460 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
461 RK3399_CLKGATE_CON(12), 2, GFLAGS),
463 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
464 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
465 RK3399_CLKGATE_CON(12), 3, GFLAGS),
467 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
468 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
469 RK3399_CLKGATE_CON(12), 4, GFLAGS),
471 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
472 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
473 RK3399_CLKGATE_CON(13), 4, GFLAGS),
475 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
476 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
477 RK3399_CLKGATE_CON(13), 5, GFLAGS),
479 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
480 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
481 RK3399_CLKGATE_CON(13), 6, GFLAGS),
483 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
484 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
485 RK3399_CLKGATE_CON(13), 7, GFLAGS),
488 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
489 RK3399_CLKGATE_CON(0), 0, GFLAGS),
490 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
491 RK3399_CLKGATE_CON(0), 1, GFLAGS),
492 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
493 RK3399_CLKGATE_CON(0), 2, GFLAGS),
494 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
495 RK3399_CLKGATE_CON(0), 3, GFLAGS),
497 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
498 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
499 RK3399_CLKGATE_CON(0), 4, GFLAGS),
500 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
501 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
502 RK3399_CLKGATE_CON(0), 5, GFLAGS),
503 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
504 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
505 RK3399_CLKGATE_CON(0), 6, GFLAGS),
507 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
508 RK3399_CLKGATE_CON(14), 12, GFLAGS),
509 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
510 RK3399_CLKGATE_CON(14), 13, GFLAGS),
512 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
513 RK3399_CLKGATE_CON(14), 9, GFLAGS),
514 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
515 RK3399_CLKGATE_CON(14), 10, GFLAGS),
516 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
517 RK3399_CLKGATE_CON(14), 11, GFLAGS),
518 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", CLK_IGNORE_UNUSED,
519 RK3399_CLKGATE_CON(0), 7, GFLAGS),
522 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
523 RK3399_CLKGATE_CON(1), 0, GFLAGS),
524 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
525 RK3399_CLKGATE_CON(1), 1, GFLAGS),
526 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
527 RK3399_CLKGATE_CON(1), 2, GFLAGS),
528 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
529 RK3399_CLKGATE_CON(1), 3, GFLAGS),
531 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
532 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
533 RK3399_CLKGATE_CON(1), 4, GFLAGS),
534 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
535 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
536 RK3399_CLKGATE_CON(1), 5, GFLAGS),
537 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
538 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
539 RK3399_CLKGATE_CON(1), 6, GFLAGS),
541 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
542 RK3399_CLKGATE_CON(14), 5, GFLAGS),
543 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
544 RK3399_CLKGATE_CON(14), 6, GFLAGS),
546 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
547 RK3399_CLKGATE_CON(14), 1, GFLAGS),
548 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
549 RK3399_CLKGATE_CON(14), 3, GFLAGS),
550 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
551 RK3399_CLKGATE_CON(14), 4, GFLAGS),
553 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
554 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
556 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
557 RK3399_CLKGATE_CON(14), 2, GFLAGS),
559 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", CLK_IGNORE_UNUSED,
560 RK3399_CLKGATE_CON(1), 7, GFLAGS),
563 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
564 RK3399_CLKGATE_CON(6), 9, GFLAGS),
565 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
566 RK3399_CLKGATE_CON(6), 8, GFLAGS),
567 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
568 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
569 RK3399_CLKGATE_CON(6), 10, GFLAGS),
571 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
572 RK3399_CLKGATE_CON(32), 0, GFLAGS),
573 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
574 RK3399_CLKGATE_CON(32), 1, GFLAGS),
575 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
576 RK3399_CLKGATE_CON(32), 4, GFLAGS),
578 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
579 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
580 RK3399_CLKGATE_CON(6), 11, GFLAGS),
581 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
582 RK3399_CLKGATE_CON(32), 2, GFLAGS),
583 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
584 RK3399_CLKGATE_CON(32), 3, GFLAGS),
586 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
587 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
588 RK3399_CLKGATE_CON(5), 5, GFLAGS),
590 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
591 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
592 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
593 RK3399_CLKGATE_CON(5), 6, GFLAGS),
594 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
595 RK3399_CLKGATE_CON(5), 7, GFLAGS),
596 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
597 RK3399_CLKGATE_CON(5), 8, GFLAGS),
598 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
599 RK3399_CLKGATE_CON(5), 9, GFLAGS),
602 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
603 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
604 RK3399_CLKGATE_CON(8), 13, GFLAGS),
605 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
606 RK3399_CLKSEL_CON(99), 0,
607 RK3399_CLKGATE_CON(8), 14, GFLAGS,
608 &rk3399_spdif_fracmux),
609 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
610 RK3399_CLKGATE_CON(8), 15, GFLAGS),
612 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
613 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
614 RK3399_CLKGATE_CON(10), 6, GFLAGS),
616 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
617 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
618 RK3399_CLKGATE_CON(8), 3, GFLAGS),
619 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
620 RK3399_CLKSEL_CON(96), 0,
621 RK3399_CLKGATE_CON(8), 4, GFLAGS,
622 &rk3399_i2s0_fracmux),
623 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
624 RK3399_CLKGATE_CON(8), 5, GFLAGS),
626 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
627 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
628 RK3399_CLKGATE_CON(8), 6, GFLAGS),
629 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
630 RK3399_CLKSEL_CON(97), 0,
631 RK3399_CLKGATE_CON(8), 7, GFLAGS,
632 &rk3399_i2s1_fracmux),
633 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
634 RK3399_CLKGATE_CON(8), 8, GFLAGS),
636 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
637 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
638 RK3399_CLKGATE_CON(8), 9, GFLAGS),
639 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
640 RK3399_CLKSEL_CON(98), 0,
641 RK3399_CLKGATE_CON(8), 10, GFLAGS,
642 &rk3399_i2s2_fracmux),
643 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
644 RK3399_CLKGATE_CON(8), 11, GFLAGS),
646 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
647 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
648 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
649 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
650 RK3399_CLKGATE_CON(8), 12, GFLAGS),
653 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
654 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
655 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
656 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
657 RK3399_CLKGATE_CON(9), 0, GFLAGS),
658 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
659 RK3399_CLKSEL_CON(100), 0,
660 RK3399_CLKGATE_CON(9), 1, GFLAGS,
661 &rk3399_uart0_fracmux),
663 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
664 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
665 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
666 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
667 RK3399_CLKGATE_CON(9), 2, GFLAGS),
668 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
669 RK3399_CLKSEL_CON(101), 0,
670 RK3399_CLKGATE_CON(9), 3, GFLAGS,
671 &rk3399_uart1_fracmux),
673 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
674 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
675 RK3399_CLKGATE_CON(9), 4, GFLAGS),
676 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
677 RK3399_CLKSEL_CON(102), 0,
678 RK3399_CLKGATE_CON(9), 5, GFLAGS,
679 &rk3399_uart2_fracmux),
681 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
682 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
683 RK3399_CLKGATE_CON(9), 6, GFLAGS),
684 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
685 RK3399_CLKSEL_CON(103), 0,
686 RK3399_CLKGATE_CON(9), 7, GFLAGS,
687 &rk3399_uart3_fracmux),
689 COMPOSITE(0, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
690 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
691 RK3399_CLKGATE_CON(3), 4, GFLAGS),
693 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
694 RK3399_CLKGATE_CON(18), 10, GFLAGS),
695 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
696 RK3399_CLKGATE_CON(18), 12, GFLAGS),
697 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
698 RK3399_CLKGATE_CON(18), 15, GFLAGS),
699 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
700 RK3399_CLKGATE_CON(19), 2, GFLAGS),
702 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", CLK_IGNORE_UNUSED,
703 RK3399_CLKGATE_CON(4), 11, GFLAGS),
704 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", CLK_IGNORE_UNUSED,
705 RK3399_CLKGATE_CON(3), 5, GFLAGS),
706 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", CLK_IGNORE_UNUSED,
707 RK3399_CLKGATE_CON(3), 6, GFLAGS),
710 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
711 RK3399_CLKGATE_CON(2), 0, GFLAGS),
712 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
713 RK3399_CLKGATE_CON(2), 1, GFLAGS),
714 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
715 RK3399_CLKGATE_CON(2), 2, GFLAGS),
716 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
717 RK3399_CLKGATE_CON(2), 3, GFLAGS),
719 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
720 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
721 RK3399_CLKGATE_CON(2), 4, GFLAGS),
723 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
724 RK3399_CLKGATE_CON(15), 0, GFLAGS),
725 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
726 RK3399_CLKGATE_CON(15), 1, GFLAGS),
727 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
728 RK3399_CLKGATE_CON(15), 2, GFLAGS),
729 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
730 RK3399_CLKGATE_CON(15), 3, GFLAGS),
731 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
732 RK3399_CLKGATE_CON(15), 4, GFLAGS),
733 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
734 RK3399_CLKGATE_CON(15), 7, GFLAGS),
736 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
737 RK3399_CLKGATE_CON(2), 5, GFLAGS),
738 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
739 RK3399_CLKGATE_CON(2), 6, GFLAGS),
740 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
741 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
742 RK3399_CLKGATE_CON(2), 7, GFLAGS),
744 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
745 RK3399_CLKGATE_CON(2), 8, GFLAGS),
746 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
747 RK3399_CLKGATE_CON(2), 9, GFLAGS),
748 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
749 RK3399_CLKGATE_CON(2), 10, GFLAGS),
750 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
751 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
752 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
753 RK3399_CLKGATE_CON(15), 5, GFLAGS),
754 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
755 RK3399_CLKGATE_CON(15), 6, GFLAGS),
758 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
759 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
760 RK3399_CLKGATE_CON(4), 0, GFLAGS),
761 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
762 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
763 RK3399_CLKGATE_CON(4), 1, GFLAGS),
764 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
765 RK3399_CLKGATE_CON(17), 2, GFLAGS),
766 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
767 RK3399_CLKGATE_CON(17), 3, GFLAGS),
769 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
770 RK3399_CLKGATE_CON(17), 0, GFLAGS),
771 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
772 RK3399_CLKGATE_CON(17), 1, GFLAGS),
775 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
776 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
777 RK3399_CLKGATE_CON(4), 4, GFLAGS),
778 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
779 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
780 RK3399_CLKGATE_CON(4), 5, GFLAGS),
782 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
783 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
784 RK3399_CLKGATE_CON(4), 2, GFLAGS),
785 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
786 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
787 RK3399_CLKGATE_CON(4), 3, GFLAGS),
788 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
789 RK3399_CLKGATE_CON(17), 10, GFLAGS),
790 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
791 RK3399_CLKGATE_CON(17), 11, GFLAGS),
793 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
794 RK3399_CLKGATE_CON(17), 8, GFLAGS),
795 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
796 RK3399_CLKGATE_CON(17), 9, GFLAGS),
799 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
800 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
801 RK3399_CLKGATE_CON(4), 6, GFLAGS),
802 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
803 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
804 RK3399_CLKGATE_CON(4), 7, GFLAGS),
805 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
806 RK3399_CLKGATE_CON(16), 2, GFLAGS),
807 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
808 RK3399_CLKGATE_CON(16), 3, GFLAGS),
810 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
811 RK3399_CLKGATE_CON(16), 0, GFLAGS),
812 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
813 RK3399_CLKGATE_CON(16), 1, GFLAGS),
816 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
817 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
818 RK3399_CLKGATE_CON(4), 10, GFLAGS),
820 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
821 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
822 RK3399_CLKGATE_CON(4), 8, GFLAGS),
823 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
824 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
825 RK3399_CLKGATE_CON(4), 9, GFLAGS),
826 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
827 RK3399_CLKGATE_CON(16), 10, GFLAGS),
828 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
829 RK3399_CLKGATE_CON(16), 11, GFLAGS),
831 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
832 RK3399_CLKGATE_CON(16), 8, GFLAGS),
833 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
834 RK3399_CLKGATE_CON(16), 9, GFLAGS),
837 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
838 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
839 RK3399_CLKGATE_CON(3), 7, GFLAGS),
840 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
841 RK3399_CLKGATE_CON(19), 0, GFLAGS),
842 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
843 RK3399_CLKGATE_CON(19), 1, GFLAGS),
846 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
847 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
848 RK3399_CLKGATE_CON(13), 0, GFLAGS),
849 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
850 RK3399_CLKGATE_CON(30), 8, GFLAGS),
851 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
852 RK3399_CLKGATE_CON(30), 10, GFLAGS),
853 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
854 RK3399_CLKGATE_CON(30), 11, GFLAGS),
855 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
856 RK3399_CLKGATE_CON(13), 1, GFLAGS),
859 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
860 RK3399_CLKGATE_CON(5), 0, GFLAGS),
861 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
862 RK3399_CLKGATE_CON(5), 1, GFLAGS),
863 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
864 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
865 RK3399_CLKGATE_CON(5), 2, GFLAGS),
866 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
867 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
868 RK3399_CLKGATE_CON(5), 3, GFLAGS),
869 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
870 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
871 RK3399_CLKGATE_CON(5), 4, GFLAGS),
873 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
874 RK3399_CLKGATE_CON(20), 2, GFLAGS),
875 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
876 RK3399_CLKGATE_CON(20), 10, GFLAGS),
877 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
878 RK3399_CLKGATE_CON(20), 12, GFLAGS),
880 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
881 RK3399_CLKGATE_CON(20), 5, GFLAGS),
882 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
883 RK3399_CLKGATE_CON(20), 6, GFLAGS),
884 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
885 RK3399_CLKGATE_CON(20), 7, GFLAGS),
886 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
887 RK3399_CLKGATE_CON(20), 8, GFLAGS),
888 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
889 RK3399_CLKGATE_CON(20), 9, GFLAGS),
890 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
891 RK3399_CLKGATE_CON(20), 13, GFLAGS),
892 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
893 RK3399_CLKGATE_CON(20), 15, GFLAGS),
895 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
896 RK3399_CLKGATE_CON(20), 4, GFLAGS),
897 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
898 RK3399_CLKGATE_CON(20), 11, GFLAGS),
899 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
900 RK3399_CLKGATE_CON(20), 14, GFLAGS),
901 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
902 RK3399_CLKGATE_CON(31), 8, GFLAGS),
905 COMPOSITE(0, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
906 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
907 RK3399_CLKGATE_CON(12), 13, GFLAGS),
908 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
909 RK3399_CLKGATE_CON(33), 8, GFLAGS),
910 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
911 RK3399_CLKGATE_CON(33), 9, GFLAGS),
913 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
914 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
915 RK3399_CLKGATE_CON(6), 0, GFLAGS),
917 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
918 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
919 RK3399_CLKGATE_CON(6), 1, GFLAGS),
921 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
922 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
924 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
925 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
928 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
929 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
930 RK3399_CLKGATE_CON(6), 2, GFLAGS),
932 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
933 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
934 RK3399_CLKGATE_CON(12), 6, GFLAGS),
935 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
936 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
938 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
939 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
940 RK3399_CLKGATE_CON(6), 3, GFLAGS),
941 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
942 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
945 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
946 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
947 RK3399_CLKGATE_CON(6), 14, GFLAGS),
949 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
950 RK3399_CLKGATE_CON(6), 12, GFLAGS),
951 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
952 RK3399_CLKGATE_CON(6), 13, GFLAGS),
953 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
954 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
955 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
956 RK3399_CLKGATE_CON(32), 8, GFLAGS),
957 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
958 RK3399_CLKGATE_CON(32), 9, GFLAGS),
959 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
960 RK3399_CLKGATE_CON(32), 10, GFLAGS),
963 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
964 RK3399_CLKGATE_CON(7), 1, GFLAGS),
965 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
966 RK3399_CLKGATE_CON(7), 0, GFLAGS),
967 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
968 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
969 RK3399_CLKGATE_CON(7), 2, GFLAGS),
970 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
971 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
972 RK3399_CLKGATE_CON(7), 3, GFLAGS),
973 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
974 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
975 RK3399_CLKGATE_CON(7), 4, GFLAGS),
977 /* aclk_perilp0 gates */
978 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
979 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
980 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
981 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
982 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
983 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
984 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
985 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
986 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 8, GFLAGS),
987 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
988 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
989 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
991 /* hclk_perilp0 gates */
992 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
993 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
994 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
995 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
996 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
997 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
999 /* pclk_perilp0 gates */
1000 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 9, GFLAGS),
1003 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
1004 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
1005 RK3399_CLKGATE_CON(7), 7, GFLAGS),
1007 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
1008 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
1009 RK3399_CLKGATE_CON(7), 8, GFLAGS),
1012 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
1013 RK3399_CLKGATE_CON(7), 6, GFLAGS),
1014 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
1015 RK3399_CLKGATE_CON(7), 5, GFLAGS),
1016 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
1017 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
1018 RK3399_CLKGATE_CON(7), 9, GFLAGS),
1020 /* fclk_cm0s gates */
1021 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1022 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1023 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1024 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1025 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1028 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1029 RK3399_CLKGATE_CON(8), 1, GFLAGS),
1030 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1031 RK3399_CLKGATE_CON(8), 0, GFLAGS),
1032 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1033 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1034 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1035 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1036 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1038 /* hclk_perilp1 gates */
1039 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1040 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1041 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1042 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1043 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1044 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1045 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1046 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1047 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1049 /* pclk_perilp1 gates */
1050 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1051 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1052 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1053 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1054 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1055 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1056 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1057 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1058 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1059 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1060 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1061 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1062 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1063 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1064 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1065 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1066 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1067 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1068 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1069 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1070 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1073 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1074 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1075 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1078 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1079 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1080 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1083 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1084 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1085 COMPOSITE(0, "clk_testout1", mux_clk_testout1_p, 0,
1086 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1087 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1089 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1090 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1091 COMPOSITE(0, "clk_testout2", mux_clk_testout2_p, 0,
1092 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1093 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1096 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1097 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1098 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1099 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", CLK_IGNORE_UNUSED,
1100 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1101 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1103 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1104 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1106 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1107 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1108 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1109 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1110 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1111 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1114 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1115 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1116 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1117 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1118 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1119 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1120 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1121 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1122 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1124 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1125 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1126 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1127 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1129 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1130 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1131 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1132 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1134 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1135 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1136 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1137 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1138 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1139 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1140 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1141 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1142 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1143 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1146 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1147 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1148 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1150 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1151 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
1152 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1153 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1154 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1155 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1156 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1159 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1160 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1162 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1163 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1164 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1167 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1168 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1169 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1170 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1171 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1172 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1174 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1175 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1176 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1177 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1179 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1180 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1181 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1182 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1184 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, CLK_SET_RATE_PARENT,
1185 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1186 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1188 /* The VOP0 is main screen, it is able to re-set parent rate. */
1189 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
1190 RK3399_CLKSEL_CON(106), 0,
1191 &rk3399_dclk_vop0_fracmux),
1193 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1194 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1195 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1198 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
1199 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1200 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1201 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1202 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1203 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1205 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1206 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1207 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1208 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1210 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1211 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1212 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1213 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1215 /* The VOP1 is sub screen, it is note able to re-set parent rate. */
1216 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1217 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1218 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1220 COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop1_frac", "dclk_vop1_div", CLK_SET_RATE_PARENT,
1221 RK3399_CLKSEL_CON(107), 0,
1222 &rk3399_dclk_vop1_fracmux),
1224 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_24m_p, 0,
1225 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1226 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1229 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1230 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1231 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1232 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1233 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1234 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1236 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1237 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1238 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1239 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1240 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1241 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1243 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1244 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1245 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1246 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1248 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1249 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1250 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1252 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1253 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1254 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1255 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1256 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1257 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1259 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1260 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1262 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1263 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1264 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1265 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1267 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1268 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1269 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1272 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1273 * so we ignore the mux and make clocks nodes as following,
1275 * pclkin_cifinv --|-------\
1276 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1277 * pclkin_cif --|-------/
1279 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1280 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1283 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1284 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1285 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1287 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1288 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1291 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1292 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1293 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1295 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1296 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1297 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1298 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1299 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1300 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1303 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1304 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1305 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1307 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1308 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1309 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1310 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1311 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1313 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1314 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1315 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1316 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1317 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1318 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1319 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1320 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1321 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1323 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1324 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1326 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1327 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1328 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1329 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1332 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1333 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1334 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", CLK_SET_RATE_PARENT,
1335 RK3399_CLKSEL_CON(105), 0,
1336 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1338 DIV(0, "clk_test_24m", "xin24m", 0,
1339 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1342 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1343 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1344 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1346 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1347 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1348 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1350 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1351 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1352 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1354 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1355 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1356 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1358 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1359 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1360 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1363 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1364 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1365 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1367 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1368 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1369 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1371 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1372 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1373 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1375 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1376 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1377 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1379 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1380 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1381 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1383 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1384 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1385 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1388 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1389 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1390 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1391 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1392 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1393 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1394 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1395 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1396 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1397 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1398 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1399 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1402 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1403 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1404 RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
1405 RK3368_CLKGATE_CON(13), 11, GFLAGS),
1408 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1410 * PMU CRU Clock-Architecture
1413 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1414 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1416 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1417 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1419 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1420 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1421 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1423 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1424 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1425 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1427 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
1428 RK3399_PMU_CLKSEL_CON(7), 0,
1429 &rk3399_pmuclk_wifi_fracmux),
1431 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1432 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1434 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1435 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1436 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1438 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1439 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1440 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1442 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1443 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1444 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1446 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1447 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1448 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1449 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1451 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1452 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1453 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1455 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
1456 RK3399_PMU_CLKSEL_CON(6), 0,
1457 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1458 &rk3399_uart4_pmu_fracmux),
1460 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1461 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1463 /* pmu clock gates */
1464 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1465 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1467 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1469 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1470 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1471 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1472 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1473 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1474 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1475 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1476 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1477 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1478 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1479 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1480 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1481 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1482 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1483 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1484 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1486 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1487 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1488 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1489 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1490 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1493 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1495 * We need to declare that we enable all NOCs which are critical clocks
1496 * always and clearly and explicitly show that we have enabled them at
1502 "pclk_center_main_noc",
1514 "aclk_center_main_noc",
1515 "aclk_center_peri_noc",
1523 "hclk_m0_perilp_noc",
1526 "hclk_sdioaudio_noc",
1543 /* other critical clocks */
1553 "aclk_dmac1_perilp",
1554 "gpll_aclk_perilp0_src",
1555 "gpll_aclk_perihp_src",
1559 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1561 * We need to declare that we enable all NOCs which are critical clocks
1562 * always and clearly and explicitly show that we have enabled them at
1568 /* other critical clocks */
1571 "fclk_cm0s_src_pmu",
1572 "clk_timer_src_pmu",
1576 static void __init rk3399_clk_init(struct device_node *np)
1578 struct rockchip_clk_provider *ctx;
1579 void __iomem *reg_base;
1582 reg_base = of_iomap(np, 0);
1584 pr_err("%s: could not map cru region\n", __func__);
1588 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1590 pr_err("%s: rockchip clk init failed\n", __func__);
1594 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1595 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1597 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1598 __func__, PTR_ERR(clk));
1600 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1602 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1603 ARRAY_SIZE(rk3399_pll_clks), -1);
1605 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1606 ARRAY_SIZE(rk3399_clk_branches));
1608 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1609 ARRAY_SIZE(rk3399_cru_critical_clocks));
1611 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1612 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1613 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1614 ARRAY_SIZE(rk3399_cpuclkl_rates));
1616 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1617 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1618 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1619 ARRAY_SIZE(rk3399_cpuclkb_rates));
1621 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1622 ROCKCHIP_SOFTRST_HIWORD_MASK);
1624 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1626 rockchip_clk_of_add_provider(np, ctx);
1628 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1630 static void __init rk3399_pmu_clk_init(struct device_node *np)
1632 struct rockchip_clk_provider *ctx;
1633 void __iomem *reg_base;
1635 reg_base = of_iomap(np, 0);
1637 pr_err("%s: could not map cru pmu region\n", __func__);
1641 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1643 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1647 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1648 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1650 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1651 ARRAY_SIZE(rk3399_clk_pmu_branches));
1653 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1654 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1656 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1657 ROCKCHIP_SOFTRST_HIWORD_MASK);
1659 rockchip_clk_of_add_provider(np, ctx);
1661 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
projects / firefly-linux-kernel-4.4.55.git / blob