2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xiao Feng <xf@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk-provider.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <dt-bindings/clock/rk3366-cru.h>
23 #define RK3366_GRF_SOC_STATUS0 0x480
26 apll, dpll, cpll, gpll, npll, mpll, wpll, bpll,
29 static struct rockchip_pll_rate_table rk3366_pll_rates[] = {
30 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
31 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
32 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
34 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
35 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
36 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
37 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
38 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
39 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
40 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
41 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
42 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
52 RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
53 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
54 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
55 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
56 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
57 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
58 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
59 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
60 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
61 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
62 RK3036_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0),
63 RK3036_PLL_RATE( 750000000, 2, 125, 2, 1, 1, 0),
64 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
65 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
66 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
67 RK3036_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0),
68 RK3036_PLL_RATE( 576000000, 1, 96, 4, 1, 1, 0),
69 RK3036_PLL_RATE( 520000000, 1, 65, 3, 1, 1, 0),
70 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
71 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
72 RK3036_PLL_RATE( 480000000, 1, 80, 4, 1, 1, 0),
73 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
74 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
75 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
76 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
81 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
82 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
83 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
84 PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
85 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
86 PNAME(mux_pll_src_npll_cpll_gpll_gpll_p) = { "npll", "cpll", "gpll", "gpll" };
87 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
88 PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
90 PNAME(mux_pll_src_cpll_gpll_usb_npll_p) = { "cpll", "gpll", "usbphy_480m",
92 PNAME(mux_pll_src_cpll_gpll_npll_npll_p) = { "cpll", "gpll", "npll", "npll" };
93 PNAME(mux_pll_src_cpll_gpll_npll_usb_p) = { "cpll", "gpll", "npll",
95 PNAME(mux_pll_src_cpll_gpll_npll_mpll_p) = { "cpll", "gpll", "npll", "mpll_src" };
96 PNAME(mux_vop_full_pwm_p) = { "xin24m", "cpll", "gpll", "npll" };
97 PNAME(mux_clk_32k_p) = { "xin32k", "clk_32k_inter" };
98 PNAME(mux_i2s_8ch_pre_p) = { "i2s_8ch_src", "i2s_8ch_frac",
99 "ext_i2s", "xin12m" };
100 PNAME(mux_i2s_8ch_clkout_p) = { "i2s_8ch_pre", "xin12m" };
101 PNAME(mux_i2s_2ch_p) = { "i2s_2ch_src", "i2s_2ch_frac",
103 PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac",
104 "ext_i2s", "xin12m" };
105 PNAME(mux_vip_out_p) = { "vip_src", "xin24m" };
106 PNAME(mux_usb3_suspend_p) = { "clk_32k", "xin24m" };
107 PNAME(mux_usbphy480m_p) = { "xin24m", "usbotg_out" };
108 PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m", "xin24m" };
109 PNAME(mux_uart2_p) = { "uart2_src", "xin24m" };
110 PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m", "xin24m" };
111 PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" };
112 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "usbphy_480m", "xin24m" };
113 PNAME(mux_bt_p) = { "bpll", "btclk520_pll" };
114 PNAME(mux_wifi_pll_p) = { "wpll_wiff", "usbphy_480m_wifi" };
116 static struct rockchip_pll_clock rk3366_pll_clks[] __initdata = {
117 [apll] = PLL(pll_rk3366, PLL_APLL, "apll", mux_pll_p, 0, RK3368_PLL_CON(0),
118 RK3368_PLL_CON(3), 8, 0, 0, rk3366_pll_rates),
119 [dpll] = PLL(pll_rk3366, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
120 RK3368_PLL_CON(11), 8, 1, 0, NULL),
121 [cpll] = PLL(pll_rk3366, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
122 RK3368_PLL_CON(15), 8, 2, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
123 [gpll] = PLL(pll_rk3366, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
124 RK3368_PLL_CON(19), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
125 [npll] = PLL(pll_rk3366, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
126 RK3368_PLL_CON(23), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
127 [mpll] = PLL(pll_rk3366, PLL_MPLL, "mpll", mux_pll_p, 0, RK3368_PLL_CON(24),
128 RK3368_PLL_CON(27), 8, 5, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
129 [wpll] = PLL(pll_rk3366, PLL_WPLL, "wpll", mux_pll_p, 0, RK3368_PLL_CON(28),
130 RK3368_PLL_CON(31), 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
131 [bpll] = PLL(pll_rk3366, PLL_BPLL, "bpll", mux_pll_p, 0, RK3368_PLL_CON(32),
132 RK3368_PLL_CON(35), 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3366_pll_rates),
135 static struct clk_div_table div_ddrphy_t[] = {
136 { .val = 0, .div = 1 },
137 { .val = 1, .div = 2 },
138 { .val = 3, .div = 4 },
142 #define MFLAGS CLK_MUX_HIWORD_MASK
143 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
144 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
145 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
147 static const struct rockchip_cpuclk_reg_data rk3366_cpuclk_data = {
148 .core_reg = RK3368_CLKSEL_CON(0),
150 .div_core_mask = 0x1f,
154 #define RK3366_DIV_ACLKM_MASK 0x1f
155 #define RK3366_DIV_ACLKM_SHIFT 8
156 #define RK3366_DIV_ATCLK_MASK 0x1f
157 #define RK3366_DIV_ATCLK_SHIFT 0
158 #define RK3366_DIV_PCLK_DBG_MASK 0x1f
159 #define RK3366_DIV_PCLK_DBG_SHIFT 8
161 #define RK3366_CLKSEL0(_offs, _aclkm) \
163 .reg = RK3368_CLKSEL_CON(0 + _offs), \
164 .val = HIWORD_UPDATE(_aclkm, RK3366_DIV_ACLKM_MASK, \
165 RK3366_DIV_ACLKM_SHIFT), \
167 #define RK3366_CLKSEL1(_offs, _atclk, _pdbg) \
169 .reg = RK3368_CLKSEL_CON(1 + _offs), \
170 .val = HIWORD_UPDATE(_atclk, RK3366_DIV_ATCLK_MASK, \
171 RK3366_DIV_ATCLK_SHIFT) | \
172 HIWORD_UPDATE(_pdbg, RK3366_DIV_PCLK_DBG_MASK, \
173 RK3366_DIV_PCLK_DBG_SHIFT), \
176 /* cluster_b: aclkm in clksel0, rest in clksel1 */
177 #define RK3366_CPUCLK_RATE(_prate, _aclkm, _atclk, _pdbg) \
181 RK3366_CLKSEL0(0, _aclkm), \
182 RK3366_CLKSEL1(0, _atclk, _pdbg), \
186 static struct rockchip_cpuclk_rate_table rk3366_cpuclk_rates[] __initdata = {
187 RK3366_CPUCLK_RATE(1512000000, 1, 5, 5),
188 RK3366_CPUCLK_RATE(1488000000, 1, 4, 4),
189 RK3366_CPUCLK_RATE(1416000000, 1, 4, 4),
190 RK3366_CPUCLK_RATE(1200000000, 1, 3, 3),
191 RK3366_CPUCLK_RATE(1008000000, 1, 3, 3),
192 RK3366_CPUCLK_RATE( 816000000, 1, 2, 2),
193 RK3366_CPUCLK_RATE( 696000000, 1, 2, 2),
194 RK3366_CPUCLK_RATE( 600000000, 1, 1, 1),
195 RK3366_CPUCLK_RATE( 408000000, 1, 1, 1),
196 RK3366_CPUCLK_RATE( 312000000, 1, 1, 1),
199 static struct rockchip_clk_branch rk3366_i2s_8ch_fracmux __initdata =
200 MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
201 RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
203 static struct rockchip_clk_branch rk3366_spdif_8ch_fracmux __initdata =
204 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
205 RK3368_CLKSEL_CON(31), 8, 2, MFLAGS);
207 static struct rockchip_clk_branch rk3366_i2s_2ch_fracmux __initdata =
208 MUX(0, "i2s_2ch_mux", mux_i2s_2ch_p, CLK_SET_RATE_PARENT,
209 RK3368_CLKSEL_CON(53), 8, 2, MFLAGS);
211 static struct rockchip_clk_branch rk3366_uart0_fracmux __initdata =
212 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
213 RK3368_CLKSEL_CON(33), 8, 2, MFLAGS);
215 static struct rockchip_clk_branch rk3366_uart3_fracmux __initdata =
216 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
217 RK3368_CLKSEL_CON(39), 8, 2, MFLAGS);
219 static struct rockchip_clk_branch rk3366_clk_branches[] __initdata = {
221 * Clock-Architecture Diagram 1
224 GATE(0, "mpll_src", "mpll", CLK_IGNORE_UNUSED,
225 RK3368_CLKGATE_CON(2), 11, GFLAGS),
228 * Clock-Architecture Diagram 2
231 MUX(SCLK_USBPHY480M, "usbphy_480m", mux_usbphy480m_p, 0,
232 RK3368_CLKSEL_CON(13), 6, 1, MFLAGS),
234 DIV(0, "clk_32k_inter", "xin24m", 0,
235 RK3368_CLKSEL_CON(7), 0, 10, DFLAGS),
236 MUX(0, "clk_32k", mux_clk_32k_p, CLK_SET_RATE_PARENT,
237 RK3368_CLKSEL_CON(7), 15, 1, MFLAGS),
239 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
240 RK3368_CLKGATE_CON(0), 0, GFLAGS),
241 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
242 RK3368_CLKGATE_CON(0), 1, GFLAGS),
243 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
244 RK3368_CLKGATE_CON(0), 2, GFLAGS),
246 DIV(0, "aclkm_core", "armclk", 0,
247 RK3368_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
248 DIV(0, "atclk_core", "armclk", 0,
249 RK3368_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
250 DIV(0, "pclk_dbg", "armclk", 0,
251 RK3368_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY),
253 COMPOSITE_NOMUX(0, "sclk_cs_pre", "armclk", CLK_IGNORE_UNUSED,
254 RK3368_CLKSEL_CON(4), 0, 5, DFLAGS,
255 RK3368_CLKGATE_CON(0), 11, GFLAGS),
256 COMPOSITE_NOMUX(0, "clkin_trace", "armclk", CLK_IGNORE_UNUSED,
257 RK3368_CLKSEL_CON(14), 8, 5, DFLAGS,
258 RK3368_CLKGATE_CON(0), 13, GFLAGS),
260 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0,
261 RK3368_CLKGATE_CON(7), 10, GFLAGS),
263 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
264 RK3368_CLKGATE_CON(1), 8, GFLAGS),
265 GATE(0, "gpll_ddr", "gpll", 0,
266 RK3368_CLKGATE_CON(1), 9, GFLAGS),
267 GATE(0, "apll_ddr", "apll", 0,
268 RK3368_CLKGATE_CON(1), 7, GFLAGS),
269 COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
270 RK3368_CLKSEL_CON(13), 4, 2, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
272 GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
273 RK3368_CLKGATE_CON(1), 10, GFLAGS),
274 GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
275 RK3368_CLKGATE_CON(1), 11, GFLAGS),
276 COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
277 RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
279 GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
280 RK3368_CLKGATE_CON(1), 0, GFLAGS),
281 COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
282 RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
283 RK3368_CLKGATE_CON(1), 2, GFLAGS),
284 COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
285 RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
286 RK3368_CLKGATE_CON(1), 1, GFLAGS),
288 COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_cpll_gpll_p, 0,
289 RK3368_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 5, DFLAGS,
290 RK3368_CLKGATE_CON(7), 2, GFLAGS),
292 COMPOSITE(0, "fclk_mcu_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
293 RK3368_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 5, DFLAGS,
294 RK3368_CLKGATE_CON(1), 3, GFLAGS),
296 COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
297 RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
298 RK3368_CLKGATE_CON(6), 1, GFLAGS),
299 COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
300 RK3368_CLKSEL_CON(28), 0,
301 RK3368_CLKGATE_CON(6), 2, GFLAGS,
302 &rk3366_i2s_8ch_fracmux),
303 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
304 RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
305 RK3368_CLKGATE_CON(6), 0, GFLAGS),
306 GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
307 RK3368_CLKGATE_CON(6), 3, GFLAGS),
309 COMPOSITE(0, "spdif_8ch_src", mux_pll_src_cpll_gpll_p, 0,
310 RK3368_CLKSEL_CON(31), 12, 1, MFLAGS, 0, 7, DFLAGS,
311 RK3368_CLKGATE_CON(6), 4, GFLAGS),
312 COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
313 RK3368_CLKSEL_CON(32), 0,
314 RK3368_CLKGATE_CON(6), 5, GFLAGS,
315 &rk3366_spdif_8ch_fracmux),
316 GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
317 RK3368_CLKGATE_CON(6), 6, GFLAGS),
319 COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
320 RK3368_CLKSEL_CON(53), 12, 1, MFLAGS, 0, 7, DFLAGS,
321 RK3368_CLKGATE_CON(5), 13, GFLAGS),
322 COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
323 RK3368_CLKSEL_CON(54), 0,
324 RK3368_CLKGATE_CON(5), 14, GFLAGS,
325 &rk3366_i2s_2ch_fracmux),
326 GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_mux", CLK_SET_RATE_PARENT,
327 RK3368_CLKGATE_CON(5), 15, GFLAGS),
330 * Clock-Architecture Diagram 3
333 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
334 RK3368_CLKSEL_CON(35), 12, 1, MFLAGS),
335 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
336 RK3368_CLKSEL_CON(37), 0, 7, DFLAGS,
337 RK3368_CLKGATE_CON(2), 4, GFLAGS),
338 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
339 RK3368_CLKSEL_CON(37), 8, 1, MFLAGS),
341 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
342 RK3368_CLKSEL_CON(15), 6, 2, MFLAGS, 0, 5, DFLAGS,
343 RK3368_CLKGATE_CON(4), 6, GFLAGS),
344 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_npll_usb_p, 0,
345 RK3368_CLKSEL_CON(15), 14, 2, MFLAGS, 8, 5, DFLAGS,
346 RK3368_CLKGATE_CON(4), 7, GFLAGS),
349 * We introduce a virtual node of hclk_vodec_pre_v to split one clock
350 * struct with a gate and a fix divider into two node in software.
352 GATE(0, "hclk_video_pre_v", "aclk_vdpu", 0,
353 RK3368_CLKGATE_CON(4), 8, GFLAGS),
355 COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_cpll_gpll_npll_usb_p, 0,
356 RK3368_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 5, DFLAGS,
357 RK3368_CLKGATE_CON(5), 8, GFLAGS),
360 * We introduce a virtual node of hclk_rkvdec_pre_v to split one clock
361 * struct with a gate and a fix divider into two node in software.
363 GATE(0, "hclk_rkvdec_pre_v", "aclk_rkvdec_pre", 0,
364 RK3368_CLKGATE_CON(5), 9, GFLAGS),
366 COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
367 RK3368_CLKSEL_CON(17), 6, 2, MFLAGS, 0, 5, DFLAGS,
368 RK3368_CLKGATE_CON(5), 1, GFLAGS),
369 COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core_src", mux_pll_src_cpll_gpll_npll_usb_p, 0,
370 RK3368_CLKSEL_CON(17), 14, 2, MFLAGS, 8, 5, DFLAGS,
371 RK3368_CLKGATE_CON(5), 2, GFLAGS),
373 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb_p, CLK_IGNORE_UNUSED,
374 RK3368_CLKSEL_CON(19), 6, 2, MFLAGS, 0, 5, DFLAGS,
375 RK3368_CLKGATE_CON(4), 0, GFLAGS),
376 DIV(0, "hclk_vio", "aclk_vio0", 0,
377 RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
379 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
380 RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
381 RK3368_CLKGATE_CON(4), 3, GFLAGS),
382 COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
383 RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
384 RK3368_CLKGATE_CON(4), 4, GFLAGS),
386 COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_cpll_gpll_usb_p, 0,
387 RK3368_CLKSEL_CON(16), 6, 2, MFLAGS, 0, 5, DFLAGS,
388 RK3368_CLKGATE_CON(4), 15, GFLAGS),
390 COMPOSITE(DCLK_VOP_FULL, "dclk_vop_full", mux_pll_src_cpll_gpll_npll_mpll_p, 0,
391 RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
392 RK3368_CLKGATE_CON(4), 1, GFLAGS),
394 COMPOSITE(SCLK_VOP_FULL_PWM, "sclk_vop_full_pwm", mux_vop_full_pwm_p, 0,
395 RK3368_CLKSEL_CON(23), 6, 2, MFLAGS, 0, 6, DFLAGS,
396 RK3368_CLKGATE_CON(4), 2, GFLAGS),
398 COMPOSITE(DCLK_VOP_LITE, "dclk_vop_lite", mux_pll_src_cpll_gpll_npll_mpll_p, 0,
399 RK3368_CLKSEL_CON(24), 8, 2, MFLAGS, 0, 8, DFLAGS,
400 RK3368_CLKGATE_CON(5), 6, GFLAGS),
402 COMPOSITE_NOMUX(DCLK_HDMIPHY, "dclk_hdmiphy", "mpll_src", 0,
403 RK3368_CLKSEL_CON(16), 8, 8, DFLAGS,
404 RK3368_CLKGATE_CON(5), 7, GFLAGS),
406 COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
407 RK3368_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 6, DFLAGS,
408 RK3368_CLKGATE_CON(4), 9, GFLAGS),
410 GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
411 RK3368_CLKGATE_CON(4), 13, GFLAGS),
412 GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "clk_32k", 0,
413 RK3368_CLKGATE_CON(4), 12, GFLAGS),
415 MUX(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
416 RK3368_CLKSEL_CON(21), 15, 1, MFLAGS),
417 COMPOSITE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
418 RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS,
419 RK3368_CLKGATE_CON(4), 5, GFLAGS),
421 GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
424 * Clock-Architecture Diagram 4
427 COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_cpll_gpll_npll_npll_p, 0,
428 RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
429 RK3368_CLKGATE_CON(5), 5, GFLAGS),
431 DIV(0, "pclk_pd_alive", "gpll", 0,
432 RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
434 /* sclk_timer has a gate in the sgrf */
436 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
437 RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
438 RK3368_CLKGATE_CON(7), 9, GFLAGS),
439 GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
440 RK3368_CLKGATE_CON(7), 3, GFLAGS),
442 COMPOSITE(0, "sclk_gpu_core_src", mux_pll_src_cpll_gpll_usb_npll_p, 0,
443 RK3368_CLKSEL_CON(14), 6, 2, MFLAGS, 0, 5, DFLAGS,
444 RK3368_CLKGATE_CON(4), 11, GFLAGS),
445 GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
446 RK3368_CLKGATE_CON(7), 11, GFLAGS),
448 COMPOSITE(0, "aclk_peri0_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
449 RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
450 RK3368_CLKGATE_CON(3), 0, GFLAGS),
451 COMPOSITE_NOMUX(PCLK_PERI0, "pclk_peri0", "aclk_peri0_src", 0,
452 RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
453 RK3368_CLKGATE_CON(3), 3, GFLAGS),
454 COMPOSITE_NOMUX(HCLK_PERI0, "hclk_peri0", "aclk_peri0_src", CLK_IGNORE_UNUSED,
455 RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
456 RK3368_CLKGATE_CON(3), 2, GFLAGS),
457 GATE(ACLK_PERI0, "aclk_peri0", "aclk_peri0_src", CLK_IGNORE_UNUSED,
458 RK3368_CLKGATE_CON(3), 1, GFLAGS),
460 COMPOSITE(0, "aclk_peri1_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
461 RK3368_CLKSEL_CON(11), 7, 1, MFLAGS, 0, 5, DFLAGS,
462 RK3368_CLKGATE_CON(3), 10, GFLAGS),
463 COMPOSITE_NOMUX(PCLK_PERI1, "pclk_peri1", "aclk_peri1_src", 0,
464 RK3368_CLKSEL_CON(11), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
465 RK3368_CLKGATE_CON(3), 13, GFLAGS),
466 COMPOSITE_NOMUX(HCLK_PERI1, "hclk_peri1", "aclk_peri1_src", CLK_IGNORE_UNUSED,
467 RK3368_CLKSEL_CON(11), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
468 RK3368_CLKGATE_CON(3), 12, GFLAGS),
469 GATE(ACLK_PERI1, "aclk_peri1", "aclk_peri1_src", CLK_IGNORE_UNUSED,
470 RK3368_CLKGATE_CON(3), 11, GFLAGS),
472 GATE(SCLK_USB3_REF, "sclk_usb3_ref", "xin24m", 0,
473 RK3368_CLKGATE_CON(3), 15, GFLAGS),
475 COMPOSITE(SCLK_USB3_SUSPEND, "sclk_usb3_suspend", mux_usb3_suspend_p, 0,
476 RK3368_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 8, DFLAGS,
477 RK3368_CLKGATE_CON(3), 14, GFLAGS),
479 /* ref_alt_clk_p has a mux in the grf */
482 * Clock-Architecture Diagram 5
485 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
486 RK3368_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
487 RK3368_CLKGATE_CON(3), 7, GFLAGS),
488 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
489 RK3368_CLKSEL_CON(45), 15, 1, MFLAGS, 8, 7, DFLAGS,
490 RK3368_CLKGATE_CON(3), 8, GFLAGS),
491 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
492 RK3368_CLKSEL_CON(46), 15, 1, MFLAGS, 8, 7, DFLAGS,
493 RK3368_CLKGATE_CON(3), 9, GFLAGS),
495 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
496 RK3368_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 7, DFLAGS,
497 RK3368_CLKGATE_CON(7), 12, GFLAGS),
498 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
499 RK3368_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 7, DFLAGS,
500 RK3368_CLKGATE_CON(7), 13, GFLAGS),
501 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
502 RK3368_CLKSEL_CON(51), 8, 2, MFLAGS, 0, 7, DFLAGS,
503 RK3368_CLKGATE_CON(7), 15, GFLAGS),
505 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3368_SDMMC_CON0, 1),
506 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3368_SDMMC_CON1, 0),
508 MMC(SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3368_SDIO0_CON0, 1),
509 MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3368_SDIO0_CON1, 0),
511 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3368_EMMC_CON0, 1),
512 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3368_EMMC_CON1, 0),
514 GATE(SCLK_OTG_PHY0, "sclk_otg_phy0", "xin24m", CLK_IGNORE_UNUSED,
515 RK3368_CLKGATE_CON(8), 1, GFLAGS),
517 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "clk_32k", CLK_IGNORE_UNUSED,
518 RK3368_CLKGATE_CON(8), 4, GFLAGS),
520 GATE(SCLK_TSADC, "sclk_tsadc", "clk_32k", 0,
521 RK3368_CLKGATE_CON(3), 5, GFLAGS),
523 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
524 RK3368_CLKSEL_CON(25), 8, 8, DFLAGS,
525 RK3368_CLKGATE_CON(3), 6, GFLAGS),
527 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
528 RK3368_CLKSEL_CON(47), 7, 1, MFLAGS, 0, 5, DFLAGS,
529 RK3368_CLKGATE_CON(7), 8, GFLAGS),
531 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_cpll_gpll_p, 0,
532 RK3368_CLKSEL_CON(52), 7, 1, MFLAGS, 0, 5, DFLAGS,
533 RK3368_CLKGATE_CON(6), 7, GFLAGS),
535 COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gpll_usb_usb_p, 0,
536 RK3368_CLKSEL_CON(33), 12, 2, MFLAGS, 0, 7, DFLAGS,
537 RK3368_CLKGATE_CON(2), 0, GFLAGS),
538 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
539 RK3368_CLKSEL_CON(34), 0,
540 RK3368_CLKGATE_CON(2), 1, GFLAGS,
541 &rk3366_uart0_fracmux),
543 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
544 RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
545 RK3368_CLKGATE_CON(2), 6, GFLAGS),
546 COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
547 RK3368_CLKSEL_CON(40), 0,
548 RK3368_CLKGATE_CON(2), 7, GFLAGS,
549 &rk3366_uart3_fracmux),
552 * Clock-Architecture Diagram 6
555 COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_gpll_p, 0,
556 RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
557 RK3368_CLKGATE_CON(3), 4, GFLAGS),
558 MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
559 RK3368_CLKSEL_CON(43), 8, 1, MFLAGS),
560 GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
561 RK3368_CLKGATE_CON(7), 7, GFLAGS),
562 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
563 RK3368_CLKGATE_CON(7), 6, GFLAGS),
564 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
565 RK3368_CLKGATE_CON(7), 4, GFLAGS),
566 GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
567 RK3368_CLKGATE_CON(7), 5, GFLAGS),
569 GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
570 RK3368_CLKGATE_CON(7), 0, GFLAGS),
573 * Clock-Architecture Diagram 7
576 COMPOSITE_NODIV(0, "btclk520_pll", mux_pll_src_cpll_gpll_npll_npll_p, 0,
577 RK3368_CLKSEL_CON(5), 13, 2, MFLAGS,
578 RK3368_CLKGATE_CON(2), 10, GFLAGS),
579 MUX(0, "clk_bt_pll", mux_bt_p, 0,
580 RK3368_CLKSEL_CON(5), 15, 1, MFLAGS),
581 COMPOSITE_NOMUX(SCLK_BT_52, "sclk_bt_520", "clk_bt_pll", 0,
582 RK3368_CLKSEL_CON(5), 0, 5, DFLAGS,
583 RK3368_CLKGATE_CON(8), 13, GFLAGS),
584 DIV(0, "pclk_btbb", "sclk_bt_520", 0,
585 RK3368_CLKSEL_CON(5), 10, 3, DFLAGS),
586 COMPOSITE_NOMUX(SCLK_BT_M0, "sclk_bt_m0", "clk_bt_pll", 0,
587 RK3368_CLKSEL_CON(5), 5, 5, DFLAGS,
588 RK3368_CLKGATE_CON(8), 14, GFLAGS),
590 GATE(SCLK_WIFI_WPLL, "wpll_wiff", "wpll", 0,
591 RK3368_CLKGATE_CON(8), 11, GFLAGS),
592 GATE(SCLK_WIFI_USBPHY480M, "usbphy_480m_wifi", "usbphy_480m", 0,
593 RK3368_CLKGATE_CON(8), 11, GFLAGS),
594 COMPOSITE(SCLK_WIFIDSP, "sclk_wifidsp", mux_wifi_pll_p, 0,
595 RK3368_CLKSEL_CON(13), 15, 1, MFLAGS, 10, 5, DFLAGS,
596 RK3368_CLKGATE_CON(8), 12, GFLAGS),
597 DIV(0, "hclk_wifi", "sclk_wifidsp", CLK_SET_RATE_PARENT,
598 RK3368_CLKSEL_CON(13), 7, 3, DFLAGS),
601 * Clock-Architecture Diagram 8
604 /* pclk_pd_pmu gates*/
605 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
606 GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 1, GFLAGS),
607 GATE(0, "pclk_pmu_noc", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 2, GFLAGS),
608 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 3, GFLAGS),
609 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 4, GFLAGS),
610 GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
611 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 6, GFLAGS),
613 /* fclk_mcu_src gates */
614 GATE(0, "fclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 7, GFLAGS),
615 GATE(0, "hclk_mcu", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 8, GFLAGS),
616 GATE(0, "hclk_mcu_noc", "fclk_mcu_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 9, GFLAGS),
618 /* pclk_pd_alive gates */
619 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
620 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
621 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
622 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 4, GFLAGS),
623 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 5, GFLAGS),
624 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
625 GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
626 GATE(PCLK_DPHYTX, "pclk_dphytx", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 10, GFLAGS),
627 GATE(PCLK_DPHYRX, "pclk_dphyrx", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 11, GFLAGS),
628 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
631 GATE(PCLK_DMFIMON, "pclk_dmfimon", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 0, GFLAGS),
632 GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
633 GATE(PCLK_DFC, "pclk_dfc", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
634 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
635 GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
636 GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
637 GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
638 GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
639 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
640 GATE(PCLK_RKPWM, "pclk_rk_pwm", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
641 GATE(0, "pclk_ddrnoc", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 10, GFLAGS),
642 GATE(0, "pclk_ddr_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 11, GFLAGS),
645 GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 7, GFLAGS),
646 GATE(HCLK_I2S_2CH, "hclk_i2s_2ch", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 8, GFLAGS),
647 GATE(HCLK_ROM, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 9, GFLAGS),
648 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_bus", 0, RK3368_CLKGATE_CON(12), 10, GFLAGS),
649 GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
650 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 4, GFLAGS),
653 GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
654 GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
655 GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
656 GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
657 GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
658 GATE(ACLK_DFC, "aclk_dfc", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 15, GFLAGS),
659 GATE(0, "aclk_gic400", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 9, GFLAGS),
661 /* clk_ddrphy gates */
662 GATE(0, "clk_ddrupctl", "ddrphy_div4", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(13), 2, GFLAGS),
664 /* clk_cs_pre gates */
665 GATE(0, "sclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 0, GFLAGS),
666 GATE(0, "hclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 1, GFLAGS),
667 GATE(0, "pclk_cs_dbg", "sclk_cs_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 2, GFLAGS),
670 GATE(0, "clk_core_cxcs", "armclk", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 3, GFLAGS),
672 /* aclkm_core gates */
673 GATE(0, "aclk_core_noc", "aclkm_core", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(9), 4, GFLAGS),
676 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu_core_src", 0, RK3368_CLKGATE_CON(18), 0, GFLAGS),
677 GATE(ACLK_GPU_NOC, "aclk_gpu_noc", "sclk_gpu_core_src", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(18), 1, GFLAGS),
679 /* aclk_peri0 gates */
680 GATE(0, "aclk_peri0_axi_matrix", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 0, GFLAGS),
681 GATE(ACLK_USB3, "aclk_usb3", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
682 GATE(0, "aclk_peri0_noc", "aclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
683 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri0", 0, RK3368_CLKGATE_CON(20), 13, GFLAGS),
685 /* hclk_peri0 gates */
686 GATE(HCLK_OTG, "hclk_otg", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
687 GATE(HCLK_HOST, "hclk_host", "hclk_peri0", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
688 GATE(0, "hclk_host_arbiter", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
689 GATE(0, "hclk_peri0_ahb_arbiter", "hclk_peri0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
690 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 0, GFLAGS),
691 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
692 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri0", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
694 /* pclk_peri0 gates */
695 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri0", 0, RK3368_CLKGATE_CON(20), 14, GFLAGS),
697 /* aclk_peri1 gates */
698 GATE(0, "aclk_peri1_axi_matrix", "aclk_peri1", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(19), 1, GFLAGS),
699 GATE(ACLK_DMAC_PERI, "aclk_dmac_peri", "aclk_peri1", 0, RK3368_CLKGATE_CON(19), 3, GFLAGS),
701 /* hclk_peri1 gates */
702 GATE(0, "hclk_peri1_ahb_arbiter", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 8, GFLAGS),
703 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 11, GFLAGS),
704 GATE(HCLK_SFC, "hclk_sfc", "hclk_peri1", 0, RK3368_CLKGATE_CON(20), 15, GFLAGS),
706 /* pclk_peri1 gates */
707 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 4, GFLAGS),
708 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
709 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 7, GFLAGS),
710 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
711 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 11, GFLAGS),
712 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 12, GFLAGS),
713 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 13, GFLAGS),
714 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 14, GFLAGS),
715 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri1", 0, RK3368_CLKGATE_CON(19), 15, GFLAGS),
716 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri1", 0, RK3368_CLKGATE_CON(20), 0, GFLAGS),
717 GATE(PCLK_SIM, "pclk_sim", "pclk_peri1", 0, RK3368_CLKGATE_CON(21), 7, GFLAGS),
721 * aclk_video(_pre) can actually select between parents of aclk_vdpu
722 * and aclk_vepu by setting bit GRF_SOC_CON0[7].
724 GATE(ACLK_VIDEO, "aclk_video", "aclk_vdpu", 0, RK3368_CLKGATE_CON(15), 0, GFLAGS),
725 GATE(0, "aclk_video_noc", "aclk_vdpu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 4, GFLAGS),
726 GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
727 GATE(0, "hclk_video_noc", "hclk_video_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 5, GFLAGS),
729 GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK3368_CLKGATE_CON(15), 6, GFLAGS),
730 GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 2, GFLAGS),
731 GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(15), 3, GFLAGS),
732 GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK3368_CLKGATE_CON(15), 7, GFLAGS),
734 /* aclk_rga_pre gates */
735 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
736 GATE(0, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
737 GATE(ACLK_VOP_LITE, "aclk_vop_lite", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 13, GFLAGS),
739 /* aclk_vio0 gates */
740 GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 2, GFLAGS),
741 GATE(ACLK_VOP_FULL, "aclk_vop_full", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 5, GFLAGS),
742 GATE(0, "aclk_vio0_noc", "aclk_vio0", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 9, GFLAGS),
743 GATE(ACLK_VOP_IEP, "aclk_vop_iep", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 4, GFLAGS),
746 GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
747 GATE(0, "hclk_isp_noc", "sclk_isp", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 1, GFLAGS),
748 GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
750 /* aclk_hdcp_pre gates */
751 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
752 GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 15, GFLAGS),
755 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 1, GFLAGS),
756 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 3, GFLAGS),
757 GATE(HCLK_VOP_FULL, "hclk_vop_full", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 6, GFLAGS),
758 GATE(HCLK_VIO_AHB_ARBITER, "hclk_vio_ahb_arbiter", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 7, GFLAGS),
759 GATE(HCLK_VIO_NOC, "hclk_vio_noc", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 8, GFLAGS),
760 GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 7, GFLAGS),
761 GATE(HCLK_VOP_LITE, "hclk_vop_lite", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 14, GFLAGS),
762 GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 11, GFLAGS),
763 GATE(HCLK_VIO_HDCPMMU, "hclk_hdcpmmu", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 12, GFLAGS),
764 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 6, GFLAGS),
765 GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(17), 8, GFLAGS),
766 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3368_CLKGATE_CON(17), 3, GFLAGS),
769 GATE(SCLK_TIMER5, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
770 GATE(SCLK_TIMER4, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
771 GATE(SCLK_TIMER3, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
772 GATE(SCLK_TIMER2, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
773 GATE(SCLK_TIMER1, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
774 GATE(SCLK_TIMER0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
777 static const char *const rk3366_critical_clocks[] __initconst = {
789 static void __init rk3366_clk_init(struct device_node *np)
791 void __iomem *reg_base;
794 reg_base = of_iomap(np, 0);
796 pr_err("%s: could not map cru region\n", __func__);
800 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
802 /* xin12m is created by a cru-internal divider */
803 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
805 pr_warn("%s: could not register clock xin12m: %ld\n",
806 __func__, PTR_ERR(clk));
808 /* ddrphy_div4 is created by a cru-internal divider */
809 clk = clk_register_fixed_factor(NULL, "ddrphy_div4", "ddrphy_src", 0, 1, 4);
811 pr_warn("%s: could not register clock xin12m: %ld\n",
812 __func__, PTR_ERR(clk));
814 clk = clk_register_fixed_factor(NULL, "hclk_video_pre",
815 "hclk_video_pre_v", 0, 1, 4);
817 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
818 __func__, PTR_ERR(clk));
820 clk = clk_register_fixed_factor(NULL, "hclk_rkvdec_pre",
821 "hclk_rkvdec_pre_v", 0, 1, 4);
823 pr_warn("%s: could not register clock hclk_rkvdec_pre: %ld\n",
824 __func__, PTR_ERR(clk));
826 /* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
827 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
829 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
830 __func__, PTR_ERR(clk));
832 rockchip_clk_add_lookup(clk, PCLK_WDT);
834 rockchip_clk_register_plls(rk3366_pll_clks,
835 ARRAY_SIZE(rk3366_pll_clks),
836 RK3366_GRF_SOC_STATUS0);
837 rockchip_clk_register_branches(rk3366_clk_branches,
838 ARRAY_SIZE(rk3366_clk_branches));
839 rockchip_clk_protect_critical(rk3366_critical_clocks,
840 ARRAY_SIZE(rk3366_critical_clocks));
842 rockchip_clk_register_armclk(ARMCLK, "armclk",
843 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
844 &rk3366_cpuclk_data, rk3366_cpuclk_rates,
845 ARRAY_SIZE(rk3366_cpuclk_rates));
847 rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
848 ROCKCHIP_SOFTRST_HIWORD_MASK);
850 rockchip_register_restart_notifier(RK3368_GLB_SRST_FST);
852 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3366-cru", rk3366_clk_init);