drivers/clk/rk/clk-pll.h

   1 #ifndef __RK_CLK_PLL_H
   2 #define __RK_CLK_PLL_H
   3
   4 #include <linux/clk-provider.h>
   5 #include <linux/delay.h>
   6 #include <linux/rockchip/cru.h>
   7
   8
   9 #define CLK_LOOPS_JIFFY_REF     (11996091ULL)
  10 #define CLK_LOOPS_RATE_REF      (1200UL) //Mhz
  11 #define CLK_LOOPS_RECALC(rate)  \
  12         div_u64(CLK_LOOPS_JIFFY_REF*(rate),CLK_LOOPS_RATE_REF*MHZ)
  13
  14 #define CLK_DIV_PLUS_ONE_SET(i, shift, width)   \
  15         ((((i)-1) << (shift)) | (((2<<(width)) - 1) << ((shift)+16)))
  16
  17 /*******************RK3188 PLL******************************/
  18 #define RK3188_PLL_CON(i)       ((i) * 4)
  19 /*******************PLL WORK MODE*************************/
  20 #define _RK3188_PLL_MODE_MSK            0x3
  21 #define _RK3188_PLL_MODE_SLOW           0x0
  22 #define _RK3188_PLL_MODE_NORM           0x1
  23 #define _RK3188_PLL_MODE_DEEP           0x2
  24
  25 #define _RK3188_PLL_MODE_GET(offset, shift)     \
  26         ((cru_readl(offset) >> (shift)) & _RK3188_PLL_MODE_MSK)
  27
  28 #define _RK3188_PLL_MODE_IS_SLOW(offset, shift) \
  29         (_RK3188_PLL_MODE_GET(offset, shift) == _RK3188_PLL_MODE_SLOW)
  30
  31 #define _RK3188_PLL_MODE_IS_NORM(offset, shift) \
  32         (_RK3188_PLL_MODE_GET(offset, shift) == _RK3188_PLL_MODE_NORM)
  33
  34 #define _RK3188_PLL_MODE_IS_DEEP(offset, shift) \
  35         (_RK3188_PLL_MODE_GET(offset, shift) == _RK3188_PLL_MODE_DEEP)
  36
  37 #define _RK3188_PLL_MODE_SET(val, shift)        \
  38         ((val) << (shift)) | CRU_W_MSK(shift, _RK3188_PLL_MODE_MSK)
  39
  40 #define _RK3188_PLL_MODE_SLOW_SET(shift)        \
  41         _RK3188_PLL_MODE_SET(_RK3188_PLL_MODE_SLOW, shift)
  42
  43 #define _RK3188_PLL_MODE_NORM_SET(shift)        \
  44         _RK3188_PLL_MODE_SET(_RK3188_PLL_MODE_NORM, shift)
  45
  46 #define _RK3188_PLL_MODE_DEEP_SET(shift)        \
  47         _RK3188_PLL_MODE_SET(_RK3188_PLL_MODE_DEEP, shift)
  48
  49 /*******************PLL OPERATION MODE*********************/
  50 #define _RK3188_PLL_BYPASS_SHIFT        0
  51 #define _RK3188_PLL_POWERDOWN_SHIFT     1
  52
  53 #define _RK3188PLUS_PLL_BYPASS_SHIFT    0
  54 #define _RK3188PLUS_PLL_POWERDOWN_SHIFT 1
  55 #define _RK3188PLUS_PLL_RESET_SHIFT     5
  56
  57 #define _RK3188_PLL_OP_SET(val, shift)  \
  58         ((val) << (shift)) | CRU_W_MSK(shift, 1)
  59
  60 #define _RK3188_PLL_BYPASS_SET(val)     \
  61         _RK3188_PLL_OP_SET(val, _RK3188_PLL_BYPASS_SHIFT)
  62
  63 #define _RK3188_PLL_POWERDOWN_SET(val)  \
  64         _RK3188_PLL_OP_SET(val, _RK3188_PLL_POWERDOWN_SHIFT)
  65
  66 #define _RK3188PLUS_PLL_BYPASS_SET(val) \
  67         _RK3188_PLL_OP_SET(val, _RK3188PLUS_PLL_BYPASS_SHIFT)
  68
  69 #define _RK3188PLUS_PLL_POWERDOWN_SET(val)      \
  70         _RK3188_PLL_OP_SET(val, _RK3188PLUS_PLL_POWERDOWN_SHIFT)
  71
  72 #define _RK3188PLUS_PLL_RESET_SET(val)  \
  73         _RK3188_PLL_OP_SET(val, _RK3188PLUS_PLL_RESET_SHIFT)
  74
  75 /*******************PLL CON0 BITS***************************/
  76 #define RK3188_PLL_CLKFACTOR_SET(val, shift, msk) \
  77         ((((val) - 1) & (msk)) << (shift))
  78
  79 #define RK3188_PLL_CLKFACTOR_GET(reg, shift, msk) \
  80         ((((reg) >> (shift)) & (msk)) + 1)
  81
  82 #define RK3188_PLL_OD_MSK               (0x3f)
  83 #define RK3188_PLL_OD_SHIFT             (0x0)
  84 #define RK3188_PLL_CLKOD(val)           RK3188_PLL_CLKFACTOR_SET(val, RK3188_PLL_OD_SHIFT, RK3188_PLL_OD_MSK)
  85 #define RK3188_PLL_NO(reg)              RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_OD_SHIFT, RK3188_PLL_OD_MSK)
  86 #define RK3188_PLL_CLKOD_SET(val)       (RK3188_PLL_CLKOD(val) | CRU_W_MSK(RK3188_PLL_OD_SHIFT, RK3188_PLL_OD_MSK))
  87
  88 #define RK3188_PLL_NR_MSK               (0x3f)
  89 #define RK3188_PLL_NR_SHIFT             (8)
  90 #define RK3188_PLL_CLKR(val)            RK3188_PLL_CLKFACTOR_SET(val, RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK)
  91 #define RK3188_PLL_NR(reg)              RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK)
  92 #define RK3188_PLL_CLKR_SET(val)        (RK3188_PLL_CLKR(val) | CRU_W_MSK(RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK))
  93
  94 #define RK3188PLUS_PLL_OD_MSK           (0xf)
  95 #define RK3188PLUS_PLL_OD_SHIFT         (0x0)
  96 #define RK3188PLUS_PLL_CLKOD(val)       RK3188_PLL_CLKFACTOR_SET(val, RK3188PLUS_PLL_OD_SHIFT, RK3188PLUS_PLL_OD_MSK)
  97 #define RK3188PLUS_PLL_NO(reg)          RK3188_PLL_CLKFACTOR_GET(reg, RK3188PLUS_PLL_OD_SHIFT, RK3188PLUS_PLL_OD_MSK)
  98 #define RK3188PLUS_PLL_CLKOD_SET(val)   (RK3188PLUS_PLL_CLKOD(val) | CRU_W_MSK(RK3188PLUS_PLL_OD_SHIFT, RK3188PLUS_PLL_OD_MSK))
  99
 100 #define RK3188PLUS_PLL_NR_MSK           (0x3f)
 101 #define RK3188PLUS_PLL_NR_SHIFT         (8)
 102 #define RK3188PLUS_PLL_CLKR(val)        RK3188_PLL_CLKFACTOR_SET(val, RK3188PLUS_PLL_NR_SHIFT, RK3188PLUS_PLL_NR_MSK)
 103 #define RK3188PLUS_PLL_NR(reg)          RK3188_PLL_CLKFACTOR_GET(reg, RK3188PLUS_PLL_NR_SHIFT, RK3188PLUS_PLL_NR_MSK)
 104 #define RK3188PLUS_PLL_CLKR_SET(val)    (RK3188PLUS_PLL_CLKR(val) | CRU_W_MSK(RK3188PLUS_PLL_NR_SHIFT, RK3188PLUS_PLL_NR_MSK))
 105
 106 /*******************PLL CON1 BITS***************************/
 107 #define RK3188_PLL_NF_MSK               (0xffff)
 108 #define RK3188_PLL_NF_SHIFT             (0)
 109 #define RK3188_PLL_CLKF(val)            RK3188_PLL_CLKFACTOR_SET(val, RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK)
 110 #define RK3188_PLL_NF(reg)              RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK)
 111 #define RK3188_PLL_CLKF_SET(val)        (RK3188_PLL_CLKF(val) | CRU_W_MSK(RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK))
 112
 113 #define RK3188PLUS_PLL_NF_MSK           (0x1fff)
 114 #define RK3188PLUS_PLL_NF_SHIFT         (0)
 115 #define RK3188PLUS_PLL_CLKF(val)        RK3188_PLL_CLKFACTOR_SET(val, RK3188PLUS_PLL_NF_SHIFT, RK3188PLUS_PLL_NF_MSK)
 116 #define RK3188PLUS_PLL_NF(reg)          RK3188_PLL_CLKFACTOR_GET(reg, RK3188PLUS_PLL_NF_SHIFT, RK3188PLUS_PLL_NF_MSK)
 117 #define RK3188PLUS_PLL_CLKF_SET(val)    (RK3188PLUS_PLL_CLKF(val) | CRU_W_MSK(RK3188PLUS_PLL_NF_SHIFT, RK3188PLUS_PLL_NF_MSK))
 118
 119 /*******************PLL CON2 BITS***************************/
 120 #define RK3188_PLL_BWADJ_MSK            (0xfff)
 121 #define RK3188_PLL_BWADJ_SHIFT          (0)
 122 #define RK3188_PLL_CLK_BWADJ_SET(val)   ((val) | CRU_W_MSK(RK3188_PLL_BWADJ_SHIFT, RK3188_PLL_BWADJ_MSK))
 123
 124 #define RK3188PLUS_PLL_BWADJ_MSK        (0xfff)
 125 #define RK3188PLUS_PLL_BWADJ_SHIFT      (0)
 126 #define RK3188PLUS_PLL_CLK_BWADJ_SET(val)       ((val) | CRU_W_MSK(RK3188PLUS_PLL_BWADJ_SHIFT, RK3188PLUS_PLL_BWADJ_MSK))
 127
 128 /*******************PLL CON3 BITS***************************/
 129 #define RK3188_PLL_RESET_MSK            (1 << 5)
 130 #define RK3188_PLL_RESET_W_MSK          (RK3188_PLL_RESET_MSK << 16)
 131 #define RK3188_PLL_RESET                (1 << 5)
 132 #define RK3188_PLL_RESET_RESUME         (0 << 5)
 133
 134 #define RK3188_PLL_BYPASS_MSK           (1 << 0)
 135 #define RK3188_PLL_BYPASS               (1 << 0)
 136 #define RK3188_PLL_NO_BYPASS            (0 << 0)
 137
 138 #define RK3188_PLL_PWR_DN_MSK           (1 << 1)
 139 #define RK3188_PLL_PWR_DN_W_MSK         (RK3188_PLL_PWR_DN_MSK << 16)
 140 #define RK3188_PLL_PWR_DN               (1 << 1)
 141 #define RK3188_PLL_PWR_ON               (0 << 1)
 142
 143 #define RK3188_PLL_STANDBY_MSK          (1 << 2)
 144 #define RK3188_PLL_STANDBY              (1 << 2)
 145 #define RK3188_PLL_NO_STANDBY           (0 << 2)
 146
 147 /*******************CLKSEL0 BITS***************************/
 148 //core_preiph div
 149 #define RK3188_CORE_PERIPH_W_MSK        (3 << 22)
 150 #define RK3188_CORE_PERIPH_MSK          (3 << 6)
 151 #define RK3188_CORE_PERIPH_2            (0 << 6)
 152 #define RK3188_CORE_PERIPH_4            (1 << 6)
 153 #define RK3188_CORE_PERIPH_8            (2 << 6)
 154 #define RK3188_CORE_PERIPH_16           (3 << 6)
 155
 156 //clk_core
 157 #define RK3188_CORE_SEL_PLL_MSK         (1 << 8)
 158 #define RK3188_CORE_SEL_PLL_W_MSK       (1 << 24)
 159 #define RK3188_CORE_SEL_APLL            (0 << 8)
 160 #define RK3188_CORE_SEL_GPLL            (1 << 8)
 161
 162 #define RK3188_CORE_CLK_DIV_W_MSK       (0x1F << 25)
 163 #define RK3188_CORE_CLK_DIV_MSK         (0x1F << 9)
 164 #define RK3188_CORE_CLK_DIV(i)          ((((i) - 1) & 0x1F) << 9)
 165 #define RK3188_CORE_CLK_MAX_DIV         32
 166
 167 /*******************CLKSEL1 BITS***************************/
 168 //aclk_core div
 169 #define RK3188_CORE_ACLK_W_MSK          (7 << 19)
 170 #define RK3188_CORE_ACLK_MSK            (7 << 3)
 171 #define RK3188_CORE_ACLK_11             (0 << 3)
 172 #define RK3188_CORE_ACLK_21             (1 << 3)
 173 #define RK3188_CORE_ACLK_31             (2 << 3)
 174 #define RK3188_CORE_ACLK_41             (3 << 3)
 175 #define RK3188_CORE_ACLK_81             (4 << 3)
 176 #define RK3188_GET_CORE_ACLK_VAL(reg)   ((reg)>=4 ? 8:((reg)+1))
 177
 178 /*******************PLL SET*********************************/
 179 #define _RK3188_PLL_SET_CLKS(_mhz, nr, nf, no) \
 180 { \
 181         .rate   = (_mhz) * KHZ, \
 182         .pllcon0 = RK3188_PLL_CLKR_SET(nr)|RK3188_PLL_CLKOD_SET(no), \
 183         .pllcon1 = RK3188_PLL_CLKF_SET(nf),\
 184         .pllcon2 = RK3188_PLL_CLK_BWADJ_SET(nf >> 1),\
 185         .rst_dly = ((nr*500)/24+1),\
 186 }
 187
 188 #define _RK3188PLUS_PLL_SET_CLKS(_mhz, nr, nf, no) \
 189 { \
 190         .rate   = (_mhz) * KHZ, \
 191         .pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no), \
 192         .pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf),\
 193         .pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1),\
 194         .rst_dly = ((nr*500)/24+1),\
 195 }
 196
 197 #define _RK3188PLUS_PLL_SET_CLKS_NB(_mhz, nr, nf, no, nb) \
 198 { \
 199         .rate   = (_mhz) * KHZ, \
 200         .pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr)|RK3188PLUS_PLL_CLKOD_SET(no), \
 201         .pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf),\
 202         .pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nb-1),\
 203         .rst_dly = ((nr*500)/24+1),\
 204 }
 205
 206 #define _RK3188_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _aclk_div) \
 207 { \
 208         .rate   = _mhz * MHZ, \
 209         .pllcon0 = RK3188_PLL_CLKR_SET(nr) | RK3188_PLL_CLKOD_SET(no), \
 210         .pllcon1 = RK3188_PLL_CLKF_SET(nf),\
 211         .pllcon2 = RK3188_PLL_CLK_BWADJ_SET(nf >> 1),\
 212         .rst_dly = ((nr*500)/24+1),\
 213         .clksel0 = RK3188_CORE_PERIPH_W_MSK | RK3188_CORE_PERIPH_##_periph_div,\
 214         .clksel1 = RK3188_CORE_ACLK_W_MSK | RK3188_CORE_ACLK_##_aclk_div,\
 215         .lpj = (CLK_LOOPS_JIFFY_REF*_mhz) / CLK_LOOPS_RATE_REF,\
 216 }
 217
 218
 219 /*******************RK3288 PLL***********************************/
 220 /*******************CLKSEL0 BITS***************************/
 221 #define RK3288_CORE_SEL_PLL_W_MSK       (1 << 31)
 222 #define RK3288_CORE_SEL_APLL            (0 << 15)
 223 #define RK3288_CORE_SEL_GPLL            (1 << 15)
 224
 225 #define RK3288_CORE_CLK_SHIFT           8
 226 #define RK3288_CORE_CLK_WIDTH           5
 227 #define RK3288_CORE_CLK_DIV(i)  \
 228         CLK_DIV_PLUS_ONE_SET(i, RK3288_CORE_CLK_SHIFT, RK3288_CORE_CLK_WIDTH)
 229 #define RK3288_CORE_CLK_MAX_DIV         (2<<RK3288_CORE_CLK_WIDTH)
 230
 231 #define RK3288_ACLK_M0_SHIFT            0
 232 #define RK3288_ACLK_M0_WIDTH            4
 233 #define RK3288_ACLK_M0_DIV(i)   \
 234         CLK_DIV_PLUS_ONE_SET(i, RK3288_ACLK_M0_SHIFT, RK3288_ACLK_M0_WIDTH)
 235
 236 #define RK3288_ACLK_MP_SHIFT            4
 237 #define RK3288_ACLK_MP_WIDTH            4
 238 #define RK3288_ACLK_MP_DIV(i)   \
 239         CLK_DIV_PLUS_ONE_SET(i, RK3288_ACLK_MP_SHIFT, RK3288_ACLK_MP_WIDTH)
 240
 241 /*******************CLKSEL37 BITS***************************/
 242 #define RK3288_CLK_L2RAM_SHIFT          0
 243 #define RK3288_CLK_L2RAM_WIDTH          3
 244 #define RK3288_CLK_L2RAM_DIV(i) \
 245         CLK_DIV_PLUS_ONE_SET(i, RK3288_CLK_L2RAM_SHIFT, RK3288_CLK_L2RAM_WIDTH)
 246
 247 #define RK3288_ATCLK_SHIFT              4
 248 #define RK3288_ATCLK_WIDTH              5
 249 #define RK3288_ATCLK_DIV(i)     \
 250         CLK_DIV_PLUS_ONE_SET(i, RK3288_ATCLK_SHIFT, RK3288_ATCLK_WIDTH)
 251
 252 #define RK3288_PCLK_DBG_SHIFT           9
 253 #define RK3288_PCLK_DBG_WIDTH           5
 254 #define RK3288_PCLK_DBG_DIV(i)  \
 255         CLK_DIV_PLUS_ONE_SET(i, RK3288_PCLK_DBG_SHIFT, RK3288_PCLK_DBG_WIDTH)
 256
 257 #define _RK3288_APLL_SET_CLKS(_mhz, nr, nf, no, l2_div, m0_div, mp_div, atclk_div, pclk_dbg_div) \
 258 { \
 259         .rate   = _mhz * MHZ, \
 260         .pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr) | RK3188PLUS_PLL_CLKOD_SET(no), \
 261         .pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf),\
 262         .pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1),\
 263         .rst_dly = ((nr*500)/24+1),\
 264         .clksel0 = RK3288_ACLK_M0_DIV(m0_div) | RK3288_ACLK_MP_DIV(mp_div),\
 265         .clksel1 = RK3288_CLK_L2RAM_DIV(l2_div) | RK3288_ATCLK_DIV(atclk_div) | RK3288_PCLK_DBG_DIV(pclk_dbg_div),\
 266         .lpj = (CLK_LOOPS_JIFFY_REF*_mhz) / CLK_LOOPS_RATE_REF,\
 267 }
 268 /***************************RK3036 PLL**************************************/
 269 #define LPJ_24M (CLK_LOOPS_JIFFY_REF * 24) / CLK_LOOPS_RATE_REF
 270 /*PLL_CON 0,1,2*/
 271 #define RK3036_PLL_PWR_ON                       (0)
 272 #define RK3036_PLL_PWR_DN                       (1)
 273 #define RK3036_PLL_BYPASS                       (1 << 15)
 274 #define RK3036_PLL_NO_BYPASS                    (0 << 15)
 275 /*con0*/
 276 #define RK3036_PLL_BYPASS_SHIFT         (15)
 277
 278 #define RK3036_PLL_POSTDIV1_MASK                (0x7)
 279 #define RK3036_PLL_POSTDIV1_SHIFT               (12)
 280 #define RK3036_PLL_FBDIV_MASK                   (0xfff)
 281 #define RK3036_PLL_FBDIV_SHIFT                  (0)
 282
 283 /*con1*/
 284 #define RK3036_PLL_RSTMODE_SHIFT                (15)
 285 #define RK3036_PLL_RST_SHIFT                    (14)
 286 #define RK3036_PLL_PWR_DN_SHIFT         (13)
 287 #define RK3036_PLL_DSMPD_SHIFT                  (12)
 288 #define RK3036_PLL_LOCK_SHIFT                   (10)
 289
 290 #define RK3036_PLL_POSTDIV2_MASK                (0x7)
 291 #define RK3036_PLL_POSTDIV2_SHIFT               (6)
 292 #define RK3036_PLL_REFDIV_MASK                  (0x3f)
 293 #define RK3036_PLL_REFDIV_SHIFT         (0)
 294
 295 /*con2*/
 296 #define RK3036_PLL_FOUT4PHASE_PWR_DN_SHIFT      (27)
 297 #define RK3036_PLL_FOUTVCO_PWR_DN_SHIFT (26)
 298 #define RK3036_PLL_FOUTPOSTDIV_PWR_DN_SHIFT     (25)
 299 #define RK3036_PLL_DAC_PWR_DN_SHIFT             (24)
 300
 301 #define RK3036_PLL_FRAC_MASK                    (0xffffff)
 302 #define RK3036_PLL_FRAC_SHIFT                   (0)
 303
 304 #define CRU_GET_REG_BIT_VAL(reg, bits_shift)            (((reg) >> (bits_shift)) & (0x1))
 305 #define CRU_GET_REG_BITS_VAL(reg, bits_shift, msk)      (((reg) >> (bits_shift)) & (msk))
 306 #define CRU_SET_BIT(val, bits_shift)                    (((val) & (0x1)) << (bits_shift))
 307 #define CRU_W_MSK(bits_shift, msk)                      ((msk) << ((bits_shift) + 16))
 308
 309 #define CRU_W_MSK_SETBITS(val, bits_shift, msk)         (CRU_W_MSK(bits_shift, msk)     \
 310                                                         | CRU_SET_BITS(val, bits_shift, msk))
 311 #define CRU_W_MSK_SETBIT(val, bits_shift)               (CRU_W_MSK(bits_shift, 0x1)     \
 312                                                         | CRU_SET_BIT(val, bits_shift))
 313
 314 #define RK3036_PLL_SET_REFDIV(val)                              CRU_W_MSK_SETBITS(val, RK3036_PLL_REFDIV_SHIFT, RK3036_PLL_REFDIV_MASK)
 315 #define RK3036_PLL_SET_FBDIV(val)                               CRU_W_MSK_SETBITS(val, RK3036_PLL_FBDIV_SHIFT, RK3036_PLL_FBDIV_MASK)
 316 #define RK3036_PLL_SET_POSTDIV1(val)                            CRU_W_MSK_SETBITS(val, RK3036_PLL_POSTDIV1_SHIFT, RK3036_PLL_POSTDIV1_MASK)
 317 #define RK3036_PLL_SET_POSTDIV2(val)                            CRU_W_MSK_SETBITS(val, RK3036_PLL_POSTDIV2_SHIFT, RK3036_PLL_POSTDIV2_MASK)
 318 #define RK3036_PLL_SET_FRAC(val)                                CRU_SET_BITS(val, RK3036_PLL_FRAC_SHIFT, RK3036_PLL_FRAC_MASK)
 319
 320 #define RK3036_PLL_GET_REFDIV(reg)                              CRU_GET_REG_BITS_VAL(reg, RK3036_PLL_REFDIV_SHIFT, RK3036_PLL_REFDIV_MASK)
 321 #define RK3036_PLL_GET_FBDIV(reg)                               CRU_GET_REG_BITS_VAL(reg, RK3036_PLL_FBDIV_SHIFT, RK3036_PLL_FBDIV_MASK)
 322 #define RK3036_PLL_GET_POSTDIV1(reg)                            CRU_GET_REG_BITS_VAL(reg, RK3036_PLL_POSTDIV1_SHIFT, RK3036_PLL_POSTDIV1_MASK)
 323 #define RK3036_PLL_GET_POSTDIV2(reg)                            CRU_GET_REG_BITS_VAL(reg, RK3036_PLL_POSTDIV2_SHIFT, RK3036_PLL_POSTDIV2_MASK)
 324 #define RK3036_PLL_GET_FRAC(reg)                                CRU_GET_REG_BITS_VAL(reg, RK3036_PLL_FRAC_SHIFT, RK3036_PLL_FRAC_MASK)
 325
 326 /*#define APLL_SET_BYPASS(val)                          CRU_SET_BIT(val, PLL_BYPASS_SHIFT)*/
 327 #define RK3036_PLL_SET_DSMPD(val)                               CRU_W_MSK_SETBIT(val, RK3036_PLL_DSMPD_SHIFT)
 328 #define RK3036_PLL_GET_DSMPD(reg)                               CRU_GET_REG_BIT_VAL(reg, RK3036_PLL_DSMPD_SHIFT)
 329
 330 /*******************CLKSEL0 BITS***************************/
 331 #define RK3036_CLK_SET_DIV_CON_SUB1(val, bits_shift, msk)       CRU_W_MSK_SETBITS((val - 1), bits_shift, msk)
 332
 333 #define RK3036_CPU_CLK_PLL_SEL_SHIFT            (14)
 334 #define RK3036_CPU_CLK_PLL_SEL_MASK     (0x3)
 335 #define RK3036_CORE_CLK_PLL_SEL_SHIFT           (7)
 336 #define RK3036_SEL_APLL                 (0)
 337 #define RK3036_SEL_GPLL                 (1)
 338 #define RK3036_CPU_SEL_PLL(plls)                CRU_W_MSK_SETBITS(plls, RK3036_CPU_CLK_PLL_SEL_SHIFT, RK3036_CPU_CLK_PLL_SEL_MASK)
 339 #define RK3036_CORE_SEL_PLL(plls)               CRU_W_MSK_SETBIT(plls, RK3036_CORE_CLK_PLL_SEL_SHIFT)
 340
 341 #define RK3036_ACLK_CPU_DIV_MASK                (0x1f)
 342 #define RK3036_ACLK_CPU_DIV_SHIFT               (8)
 343 #define RK3036_A9_CORE_DIV_MASK         (0x1f)
 344 #define RK3036_A9_CORE_DIV_SHIFT                (0)
 345
 346 #define RATIO_11                (1)
 347 #define RATIO_21                (2)
 348 #define RATIO_41                (4)
 349 #define RATIO_81                (8)
 350
 351 #define RK3036_ACLK_CPU_DIV(val)                RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_ACLK_CPU_DIV_SHIFT, RK3036_ACLK_CPU_DIV_MASK)
 352 #define RK3036_CLK_CORE_DIV(val)                RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_A9_CORE_DIV_SHIFT, RK3036_A9_CORE_DIV_MASK)
 353 /*******************CLKSEL1 BITS***************************/
 354 #define RK3036_PCLK_CPU_DIV_MASK                (0x7)
 355 #define RK3036_PCLK_CPU_DIV_SHIFT               (12)
 356 #define RK3036_HCLK_CPU_DIV_MASK                (0x3)
 357 #define RK3036_HCLK_CPU_DIV_SHIFT               (8)
 358 #define RK3036_ACLK_CORE_DIV_MASK               (0x7)
 359 #define RK3036_ACLK_CORE_DIV_SHIFT              (4)
 360 #define RK3036_CORE_PERIPH_DIV_MASK             (0xf)
 361 #define RK3036_CORE_PERIPH_DIV_SHIFT            (0)
 362
 363 #define RK3036_PCLK_CPU_DIV(val)                RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_PCLK_CPU_DIV_SHIFT, RK3036_PCLK_CPU_DIV_MASK)
 364 #define RK3036_HCLK_CPU_DIV(val)                RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_HCLK_CPU_DIV_SHIFT, RK3036_HCLK_CPU_DIV_MASK)
 365 #define RK3036_ACLK_CORE_DIV(val)               RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_ACLK_CORE_DIV_SHIFT, RK3036_ACLK_CORE_DIV_MASK)
 366 #define RK3036_CLK_CORE_PERI_DIV(val)           RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_CORE_PERIPH_DIV_SHIFT, RK3036_CORE_PERIPH_DIV_MASK)
 367
 368 /*******************clksel10***************************/
 369 #define RK3036_PERI_PLL_SEL_SHIFT       14
 370 #define RK3036_PERI_PLL_SEL_MASK        (0x3)
 371 #define RK3036_PERI_PCLK_DIV_MASK       (0x3)
 372 #define RK3036_PERI_PCLK_DIV_SHIFT      (12)
 373 #define RK3036_PERI_HCLK_DIV_MASK       (0x3)
 374 #define RK3036_PERI_HCLK_DIV_SHIFT      (8)
 375 #define RK3036_PERI_ACLK_DIV_MASK       (0x1f)
 376 #define RK3036_PERI_ACLK_DIV_SHIFT      (0)
 377
 378 #define RK3036_SEL_3PLL_APLL            (0)
 379 #define RK3036_SEL_3PLL_DPLL            (1)
 380 #define RK3036_SEL_3PLL_GPLL            (2)
 381
 382
 383 #define RK3036_PERI_CLK_SEL_PLL(plls)   CRU_W_MSK_SETBITS(plls, RK3036_PERI_PLL_SEL_SHIFT, RK3036_PERI_PLL_SEL_MASK)
 384 #define RK3036_PERI_SET_ACLK_DIV(val)           RK3036_CLK_SET_DIV_CON_SUB1(val, RK3036_PERI_ACLK_DIV_SHIFT, RK3036_PERI_ACLK_DIV_MASK)
 385
 386 /*******************gate BITS***************************/
 387 #define RK3036_CLK_GATE_CLKID_CONS(i)   RK3036_CRU_CLKGATES_CON((i) / 16)
 388
 389 #define RK3036_CLK_GATE(i)              (1 << ((i)%16))
 390 #define RK3036_CLK_UN_GATE(i)           (0)
 391
 392 #define RK3036_CLK_GATE_W_MSK(i)        (1 << (((i) % 16) + 16))
 393 #define RK3036_CLK_GATE_CLKID(i)        (16 * (i))
 394
 395 #define _RK3036_APLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac, \
 396                 _periph_div) \
 397 { \
 398         .rate   = (_mhz) * MHZ, \
 399         .pllcon0 = RK3036_PLL_SET_POSTDIV1(_postdiv1) | RK3036_PLL_SET_FBDIV(_fbdiv),   \
 400         .pllcon1 = RK3036_PLL_SET_DSMPD(_dsmpd) | RK3036_PLL_SET_POSTDIV2(_postdiv2) | RK3036_PLL_SET_REFDIV(_refdiv),  \
 401         .pllcon2 = RK3036_PLL_SET_FRAC(_frac),  \
 402         .clksel1 = RK3036_CLK_CORE_PERI_DIV(RATIO_##_periph_div),       \
 403         .lpj    = (CLK_LOOPS_JIFFY_REF * _mhz) / CLK_LOOPS_RATE_REF,    \
 404         .rst_dly = 0,\
 405 }
 406
 407 #define _RK3036_PLL_SET_CLKS(_mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac) \
 408 { \
 409         .rate   = (_mhz) * KHZ, \
 410         .pllcon0 = RK3036_PLL_SET_POSTDIV1(_postdiv1) | RK3036_PLL_SET_FBDIV(_fbdiv),   \
 411         .pllcon1 = RK3036_PLL_SET_DSMPD(_dsmpd) | RK3036_PLL_SET_POSTDIV2(_postdiv2) | RK3036_PLL_SET_REFDIV(_refdiv),  \
 412         .pllcon2 = RK3036_PLL_SET_FRAC(_frac),  \
 413 }
 414
 415 /***************************RK3368 PLL**************************************/
 416 /*******************CLKSEL0/2 BITS***************************/
 417 #define RK3368_CORE_SEL_PLL_W_MSK       (1 << 23)
 418 #define RK3368_CORE_SEL_APLL            (0 << 7)
 419 #define RK3368_CORE_SEL_GPLL            (1 << 7)
 420
 421 #define RK3368_CORE_CLK_SHIFT           0
 422 #define RK3368_CORE_CLK_WIDTH           5
 423 #define RK3368_CORE_CLK_DIV(i)  \
 424         CLK_DIV_PLUS_ONE_SET(i, RK3368_CORE_CLK_SHIFT, RK3368_CORE_CLK_WIDTH)
 425 #define RK3368_CORE_CLK_MAX_DIV         (2<<RK3368_CORE_CLK_WIDTH)
 426
 427 #define RK3368_ACLKM_CORE_SHIFT         8
 428 #define RK3368_ACLKM_CORE_WIDTH         5
 429 #define RK3368_ACLKM_CORE_DIV(i)        \
 430         CLK_DIV_PLUS_ONE_SET(i, RK3368_ACLKM_CORE_SHIFT, RK3368_ACLKM_CORE_WIDTH)
 431
 432 /*******************CLKSEL1/3 BITS***************************/
 433 #define RK3368_ATCLK_CORE_SHIFT         0
 434 #define RK3368_ATCLK_CORE_WIDTH         5
 435 #define RK3368_ATCLK_CORE_DIV(i)        \
 436         CLK_DIV_PLUS_ONE_SET(i, RK3368_ATCLK_CORE_SHIFT, RK3368_ATCLK_CORE_WIDTH)
 437
 438 #define RK3368_PCLK_DBG_SHIFT           8
 439 #define RK3368_PCLK_DBG_WIDTH           5
 440 #define RK3368_PCLK_DBG_DIV(i)  \
 441         CLK_DIV_PLUS_ONE_SET(i, RK3368_PCLK_DBG_SHIFT, RK3368_PCLK_DBG_WIDTH)
 442
 443 #define _RK3368_APLL_SET_CLKS(_mhz, nr, nf, no, aclkm_div, atclk_div, pclk_dbg_div) \
 444 { \
 445         .rate   = _mhz * MHZ, \
 446         .pllcon0 = RK3188PLUS_PLL_CLKR_SET(nr) | RK3188PLUS_PLL_CLKOD_SET(no), \
 447         .pllcon1 = RK3188PLUS_PLL_CLKF_SET(nf),\
 448         .pllcon2 = RK3188PLUS_PLL_CLK_BWADJ_SET(nf >> 1),\
 449         .rst_dly = ((nr*500)/24+1),\
 450         .clksel0 = RK3368_ACLKM_CORE_DIV(aclkm_div),\
 451         .clksel1 = RK3368_ATCLK_CORE_DIV(atclk_div) | RK3368_PCLK_DBG_DIV(pclk_dbg_div) \
 452 }
 453
 454 struct pll_clk_set {
 455         unsigned long   rate;
 456         u32     pllcon0;
 457         u32     pllcon1;
 458         u32     pllcon2;
 459         unsigned long   rst_dly;//us
 460 };
 461
 462 struct apll_clk_set {
 463         unsigned long   rate;
 464         u32     pllcon0;
 465         u32     pllcon1;
 466         u32     pllcon2;
 467         u32     rst_dly;//us
 468         u32     clksel0;
 469         u32     clksel1;
 470         unsigned long   lpj;
 471 };
 472
 473
 474 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
 475
 476 struct clk_pll {
 477         struct clk_hw   hw;
 478         u32             reg;
 479         u32             width;
 480         u32             mode_offset;
 481         u8              mode_shift;
 482         u32             status_offset;
 483         u8              status_shift;
 484         u32             flags;
 485         const void      *table;
 486         spinlock_t      *lock;
 487 };
 488
 489 const struct clk_ops *rk_get_pll_ops(u32 pll_flags);
 490
 491 struct clk *rk_clk_register_pll(struct device *dev, const char *name,
 492                 const char *parent_name, unsigned long flags, u32 reg,
 493                 u32 width, u32 mode_offset, u8 mode_shift,
 494                 u32 status_offset, u8 status_shift, u32 pll_flags,
 495                 spinlock_t *lock);
 496
 497
 498 #endif /* __RK_CLK_PLL_H */