2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/module.h>
17 #include <linux/regmap.h>
18 #include <linux/reset-controller.h>
20 #include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21 #include <dt-bindings/reset/qcom,mmcc-apq8084.h>
24 #include "clk-regmap.h"
27 #include "clk-branch.h"
49 static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
56 static const char * const mmcc_xo_mmpll0_mmpll1_gpll0[] = {
63 static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
72 static const char * const mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
81 static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
89 static const char * const mmcc_xo_mmpll0_1_2_gpll0[] = {
97 static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
105 static const char * const mmcc_xo_mmpll0_1_3_gpll0[] = {
113 static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
122 static const char * const mmcc_xo_dsi_hdmi_edp[] = {
131 static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
140 static const char * const mmcc_xo_dsi_hdmi_edp_gpll0[] = {
149 static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
154 { P_DSI0PLL_BYTE, 1 },
155 { P_DSI1PLL_BYTE, 2 }
158 static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
167 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
175 static const char * const mmcc_xo_mmpll0_1_4_gpll0[] = {
183 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
192 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0[] = {
201 static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
211 static const char * const mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
221 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
223 static struct clk_pll mmpll0 = {
227 .config_reg = 0x0014,
229 .status_reg = 0x001c,
231 .clkr.hw.init = &(struct clk_init_data){
233 .parent_names = (const char *[]){ "xo" },
239 static struct clk_regmap mmpll0_vote = {
240 .enable_reg = 0x0100,
241 .enable_mask = BIT(0),
242 .hw.init = &(struct clk_init_data){
243 .name = "mmpll0_vote",
244 .parent_names = (const char *[]){ "mmpll0" },
246 .ops = &clk_pll_vote_ops,
250 static struct clk_pll mmpll1 = {
254 .config_reg = 0x0050,
256 .status_reg = 0x005c,
258 .clkr.hw.init = &(struct clk_init_data){
260 .parent_names = (const char *[]){ "xo" },
266 static struct clk_regmap mmpll1_vote = {
267 .enable_reg = 0x0100,
268 .enable_mask = BIT(1),
269 .hw.init = &(struct clk_init_data){
270 .name = "mmpll1_vote",
271 .parent_names = (const char *[]){ "mmpll1" },
273 .ops = &clk_pll_vote_ops,
277 static struct clk_pll mmpll2 = {
281 .config_reg = 0x4110,
283 .status_reg = 0x411c,
284 .clkr.hw.init = &(struct clk_init_data){
286 .parent_names = (const char *[]){ "xo" },
292 static struct clk_pll mmpll3 = {
296 .config_reg = 0x0090,
298 .status_reg = 0x009c,
300 .clkr.hw.init = &(struct clk_init_data){
302 .parent_names = (const char *[]){ "xo" },
308 static struct clk_pll mmpll4 = {
312 .config_reg = 0x00b0,
314 .status_reg = 0x00bc,
315 .clkr.hw.init = &(struct clk_init_data){
317 .parent_names = (const char *[]){ "xo" },
323 static struct clk_rcg2 mmss_ahb_clk_src = {
326 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
327 .clkr.hw.init = &(struct clk_init_data){
328 .name = "mmss_ahb_clk_src",
329 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
331 .ops = &clk_rcg2_ops,
335 static struct freq_tbl ftbl_mmss_axi_clk[] = {
336 F(19200000, P_XO, 1, 0, 0),
337 F(37500000, P_GPLL0, 16, 0, 0),
338 F(50000000, P_GPLL0, 12, 0, 0),
339 F(75000000, P_GPLL0, 8, 0, 0),
340 F(100000000, P_GPLL0, 6, 0, 0),
341 F(150000000, P_GPLL0, 4, 0, 0),
342 F(333430000, P_MMPLL1, 3.5, 0, 0),
343 F(400000000, P_MMPLL0, 2, 0, 0),
344 F(466800000, P_MMPLL1, 2.5, 0, 0),
347 static struct clk_rcg2 mmss_axi_clk_src = {
350 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
351 .freq_tbl = ftbl_mmss_axi_clk,
352 .clkr.hw.init = &(struct clk_init_data){
353 .name = "mmss_axi_clk_src",
354 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
356 .ops = &clk_rcg2_ops,
360 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
361 F(19200000, P_XO, 1, 0, 0),
362 F(37500000, P_GPLL0, 16, 0, 0),
363 F(50000000, P_GPLL0, 12, 0, 0),
364 F(75000000, P_GPLL0, 8, 0, 0),
365 F(109090000, P_GPLL0, 5.5, 0, 0),
366 F(150000000, P_GPLL0, 4, 0, 0),
367 F(228570000, P_MMPLL0, 3.5, 0, 0),
368 F(320000000, P_MMPLL0, 2.5, 0, 0),
371 static struct clk_rcg2 ocmemnoc_clk_src = {
374 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
375 .freq_tbl = ftbl_ocmemnoc_clk,
376 .clkr.hw.init = &(struct clk_init_data){
377 .name = "ocmemnoc_clk_src",
378 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
380 .ops = &clk_rcg2_ops,
384 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
385 F(100000000, P_GPLL0, 6, 0, 0),
386 F(200000000, P_MMPLL0, 4, 0, 0),
390 static struct clk_rcg2 csi0_clk_src = {
393 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
394 .freq_tbl = ftbl_camss_csi0_3_clk,
395 .clkr.hw.init = &(struct clk_init_data){
396 .name = "csi0_clk_src",
397 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
399 .ops = &clk_rcg2_ops,
403 static struct clk_rcg2 csi1_clk_src = {
406 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
407 .freq_tbl = ftbl_camss_csi0_3_clk,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "csi1_clk_src",
410 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
412 .ops = &clk_rcg2_ops,
416 static struct clk_rcg2 csi2_clk_src = {
419 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
420 .freq_tbl = ftbl_camss_csi0_3_clk,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "csi2_clk_src",
423 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
425 .ops = &clk_rcg2_ops,
429 static struct clk_rcg2 csi3_clk_src = {
432 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
433 .freq_tbl = ftbl_camss_csi0_3_clk,
434 .clkr.hw.init = &(struct clk_init_data){
435 .name = "csi3_clk_src",
436 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
438 .ops = &clk_rcg2_ops,
442 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
443 F(37500000, P_GPLL0, 16, 0, 0),
444 F(50000000, P_GPLL0, 12, 0, 0),
445 F(60000000, P_GPLL0, 10, 0, 0),
446 F(80000000, P_GPLL0, 7.5, 0, 0),
447 F(100000000, P_GPLL0, 6, 0, 0),
448 F(109090000, P_GPLL0, 5.5, 0, 0),
449 F(133330000, P_GPLL0, 4.5, 0, 0),
450 F(200000000, P_GPLL0, 3, 0, 0),
451 F(228570000, P_MMPLL0, 3.5, 0, 0),
452 F(266670000, P_MMPLL0, 3, 0, 0),
453 F(320000000, P_MMPLL0, 2.5, 0, 0),
454 F(465000000, P_MMPLL4, 2, 0, 0),
455 F(600000000, P_GPLL0, 1, 0, 0),
459 static struct clk_rcg2 vfe0_clk_src = {
462 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
463 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
464 .clkr.hw.init = &(struct clk_init_data){
465 .name = "vfe0_clk_src",
466 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
468 .ops = &clk_rcg2_ops,
472 static struct clk_rcg2 vfe1_clk_src = {
475 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
476 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
477 .clkr.hw.init = &(struct clk_init_data){
478 .name = "vfe1_clk_src",
479 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
481 .ops = &clk_rcg2_ops,
485 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
486 F(37500000, P_GPLL0, 16, 0, 0),
487 F(60000000, P_GPLL0, 10, 0, 0),
488 F(75000000, P_GPLL0, 8, 0, 0),
489 F(85710000, P_GPLL0, 7, 0, 0),
490 F(100000000, P_GPLL0, 6, 0, 0),
491 F(150000000, P_GPLL0, 4, 0, 0),
492 F(160000000, P_MMPLL0, 5, 0, 0),
493 F(200000000, P_MMPLL0, 4, 0, 0),
494 F(228570000, P_MMPLL0, 3.5, 0, 0),
495 F(300000000, P_GPLL0, 2, 0, 0),
496 F(320000000, P_MMPLL0, 2.5, 0, 0),
500 static struct clk_rcg2 mdp_clk_src = {
503 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
504 .freq_tbl = ftbl_mdss_mdp_clk,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "mdp_clk_src",
507 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
509 .ops = &clk_rcg2_ops,
513 static struct clk_rcg2 gfx3d_clk_src = {
516 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
517 .clkr.hw.init = &(struct clk_init_data){
518 .name = "gfx3d_clk_src",
519 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
521 .ops = &clk_rcg2_ops,
525 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
526 F(75000000, P_GPLL0, 8, 0, 0),
527 F(133330000, P_GPLL0, 4.5, 0, 0),
528 F(200000000, P_GPLL0, 3, 0, 0),
529 F(228570000, P_MMPLL0, 3.5, 0, 0),
530 F(266670000, P_MMPLL0, 3, 0, 0),
531 F(320000000, P_MMPLL0, 2.5, 0, 0),
535 static struct clk_rcg2 jpeg0_clk_src = {
538 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
539 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
540 .clkr.hw.init = &(struct clk_init_data){
541 .name = "jpeg0_clk_src",
542 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
544 .ops = &clk_rcg2_ops,
548 static struct clk_rcg2 jpeg1_clk_src = {
551 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
552 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
553 .clkr.hw.init = &(struct clk_init_data){
554 .name = "jpeg1_clk_src",
555 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
557 .ops = &clk_rcg2_ops,
561 static struct clk_rcg2 jpeg2_clk_src = {
564 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
565 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "jpeg2_clk_src",
568 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
570 .ops = &clk_rcg2_ops,
574 static struct freq_tbl pixel_freq_tbl[] = {
575 { .src = P_DSI0PLL },
579 static struct clk_rcg2 pclk0_clk_src = {
583 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
584 .freq_tbl = pixel_freq_tbl,
585 .clkr.hw.init = &(struct clk_init_data){
586 .name = "pclk0_clk_src",
587 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
589 .ops = &clk_pixel_ops,
590 .flags = CLK_SET_RATE_PARENT,
594 static struct clk_rcg2 pclk1_clk_src = {
598 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
599 .freq_tbl = pixel_freq_tbl,
600 .clkr.hw.init = &(struct clk_init_data){
601 .name = "pclk1_clk_src",
602 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
604 .ops = &clk_pixel_ops,
605 .flags = CLK_SET_RATE_PARENT,
609 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
610 F(50000000, P_GPLL0, 12, 0, 0),
611 F(100000000, P_GPLL0, 6, 0, 0),
612 F(133330000, P_GPLL0, 4.5, 0, 0),
613 F(200000000, P_MMPLL0, 4, 0, 0),
614 F(266670000, P_MMPLL0, 3, 0, 0),
615 F(465000000, P_MMPLL3, 2, 0, 0),
619 static struct clk_rcg2 vcodec0_clk_src = {
623 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
624 .freq_tbl = ftbl_venus0_vcodec0_clk,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "vcodec0_clk_src",
627 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
629 .ops = &clk_rcg2_ops,
633 static struct freq_tbl ftbl_avsync_vp_clk[] = {
634 F(150000000, P_GPLL0, 4, 0, 0),
635 F(320000000, P_MMPLL0, 2.5, 0, 0),
639 static struct clk_rcg2 vp_clk_src = {
642 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
643 .freq_tbl = ftbl_avsync_vp_clk,
644 .clkr.hw.init = &(struct clk_init_data){
645 .name = "vp_clk_src",
646 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
648 .ops = &clk_rcg2_ops,
652 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
653 F(19200000, P_XO, 1, 0, 0),
657 static struct clk_rcg2 cci_clk_src = {
661 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
662 .freq_tbl = ftbl_camss_cci_cci_clk,
663 .clkr.hw.init = &(struct clk_init_data){
664 .name = "cci_clk_src",
665 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
667 .ops = &clk_rcg2_ops,
671 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
672 F(10000, P_XO, 16, 1, 120),
673 F(24000, P_XO, 16, 1, 50),
674 F(6000000, P_GPLL0, 10, 1, 10),
675 F(12000000, P_GPLL0, 10, 1, 5),
676 F(13000000, P_GPLL0, 4, 13, 150),
677 F(24000000, P_GPLL0, 5, 1, 5),
681 static struct clk_rcg2 camss_gp0_clk_src = {
685 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
686 .freq_tbl = ftbl_camss_gp0_1_clk,
687 .clkr.hw.init = &(struct clk_init_data){
688 .name = "camss_gp0_clk_src",
689 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
691 .ops = &clk_rcg2_ops,
695 static struct clk_rcg2 camss_gp1_clk_src = {
699 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
700 .freq_tbl = ftbl_camss_gp0_1_clk,
701 .clkr.hw.init = &(struct clk_init_data){
702 .name = "camss_gp1_clk_src",
703 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
705 .ops = &clk_rcg2_ops,
709 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
710 F(4800000, P_XO, 4, 0, 0),
711 F(6000000, P_GPLL0, 10, 1, 10),
712 F(8000000, P_GPLL0, 15, 1, 5),
713 F(9600000, P_XO, 2, 0, 0),
714 F(16000000, P_MMPLL0, 10, 1, 5),
715 F(19200000, P_XO, 1, 0, 0),
716 F(24000000, P_GPLL0, 5, 1, 5),
717 F(32000000, P_MMPLL0, 5, 1, 5),
718 F(48000000, P_GPLL0, 12.5, 0, 0),
719 F(64000000, P_MMPLL0, 12.5, 0, 0),
723 static struct clk_rcg2 mclk0_clk_src = {
727 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
728 .freq_tbl = ftbl_camss_mclk0_3_clk,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "mclk0_clk_src",
731 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
733 .ops = &clk_rcg2_ops,
737 static struct clk_rcg2 mclk1_clk_src = {
741 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
742 .freq_tbl = ftbl_camss_mclk0_3_clk,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "mclk1_clk_src",
745 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
747 .ops = &clk_rcg2_ops,
751 static struct clk_rcg2 mclk2_clk_src = {
755 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
756 .freq_tbl = ftbl_camss_mclk0_3_clk,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "mclk2_clk_src",
759 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
761 .ops = &clk_rcg2_ops,
765 static struct clk_rcg2 mclk3_clk_src = {
769 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
770 .freq_tbl = ftbl_camss_mclk0_3_clk,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "mclk3_clk_src",
773 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
775 .ops = &clk_rcg2_ops,
779 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
780 F(100000000, P_GPLL0, 6, 0, 0),
781 F(200000000, P_MMPLL0, 4, 0, 0),
785 static struct clk_rcg2 csi0phytimer_clk_src = {
788 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
789 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
790 .clkr.hw.init = &(struct clk_init_data){
791 .name = "csi0phytimer_clk_src",
792 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
794 .ops = &clk_rcg2_ops,
798 static struct clk_rcg2 csi1phytimer_clk_src = {
801 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
802 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
803 .clkr.hw.init = &(struct clk_init_data){
804 .name = "csi1phytimer_clk_src",
805 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
807 .ops = &clk_rcg2_ops,
811 static struct clk_rcg2 csi2phytimer_clk_src = {
814 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
815 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
816 .clkr.hw.init = &(struct clk_init_data){
817 .name = "csi2phytimer_clk_src",
818 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
820 .ops = &clk_rcg2_ops,
824 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
825 F(133330000, P_GPLL0, 4.5, 0, 0),
826 F(266670000, P_MMPLL0, 3, 0, 0),
827 F(320000000, P_MMPLL0, 2.5, 0, 0),
828 F(372000000, P_MMPLL4, 2.5, 0, 0),
829 F(465000000, P_MMPLL4, 2, 0, 0),
830 F(600000000, P_GPLL0, 1, 0, 0),
834 static struct clk_rcg2 cpp_clk_src = {
837 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
838 .freq_tbl = ftbl_camss_vfe_cpp_clk,
839 .clkr.hw.init = &(struct clk_init_data){
840 .name = "cpp_clk_src",
841 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
843 .ops = &clk_rcg2_ops,
847 static struct freq_tbl byte_freq_tbl[] = {
848 { .src = P_DSI0PLL_BYTE },
852 static struct clk_rcg2 byte0_clk_src = {
855 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
856 .freq_tbl = byte_freq_tbl,
857 .clkr.hw.init = &(struct clk_init_data){
858 .name = "byte0_clk_src",
859 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
861 .ops = &clk_byte_ops,
862 .flags = CLK_SET_RATE_PARENT,
866 static struct clk_rcg2 byte1_clk_src = {
869 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
870 .freq_tbl = byte_freq_tbl,
871 .clkr.hw.init = &(struct clk_init_data){
872 .name = "byte1_clk_src",
873 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
875 .ops = &clk_byte_ops,
876 .flags = CLK_SET_RATE_PARENT,
880 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
881 F(19200000, P_XO, 1, 0, 0),
885 static struct clk_rcg2 edpaux_clk_src = {
888 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
889 .freq_tbl = ftbl_mdss_edpaux_clk,
890 .clkr.hw.init = &(struct clk_init_data){
891 .name = "edpaux_clk_src",
892 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
894 .ops = &clk_rcg2_ops,
898 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
899 F(135000000, P_EDPLINK, 2, 0, 0),
900 F(270000000, P_EDPLINK, 11, 0, 0),
904 static struct clk_rcg2 edplink_clk_src = {
907 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
908 .freq_tbl = ftbl_mdss_edplink_clk,
909 .clkr.hw.init = &(struct clk_init_data){
910 .name = "edplink_clk_src",
911 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
913 .ops = &clk_rcg2_ops,
914 .flags = CLK_SET_RATE_PARENT,
918 static struct freq_tbl edp_pixel_freq_tbl[] = {
923 static struct clk_rcg2 edppixel_clk_src = {
927 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
928 .freq_tbl = edp_pixel_freq_tbl,
929 .clkr.hw.init = &(struct clk_init_data){
930 .name = "edppixel_clk_src",
931 .parent_names = mmcc_xo_dsi_hdmi_edp,
933 .ops = &clk_edp_pixel_ops,
937 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
938 F(19200000, P_XO, 1, 0, 0),
942 static struct clk_rcg2 esc0_clk_src = {
945 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
946 .freq_tbl = ftbl_mdss_esc0_1_clk,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "esc0_clk_src",
949 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
951 .ops = &clk_rcg2_ops,
955 static struct clk_rcg2 esc1_clk_src = {
958 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
959 .freq_tbl = ftbl_mdss_esc0_1_clk,
960 .clkr.hw.init = &(struct clk_init_data){
961 .name = "esc1_clk_src",
962 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
964 .ops = &clk_rcg2_ops,
968 static struct freq_tbl extpclk_freq_tbl[] = {
969 { .src = P_HDMIPLL },
973 static struct clk_rcg2 extpclk_clk_src = {
976 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
977 .freq_tbl = extpclk_freq_tbl,
978 .clkr.hw.init = &(struct clk_init_data){
979 .name = "extpclk_clk_src",
980 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
982 .ops = &clk_byte_ops,
983 .flags = CLK_SET_RATE_PARENT,
987 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
988 F(19200000, P_XO, 1, 0, 0),
992 static struct clk_rcg2 hdmi_clk_src = {
995 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
996 .freq_tbl = ftbl_mdss_hdmi_clk,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "hdmi_clk_src",
999 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1001 .ops = &clk_rcg2_ops,
1005 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1006 F(19200000, P_XO, 1, 0, 0),
1010 static struct clk_rcg2 vsync_clk_src = {
1013 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1014 .freq_tbl = ftbl_mdss_vsync_clk,
1015 .clkr.hw.init = &(struct clk_init_data){
1016 .name = "vsync_clk_src",
1017 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1019 .ops = &clk_rcg2_ops,
1023 static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1024 F(50000000, P_GPLL0, 12, 0, 0),
1028 static struct clk_rcg2 rbcpr_clk_src = {
1031 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1032 .freq_tbl = ftbl_mmss_rbcpr_clk,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "rbcpr_clk_src",
1035 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1037 .ops = &clk_rcg2_ops,
1041 static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1042 F(19200000, P_XO, 1, 0, 0),
1046 static struct clk_rcg2 rbbmtimer_clk_src = {
1049 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1050 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "rbbmtimer_clk_src",
1053 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1055 .ops = &clk_rcg2_ops,
1059 static struct freq_tbl ftbl_vpu_maple_clk[] = {
1060 F(50000000, P_GPLL0, 12, 0, 0),
1061 F(100000000, P_GPLL0, 6, 0, 0),
1062 F(133330000, P_GPLL0, 4.5, 0, 0),
1063 F(200000000, P_MMPLL0, 4, 0, 0),
1064 F(266670000, P_MMPLL0, 3, 0, 0),
1065 F(465000000, P_MMPLL3, 2, 0, 0),
1069 static struct clk_rcg2 maple_clk_src = {
1072 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1073 .freq_tbl = ftbl_vpu_maple_clk,
1074 .clkr.hw.init = &(struct clk_init_data){
1075 .name = "maple_clk_src",
1076 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1078 .ops = &clk_rcg2_ops,
1082 static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1083 F(50000000, P_GPLL0, 12, 0, 0),
1084 F(100000000, P_GPLL0, 6, 0, 0),
1085 F(200000000, P_MMPLL0, 4, 0, 0),
1086 F(320000000, P_MMPLL0, 2.5, 0, 0),
1087 F(400000000, P_MMPLL0, 2, 0, 0),
1091 static struct clk_rcg2 vdp_clk_src = {
1094 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1095 .freq_tbl = ftbl_vpu_vdp_clk,
1096 .clkr.hw.init = &(struct clk_init_data){
1097 .name = "vdp_clk_src",
1098 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1100 .ops = &clk_rcg2_ops,
1104 static struct freq_tbl ftbl_vpu_bus_clk[] = {
1105 F(40000000, P_GPLL0, 15, 0, 0),
1106 F(80000000, P_MMPLL0, 10, 0, 0),
1110 static struct clk_rcg2 vpu_bus_clk_src = {
1113 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1114 .freq_tbl = ftbl_vpu_bus_clk,
1115 .clkr.hw.init = &(struct clk_init_data){
1116 .name = "vpu_bus_clk_src",
1117 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1119 .ops = &clk_rcg2_ops,
1123 static struct clk_branch mmss_cxo_clk = {
1126 .enable_reg = 0x5104,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "mmss_cxo_clk",
1130 .parent_names = (const char *[]){ "xo" },
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1138 static struct clk_branch mmss_sleepclk_clk = {
1141 .enable_reg = 0x5100,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "mmss_sleepclk_clk",
1145 .parent_names = (const char *[]){
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1155 static struct clk_branch avsync_ahb_clk = {
1158 .enable_reg = 0x2414,
1159 .enable_mask = BIT(0),
1160 .hw.init = &(struct clk_init_data){
1161 .name = "avsync_ahb_clk",
1162 .parent_names = (const char *[]){
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1172 static struct clk_branch avsync_edppixel_clk = {
1175 .enable_reg = 0x2418,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "avsync_edppixel_clk",
1179 .parent_names = (const char *[]){
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1189 static struct clk_branch avsync_extpclk_clk = {
1192 .enable_reg = 0x2410,
1193 .enable_mask = BIT(0),
1194 .hw.init = &(struct clk_init_data){
1195 .name = "avsync_extpclk_clk",
1196 .parent_names = (const char *[]){
1200 .flags = CLK_SET_RATE_PARENT,
1201 .ops = &clk_branch2_ops,
1206 static struct clk_branch avsync_pclk0_clk = {
1209 .enable_reg = 0x241c,
1210 .enable_mask = BIT(0),
1211 .hw.init = &(struct clk_init_data){
1212 .name = "avsync_pclk0_clk",
1213 .parent_names = (const char *[]){
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_branch2_ops,
1223 static struct clk_branch avsync_pclk1_clk = {
1226 .enable_reg = 0x2420,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "avsync_pclk1_clk",
1230 .parent_names = (const char *[]){
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1240 static struct clk_branch avsync_vp_clk = {
1243 .enable_reg = 0x2404,
1244 .enable_mask = BIT(0),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "avsync_vp_clk",
1247 .parent_names = (const char *[]){
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1257 static struct clk_branch camss_ahb_clk = {
1260 .enable_reg = 0x348c,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "camss_ahb_clk",
1264 .parent_names = (const char *[]){
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_branch2_ops,
1274 static struct clk_branch camss_cci_cci_ahb_clk = {
1277 .enable_reg = 0x3348,
1278 .enable_mask = BIT(0),
1279 .hw.init = &(struct clk_init_data){
1280 .name = "camss_cci_cci_ahb_clk",
1281 .parent_names = (const char *[]){
1285 .ops = &clk_branch2_ops,
1290 static struct clk_branch camss_cci_cci_clk = {
1293 .enable_reg = 0x3344,
1294 .enable_mask = BIT(0),
1295 .hw.init = &(struct clk_init_data){
1296 .name = "camss_cci_cci_clk",
1297 .parent_names = (const char *[]){
1301 .flags = CLK_SET_RATE_PARENT,
1302 .ops = &clk_branch2_ops,
1307 static struct clk_branch camss_csi0_ahb_clk = {
1310 .enable_reg = 0x30bc,
1311 .enable_mask = BIT(0),
1312 .hw.init = &(struct clk_init_data){
1313 .name = "camss_csi0_ahb_clk",
1314 .parent_names = (const char *[]){
1318 .ops = &clk_branch2_ops,
1323 static struct clk_branch camss_csi0_clk = {
1326 .enable_reg = 0x30b4,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "camss_csi0_clk",
1330 .parent_names = (const char *[]){
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1340 static struct clk_branch camss_csi0phy_clk = {
1343 .enable_reg = 0x30c4,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "camss_csi0phy_clk",
1347 .parent_names = (const char *[]){
1351 .flags = CLK_SET_RATE_PARENT,
1352 .ops = &clk_branch2_ops,
1357 static struct clk_branch camss_csi0pix_clk = {
1360 .enable_reg = 0x30e4,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "camss_csi0pix_clk",
1364 .parent_names = (const char *[]){
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1374 static struct clk_branch camss_csi0rdi_clk = {
1377 .enable_reg = 0x30d4,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "camss_csi0rdi_clk",
1381 .parent_names = (const char *[]){
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1391 static struct clk_branch camss_csi1_ahb_clk = {
1394 .enable_reg = 0x3128,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "camss_csi1_ahb_clk",
1398 .parent_names = (const char *[]){
1402 .flags = CLK_SET_RATE_PARENT,
1403 .ops = &clk_branch2_ops,
1408 static struct clk_branch camss_csi1_clk = {
1411 .enable_reg = 0x3124,
1412 .enable_mask = BIT(0),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "camss_csi1_clk",
1415 .parent_names = (const char *[]){
1419 .flags = CLK_SET_RATE_PARENT,
1420 .ops = &clk_branch2_ops,
1425 static struct clk_branch camss_csi1phy_clk = {
1428 .enable_reg = 0x3134,
1429 .enable_mask = BIT(0),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "camss_csi1phy_clk",
1432 .parent_names = (const char *[]){
1436 .flags = CLK_SET_RATE_PARENT,
1437 .ops = &clk_branch2_ops,
1442 static struct clk_branch camss_csi1pix_clk = {
1445 .enable_reg = 0x3154,
1446 .enable_mask = BIT(0),
1447 .hw.init = &(struct clk_init_data){
1448 .name = "camss_csi1pix_clk",
1449 .parent_names = (const char *[]){
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1459 static struct clk_branch camss_csi1rdi_clk = {
1462 .enable_reg = 0x3144,
1463 .enable_mask = BIT(0),
1464 .hw.init = &(struct clk_init_data){
1465 .name = "camss_csi1rdi_clk",
1466 .parent_names = (const char *[]){
1470 .flags = CLK_SET_RATE_PARENT,
1471 .ops = &clk_branch2_ops,
1476 static struct clk_branch camss_csi2_ahb_clk = {
1479 .enable_reg = 0x3188,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "camss_csi2_ahb_clk",
1483 .parent_names = (const char *[]){
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch camss_csi2_clk = {
1495 .enable_reg = 0x3184,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "camss_csi2_clk",
1499 .parent_names = (const char *[]){
1503 .flags = CLK_SET_RATE_PARENT,
1504 .ops = &clk_branch2_ops,
1509 static struct clk_branch camss_csi2phy_clk = {
1512 .enable_reg = 0x3194,
1513 .enable_mask = BIT(0),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "camss_csi2phy_clk",
1516 .parent_names = (const char *[]){
1520 .flags = CLK_SET_RATE_PARENT,
1521 .ops = &clk_branch2_ops,
1526 static struct clk_branch camss_csi2pix_clk = {
1529 .enable_reg = 0x31b4,
1530 .enable_mask = BIT(0),
1531 .hw.init = &(struct clk_init_data){
1532 .name = "camss_csi2pix_clk",
1533 .parent_names = (const char *[]){
1537 .flags = CLK_SET_RATE_PARENT,
1538 .ops = &clk_branch2_ops,
1543 static struct clk_branch camss_csi2rdi_clk = {
1546 .enable_reg = 0x31a4,
1547 .enable_mask = BIT(0),
1548 .hw.init = &(struct clk_init_data){
1549 .name = "camss_csi2rdi_clk",
1550 .parent_names = (const char *[]){
1554 .flags = CLK_SET_RATE_PARENT,
1555 .ops = &clk_branch2_ops,
1560 static struct clk_branch camss_csi3_ahb_clk = {
1563 .enable_reg = 0x31e8,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "camss_csi3_ahb_clk",
1567 .parent_names = (const char *[]){
1571 .ops = &clk_branch2_ops,
1576 static struct clk_branch camss_csi3_clk = {
1579 .enable_reg = 0x31e4,
1580 .enable_mask = BIT(0),
1581 .hw.init = &(struct clk_init_data){
1582 .name = "camss_csi3_clk",
1583 .parent_names = (const char *[]){
1587 .flags = CLK_SET_RATE_PARENT,
1588 .ops = &clk_branch2_ops,
1593 static struct clk_branch camss_csi3phy_clk = {
1596 .enable_reg = 0x31f4,
1597 .enable_mask = BIT(0),
1598 .hw.init = &(struct clk_init_data){
1599 .name = "camss_csi3phy_clk",
1600 .parent_names = (const char *[]){
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1610 static struct clk_branch camss_csi3pix_clk = {
1613 .enable_reg = 0x3214,
1614 .enable_mask = BIT(0),
1615 .hw.init = &(struct clk_init_data){
1616 .name = "camss_csi3pix_clk",
1617 .parent_names = (const char *[]){
1621 .flags = CLK_SET_RATE_PARENT,
1622 .ops = &clk_branch2_ops,
1627 static struct clk_branch camss_csi3rdi_clk = {
1630 .enable_reg = 0x3204,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "camss_csi3rdi_clk",
1634 .parent_names = (const char *[]){
1638 .flags = CLK_SET_RATE_PARENT,
1639 .ops = &clk_branch2_ops,
1644 static struct clk_branch camss_csi_vfe0_clk = {
1647 .enable_reg = 0x3704,
1648 .enable_mask = BIT(0),
1649 .hw.init = &(struct clk_init_data){
1650 .name = "camss_csi_vfe0_clk",
1651 .parent_names = (const char *[]){
1655 .flags = CLK_SET_RATE_PARENT,
1656 .ops = &clk_branch2_ops,
1661 static struct clk_branch camss_csi_vfe1_clk = {
1664 .enable_reg = 0x3714,
1665 .enable_mask = BIT(0),
1666 .hw.init = &(struct clk_init_data){
1667 .name = "camss_csi_vfe1_clk",
1668 .parent_names = (const char *[]){
1672 .flags = CLK_SET_RATE_PARENT,
1673 .ops = &clk_branch2_ops,
1678 static struct clk_branch camss_gp0_clk = {
1681 .enable_reg = 0x3444,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "camss_gp0_clk",
1685 .parent_names = (const char *[]){
1686 "camss_gp0_clk_src",
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1695 static struct clk_branch camss_gp1_clk = {
1698 .enable_reg = 0x3474,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "camss_gp1_clk",
1702 .parent_names = (const char *[]){
1703 "camss_gp1_clk_src",
1706 .flags = CLK_SET_RATE_PARENT,
1707 .ops = &clk_branch2_ops,
1712 static struct clk_branch camss_ispif_ahb_clk = {
1715 .enable_reg = 0x3224,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(struct clk_init_data){
1718 .name = "camss_ispif_ahb_clk",
1719 .parent_names = (const char *[]){
1723 .flags = CLK_SET_RATE_PARENT,
1724 .ops = &clk_branch2_ops,
1729 static struct clk_branch camss_jpeg_jpeg0_clk = {
1732 .enable_reg = 0x35a8,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data){
1735 .name = "camss_jpeg_jpeg0_clk",
1736 .parent_names = (const char *[]){
1740 .flags = CLK_SET_RATE_PARENT,
1741 .ops = &clk_branch2_ops,
1746 static struct clk_branch camss_jpeg_jpeg1_clk = {
1749 .enable_reg = 0x35ac,
1750 .enable_mask = BIT(0),
1751 .hw.init = &(struct clk_init_data){
1752 .name = "camss_jpeg_jpeg1_clk",
1753 .parent_names = (const char *[]){
1757 .flags = CLK_SET_RATE_PARENT,
1758 .ops = &clk_branch2_ops,
1763 static struct clk_branch camss_jpeg_jpeg2_clk = {
1766 .enable_reg = 0x35b0,
1767 .enable_mask = BIT(0),
1768 .hw.init = &(struct clk_init_data){
1769 .name = "camss_jpeg_jpeg2_clk",
1770 .parent_names = (const char *[]){
1774 .flags = CLK_SET_RATE_PARENT,
1775 .ops = &clk_branch2_ops,
1780 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1783 .enable_reg = 0x35b4,
1784 .enable_mask = BIT(0),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "camss_jpeg_jpeg_ahb_clk",
1787 .parent_names = (const char *[]){
1791 .ops = &clk_branch2_ops,
1796 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1799 .enable_reg = 0x35b8,
1800 .enable_mask = BIT(0),
1801 .hw.init = &(struct clk_init_data){
1802 .name = "camss_jpeg_jpeg_axi_clk",
1803 .parent_names = (const char *[]){
1807 .ops = &clk_branch2_ops,
1812 static struct clk_branch camss_mclk0_clk = {
1815 .enable_reg = 0x3384,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "camss_mclk0_clk",
1819 .parent_names = (const char *[]){
1823 .flags = CLK_SET_RATE_PARENT,
1824 .ops = &clk_branch2_ops,
1829 static struct clk_branch camss_mclk1_clk = {
1832 .enable_reg = 0x33b4,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "camss_mclk1_clk",
1836 .parent_names = (const char *[]){
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1846 static struct clk_branch camss_mclk2_clk = {
1849 .enable_reg = 0x33e4,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "camss_mclk2_clk",
1853 .parent_names = (const char *[]){
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1863 static struct clk_branch camss_mclk3_clk = {
1866 .enable_reg = 0x3414,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "camss_mclk3_clk",
1870 .parent_names = (const char *[]){
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1880 static struct clk_branch camss_micro_ahb_clk = {
1883 .enable_reg = 0x3494,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "camss_micro_ahb_clk",
1887 .parent_names = (const char *[]){
1891 .ops = &clk_branch2_ops,
1896 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1899 .enable_reg = 0x3024,
1900 .enable_mask = BIT(0),
1901 .hw.init = &(struct clk_init_data){
1902 .name = "camss_phy0_csi0phytimer_clk",
1903 .parent_names = (const char *[]){
1904 "csi0phytimer_clk_src",
1907 .flags = CLK_SET_RATE_PARENT,
1908 .ops = &clk_branch2_ops,
1913 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1916 .enable_reg = 0x3054,
1917 .enable_mask = BIT(0),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "camss_phy1_csi1phytimer_clk",
1920 .parent_names = (const char *[]){
1921 "csi1phytimer_clk_src",
1924 .flags = CLK_SET_RATE_PARENT,
1925 .ops = &clk_branch2_ops,
1930 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1933 .enable_reg = 0x3084,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(struct clk_init_data){
1936 .name = "camss_phy2_csi2phytimer_clk",
1937 .parent_names = (const char *[]){
1938 "csi2phytimer_clk_src",
1941 .flags = CLK_SET_RATE_PARENT,
1942 .ops = &clk_branch2_ops,
1947 static struct clk_branch camss_top_ahb_clk = {
1950 .enable_reg = 0x3484,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "camss_top_ahb_clk",
1954 .parent_names = (const char *[]){
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1964 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1967 .enable_reg = 0x36b4,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(struct clk_init_data){
1970 .name = "camss_vfe_cpp_ahb_clk",
1971 .parent_names = (const char *[]){
1975 .flags = CLK_SET_RATE_PARENT,
1976 .ops = &clk_branch2_ops,
1981 static struct clk_branch camss_vfe_cpp_clk = {
1984 .enable_reg = 0x36b0,
1985 .enable_mask = BIT(0),
1986 .hw.init = &(struct clk_init_data){
1987 .name = "camss_vfe_cpp_clk",
1988 .parent_names = (const char *[]){
1992 .flags = CLK_SET_RATE_PARENT,
1993 .ops = &clk_branch2_ops,
1998 static struct clk_branch camss_vfe_vfe0_clk = {
2001 .enable_reg = 0x36a8,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "camss_vfe_vfe0_clk",
2005 .parent_names = (const char *[]){
2009 .flags = CLK_SET_RATE_PARENT,
2010 .ops = &clk_branch2_ops,
2015 static struct clk_branch camss_vfe_vfe1_clk = {
2018 .enable_reg = 0x36ac,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "camss_vfe_vfe1_clk",
2022 .parent_names = (const char *[]){
2026 .flags = CLK_SET_RATE_PARENT,
2027 .ops = &clk_branch2_ops,
2032 static struct clk_branch camss_vfe_vfe_ahb_clk = {
2035 .enable_reg = 0x36b8,
2036 .enable_mask = BIT(0),
2037 .hw.init = &(struct clk_init_data){
2038 .name = "camss_vfe_vfe_ahb_clk",
2039 .parent_names = (const char *[]){
2043 .flags = CLK_SET_RATE_PARENT,
2044 .ops = &clk_branch2_ops,
2049 static struct clk_branch camss_vfe_vfe_axi_clk = {
2052 .enable_reg = 0x36bc,
2053 .enable_mask = BIT(0),
2054 .hw.init = &(struct clk_init_data){
2055 .name = "camss_vfe_vfe_axi_clk",
2056 .parent_names = (const char *[]){
2060 .flags = CLK_SET_RATE_PARENT,
2061 .ops = &clk_branch2_ops,
2066 static struct clk_branch mdss_ahb_clk = {
2069 .enable_reg = 0x2308,
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "mdss_ahb_clk",
2073 .parent_names = (const char *[]){
2077 .flags = CLK_SET_RATE_PARENT,
2078 .ops = &clk_branch2_ops,
2083 static struct clk_branch mdss_axi_clk = {
2086 .enable_reg = 0x2310,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "mdss_axi_clk",
2090 .parent_names = (const char *[]){
2094 .flags = CLK_SET_RATE_PARENT,
2095 .ops = &clk_branch2_ops,
2100 static struct clk_branch mdss_byte0_clk = {
2103 .enable_reg = 0x233c,
2104 .enable_mask = BIT(0),
2105 .hw.init = &(struct clk_init_data){
2106 .name = "mdss_byte0_clk",
2107 .parent_names = (const char *[]){
2111 .flags = CLK_SET_RATE_PARENT,
2112 .ops = &clk_branch2_ops,
2117 static struct clk_branch mdss_byte1_clk = {
2120 .enable_reg = 0x2340,
2121 .enable_mask = BIT(0),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "mdss_byte1_clk",
2124 .parent_names = (const char *[]){
2128 .flags = CLK_SET_RATE_PARENT,
2129 .ops = &clk_branch2_ops,
2134 static struct clk_branch mdss_edpaux_clk = {
2137 .enable_reg = 0x2334,
2138 .enable_mask = BIT(0),
2139 .hw.init = &(struct clk_init_data){
2140 .name = "mdss_edpaux_clk",
2141 .parent_names = (const char *[]){
2145 .flags = CLK_SET_RATE_PARENT,
2146 .ops = &clk_branch2_ops,
2151 static struct clk_branch mdss_edplink_clk = {
2154 .enable_reg = 0x2330,
2155 .enable_mask = BIT(0),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "mdss_edplink_clk",
2158 .parent_names = (const char *[]){
2162 .flags = CLK_SET_RATE_PARENT,
2163 .ops = &clk_branch2_ops,
2168 static struct clk_branch mdss_edppixel_clk = {
2171 .enable_reg = 0x232c,
2172 .enable_mask = BIT(0),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "mdss_edppixel_clk",
2175 .parent_names = (const char *[]){
2179 .flags = CLK_SET_RATE_PARENT,
2180 .ops = &clk_branch2_ops,
2185 static struct clk_branch mdss_esc0_clk = {
2188 .enable_reg = 0x2344,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "mdss_esc0_clk",
2192 .parent_names = (const char *[]){
2196 .flags = CLK_SET_RATE_PARENT,
2197 .ops = &clk_branch2_ops,
2202 static struct clk_branch mdss_esc1_clk = {
2205 .enable_reg = 0x2348,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "mdss_esc1_clk",
2209 .parent_names = (const char *[]){
2213 .flags = CLK_SET_RATE_PARENT,
2214 .ops = &clk_branch2_ops,
2219 static struct clk_branch mdss_extpclk_clk = {
2222 .enable_reg = 0x2324,
2223 .enable_mask = BIT(0),
2224 .hw.init = &(struct clk_init_data){
2225 .name = "mdss_extpclk_clk",
2226 .parent_names = (const char *[]){
2230 .flags = CLK_SET_RATE_PARENT,
2231 .ops = &clk_branch2_ops,
2236 static struct clk_branch mdss_hdmi_ahb_clk = {
2239 .enable_reg = 0x230c,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "mdss_hdmi_ahb_clk",
2243 .parent_names = (const char *[]){
2247 .flags = CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2253 static struct clk_branch mdss_hdmi_clk = {
2256 .enable_reg = 0x2338,
2257 .enable_mask = BIT(0),
2258 .hw.init = &(struct clk_init_data){
2259 .name = "mdss_hdmi_clk",
2260 .parent_names = (const char *[]){
2264 .flags = CLK_SET_RATE_PARENT,
2265 .ops = &clk_branch2_ops,
2270 static struct clk_branch mdss_mdp_clk = {
2273 .enable_reg = 0x231c,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "mdss_mdp_clk",
2277 .parent_names = (const char *[]){
2281 .flags = CLK_SET_RATE_PARENT,
2282 .ops = &clk_branch2_ops,
2287 static struct clk_branch mdss_mdp_lut_clk = {
2290 .enable_reg = 0x2320,
2291 .enable_mask = BIT(0),
2292 .hw.init = &(struct clk_init_data){
2293 .name = "mdss_mdp_lut_clk",
2294 .parent_names = (const char *[]){
2298 .flags = CLK_SET_RATE_PARENT,
2299 .ops = &clk_branch2_ops,
2304 static struct clk_branch mdss_pclk0_clk = {
2307 .enable_reg = 0x2314,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "mdss_pclk0_clk",
2311 .parent_names = (const char *[]){
2315 .flags = CLK_SET_RATE_PARENT,
2316 .ops = &clk_branch2_ops,
2321 static struct clk_branch mdss_pclk1_clk = {
2324 .enable_reg = 0x2318,
2325 .enable_mask = BIT(0),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "mdss_pclk1_clk",
2328 .parent_names = (const char *[]){
2332 .flags = CLK_SET_RATE_PARENT,
2333 .ops = &clk_branch2_ops,
2338 static struct clk_branch mdss_vsync_clk = {
2341 .enable_reg = 0x2328,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "mdss_vsync_clk",
2345 .parent_names = (const char *[]){
2349 .flags = CLK_SET_RATE_PARENT,
2350 .ops = &clk_branch2_ops,
2355 static struct clk_branch mmss_rbcpr_ahb_clk = {
2358 .enable_reg = 0x4088,
2359 .enable_mask = BIT(0),
2360 .hw.init = &(struct clk_init_data){
2361 .name = "mmss_rbcpr_ahb_clk",
2362 .parent_names = (const char *[]){
2366 .flags = CLK_SET_RATE_PARENT,
2367 .ops = &clk_branch2_ops,
2372 static struct clk_branch mmss_rbcpr_clk = {
2375 .enable_reg = 0x4084,
2376 .enable_mask = BIT(0),
2377 .hw.init = &(struct clk_init_data){
2378 .name = "mmss_rbcpr_clk",
2379 .parent_names = (const char *[]){
2383 .flags = CLK_SET_RATE_PARENT,
2384 .ops = &clk_branch2_ops,
2389 static struct clk_branch mmss_spdm_ahb_clk = {
2392 .enable_reg = 0x0230,
2393 .enable_mask = BIT(0),
2394 .hw.init = &(struct clk_init_data){
2395 .name = "mmss_spdm_ahb_clk",
2396 .parent_names = (const char *[]){
2397 "mmss_spdm_ahb_div_clk",
2400 .flags = CLK_SET_RATE_PARENT,
2401 .ops = &clk_branch2_ops,
2406 static struct clk_branch mmss_spdm_axi_clk = {
2409 .enable_reg = 0x0210,
2410 .enable_mask = BIT(0),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "mmss_spdm_axi_clk",
2413 .parent_names = (const char *[]){
2414 "mmss_spdm_axi_div_clk",
2417 .flags = CLK_SET_RATE_PARENT,
2418 .ops = &clk_branch2_ops,
2423 static struct clk_branch mmss_spdm_csi0_clk = {
2426 .enable_reg = 0x023c,
2427 .enable_mask = BIT(0),
2428 .hw.init = &(struct clk_init_data){
2429 .name = "mmss_spdm_csi0_clk",
2430 .parent_names = (const char *[]){
2431 "mmss_spdm_csi0_div_clk",
2434 .flags = CLK_SET_RATE_PARENT,
2435 .ops = &clk_branch2_ops,
2440 static struct clk_branch mmss_spdm_gfx3d_clk = {
2443 .enable_reg = 0x022c,
2444 .enable_mask = BIT(0),
2445 .hw.init = &(struct clk_init_data){
2446 .name = "mmss_spdm_gfx3d_clk",
2447 .parent_names = (const char *[]){
2448 "mmss_spdm_gfx3d_div_clk",
2451 .flags = CLK_SET_RATE_PARENT,
2452 .ops = &clk_branch2_ops,
2457 static struct clk_branch mmss_spdm_jpeg0_clk = {
2460 .enable_reg = 0x0204,
2461 .enable_mask = BIT(0),
2462 .hw.init = &(struct clk_init_data){
2463 .name = "mmss_spdm_jpeg0_clk",
2464 .parent_names = (const char *[]){
2465 "mmss_spdm_jpeg0_div_clk",
2468 .flags = CLK_SET_RATE_PARENT,
2469 .ops = &clk_branch2_ops,
2474 static struct clk_branch mmss_spdm_jpeg1_clk = {
2477 .enable_reg = 0x0208,
2478 .enable_mask = BIT(0),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "mmss_spdm_jpeg1_clk",
2481 .parent_names = (const char *[]){
2482 "mmss_spdm_jpeg1_div_clk",
2485 .flags = CLK_SET_RATE_PARENT,
2486 .ops = &clk_branch2_ops,
2491 static struct clk_branch mmss_spdm_jpeg2_clk = {
2494 .enable_reg = 0x0224,
2495 .enable_mask = BIT(0),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "mmss_spdm_jpeg2_clk",
2498 .parent_names = (const char *[]){
2499 "mmss_spdm_jpeg2_div_clk",
2502 .flags = CLK_SET_RATE_PARENT,
2503 .ops = &clk_branch2_ops,
2508 static struct clk_branch mmss_spdm_mdp_clk = {
2511 .enable_reg = 0x020c,
2512 .enable_mask = BIT(0),
2513 .hw.init = &(struct clk_init_data){
2514 .name = "mmss_spdm_mdp_clk",
2515 .parent_names = (const char *[]){
2516 "mmss_spdm_mdp_div_clk",
2519 .flags = CLK_SET_RATE_PARENT,
2520 .ops = &clk_branch2_ops,
2525 static struct clk_branch mmss_spdm_pclk0_clk = {
2528 .enable_reg = 0x0234,
2529 .enable_mask = BIT(0),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "mmss_spdm_pclk0_clk",
2532 .parent_names = (const char *[]){
2533 "mmss_spdm_pclk0_div_clk",
2536 .flags = CLK_SET_RATE_PARENT,
2537 .ops = &clk_branch2_ops,
2542 static struct clk_branch mmss_spdm_pclk1_clk = {
2545 .enable_reg = 0x0228,
2546 .enable_mask = BIT(0),
2547 .hw.init = &(struct clk_init_data){
2548 .name = "mmss_spdm_pclk1_clk",
2549 .parent_names = (const char *[]){
2550 "mmss_spdm_pclk1_div_clk",
2553 .flags = CLK_SET_RATE_PARENT,
2554 .ops = &clk_branch2_ops,
2559 static struct clk_branch mmss_spdm_vcodec0_clk = {
2562 .enable_reg = 0x0214,
2563 .enable_mask = BIT(0),
2564 .hw.init = &(struct clk_init_data){
2565 .name = "mmss_spdm_vcodec0_clk",
2566 .parent_names = (const char *[]){
2567 "mmss_spdm_vcodec0_div_clk",
2570 .flags = CLK_SET_RATE_PARENT,
2571 .ops = &clk_branch2_ops,
2576 static struct clk_branch mmss_spdm_vfe0_clk = {
2579 .enable_reg = 0x0218,
2580 .enable_mask = BIT(0),
2581 .hw.init = &(struct clk_init_data){
2582 .name = "mmss_spdm_vfe0_clk",
2583 .parent_names = (const char *[]){
2584 "mmss_spdm_vfe0_div_clk",
2587 .flags = CLK_SET_RATE_PARENT,
2588 .ops = &clk_branch2_ops,
2593 static struct clk_branch mmss_spdm_vfe1_clk = {
2596 .enable_reg = 0x021c,
2597 .enable_mask = BIT(0),
2598 .hw.init = &(struct clk_init_data){
2599 .name = "mmss_spdm_vfe1_clk",
2600 .parent_names = (const char *[]){
2601 "mmss_spdm_vfe1_div_clk",
2604 .flags = CLK_SET_RATE_PARENT,
2605 .ops = &clk_branch2_ops,
2610 static struct clk_branch mmss_spdm_rm_axi_clk = {
2613 .enable_reg = 0x0304,
2614 .enable_mask = BIT(0),
2615 .hw.init = &(struct clk_init_data){
2616 .name = "mmss_spdm_rm_axi_clk",
2617 .parent_names = (const char *[]){
2621 .flags = CLK_SET_RATE_PARENT,
2622 .ops = &clk_branch2_ops,
2627 static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2630 .enable_reg = 0x0308,
2631 .enable_mask = BIT(0),
2632 .hw.init = &(struct clk_init_data){
2633 .name = "mmss_spdm_rm_ocmemnoc_clk",
2634 .parent_names = (const char *[]){
2638 .flags = CLK_SET_RATE_PARENT,
2639 .ops = &clk_branch2_ops,
2645 static struct clk_branch mmss_misc_ahb_clk = {
2648 .enable_reg = 0x502c,
2649 .enable_mask = BIT(0),
2650 .hw.init = &(struct clk_init_data){
2651 .name = "mmss_misc_ahb_clk",
2652 .parent_names = (const char *[]){
2656 .flags = CLK_SET_RATE_PARENT,
2657 .ops = &clk_branch2_ops,
2662 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2665 .enable_reg = 0x5024,
2666 .enable_mask = BIT(0),
2667 .hw.init = &(struct clk_init_data){
2668 .name = "mmss_mmssnoc_ahb_clk",
2669 .parent_names = (const char *[]){
2673 .ops = &clk_branch2_ops,
2674 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2679 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2682 .enable_reg = 0x5028,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "mmss_mmssnoc_bto_ahb_clk",
2686 .parent_names = (const char *[]){
2690 .ops = &clk_branch2_ops,
2691 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2696 static struct clk_branch mmss_mmssnoc_axi_clk = {
2699 .enable_reg = 0x506c,
2700 .enable_mask = BIT(0),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "mmss_mmssnoc_axi_clk",
2703 .parent_names = (const char *[]){
2707 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2708 .ops = &clk_branch2_ops,
2713 static struct clk_branch mmss_s0_axi_clk = {
2716 .enable_reg = 0x5064,
2717 .enable_mask = BIT(0),
2718 .hw.init = &(struct clk_init_data){
2719 .name = "mmss_s0_axi_clk",
2720 .parent_names = (const char *[]){
2724 .ops = &clk_branch2_ops,
2725 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2730 static struct clk_branch ocmemcx_ahb_clk = {
2733 .enable_reg = 0x405c,
2734 .enable_mask = BIT(0),
2735 .hw.init = &(struct clk_init_data){
2736 .name = "ocmemcx_ahb_clk",
2737 .parent_names = (const char *[]){
2741 .flags = CLK_SET_RATE_PARENT,
2742 .ops = &clk_branch2_ops,
2747 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2750 .enable_reg = 0x4058,
2751 .enable_mask = BIT(0),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "ocmemcx_ocmemnoc_clk",
2754 .parent_names = (const char *[]){
2758 .flags = CLK_SET_RATE_PARENT,
2759 .ops = &clk_branch2_ops,
2764 static struct clk_branch oxili_ocmemgx_clk = {
2767 .enable_reg = 0x402c,
2768 .enable_mask = BIT(0),
2769 .hw.init = &(struct clk_init_data){
2770 .name = "oxili_ocmemgx_clk",
2771 .parent_names = (const char *[]){
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2781 static struct clk_branch oxili_gfx3d_clk = {
2784 .enable_reg = 0x4028,
2785 .enable_mask = BIT(0),
2786 .hw.init = &(struct clk_init_data){
2787 .name = "oxili_gfx3d_clk",
2788 .parent_names = (const char *[]){
2792 .flags = CLK_SET_RATE_PARENT,
2793 .ops = &clk_branch2_ops,
2798 static struct clk_branch oxili_rbbmtimer_clk = {
2801 .enable_reg = 0x40b0,
2802 .enable_mask = BIT(0),
2803 .hw.init = &(struct clk_init_data){
2804 .name = "oxili_rbbmtimer_clk",
2805 .parent_names = (const char *[]){
2806 "rbbmtimer_clk_src",
2809 .flags = CLK_SET_RATE_PARENT,
2810 .ops = &clk_branch2_ops,
2815 static struct clk_branch oxilicx_ahb_clk = {
2818 .enable_reg = 0x403c,
2819 .enable_mask = BIT(0),
2820 .hw.init = &(struct clk_init_data){
2821 .name = "oxilicx_ahb_clk",
2822 .parent_names = (const char *[]){
2826 .flags = CLK_SET_RATE_PARENT,
2827 .ops = &clk_branch2_ops,
2832 static struct clk_branch venus0_ahb_clk = {
2835 .enable_reg = 0x1030,
2836 .enable_mask = BIT(0),
2837 .hw.init = &(struct clk_init_data){
2838 .name = "venus0_ahb_clk",
2839 .parent_names = (const char *[]){
2843 .flags = CLK_SET_RATE_PARENT,
2844 .ops = &clk_branch2_ops,
2849 static struct clk_branch venus0_axi_clk = {
2852 .enable_reg = 0x1034,
2853 .enable_mask = BIT(0),
2854 .hw.init = &(struct clk_init_data){
2855 .name = "venus0_axi_clk",
2856 .parent_names = (const char *[]){
2860 .flags = CLK_SET_RATE_PARENT,
2861 .ops = &clk_branch2_ops,
2866 static struct clk_branch venus0_core0_vcodec_clk = {
2869 .enable_reg = 0x1048,
2870 .enable_mask = BIT(0),
2871 .hw.init = &(struct clk_init_data){
2872 .name = "venus0_core0_vcodec_clk",
2873 .parent_names = (const char *[]){
2877 .flags = CLK_SET_RATE_PARENT,
2878 .ops = &clk_branch2_ops,
2883 static struct clk_branch venus0_core1_vcodec_clk = {
2886 .enable_reg = 0x104c,
2887 .enable_mask = BIT(0),
2888 .hw.init = &(struct clk_init_data){
2889 .name = "venus0_core1_vcodec_clk",
2890 .parent_names = (const char *[]){
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2900 static struct clk_branch venus0_ocmemnoc_clk = {
2903 .enable_reg = 0x1038,
2904 .enable_mask = BIT(0),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "venus0_ocmemnoc_clk",
2907 .parent_names = (const char *[]){
2911 .flags = CLK_SET_RATE_PARENT,
2912 .ops = &clk_branch2_ops,
2917 static struct clk_branch venus0_vcodec0_clk = {
2920 .enable_reg = 0x1028,
2921 .enable_mask = BIT(0),
2922 .hw.init = &(struct clk_init_data){
2923 .name = "venus0_vcodec0_clk",
2924 .parent_names = (const char *[]){
2928 .flags = CLK_SET_RATE_PARENT,
2929 .ops = &clk_branch2_ops,
2934 static struct clk_branch vpu_ahb_clk = {
2937 .enable_reg = 0x1430,
2938 .enable_mask = BIT(0),
2939 .hw.init = &(struct clk_init_data){
2940 .name = "vpu_ahb_clk",
2941 .parent_names = (const char *[]){
2945 .flags = CLK_SET_RATE_PARENT,
2946 .ops = &clk_branch2_ops,
2951 static struct clk_branch vpu_axi_clk = {
2954 .enable_reg = 0x143c,
2955 .enable_mask = BIT(0),
2956 .hw.init = &(struct clk_init_data){
2957 .name = "vpu_axi_clk",
2958 .parent_names = (const char *[]){
2962 .flags = CLK_SET_RATE_PARENT,
2963 .ops = &clk_branch2_ops,
2968 static struct clk_branch vpu_bus_clk = {
2971 .enable_reg = 0x1440,
2972 .enable_mask = BIT(0),
2973 .hw.init = &(struct clk_init_data){
2974 .name = "vpu_bus_clk",
2975 .parent_names = (const char *[]){
2979 .flags = CLK_SET_RATE_PARENT,
2980 .ops = &clk_branch2_ops,
2985 static struct clk_branch vpu_cxo_clk = {
2988 .enable_reg = 0x1434,
2989 .enable_mask = BIT(0),
2990 .hw.init = &(struct clk_init_data){
2991 .name = "vpu_cxo_clk",
2992 .parent_names = (const char *[]){ "xo" },
2994 .flags = CLK_SET_RATE_PARENT,
2995 .ops = &clk_branch2_ops,
3000 static struct clk_branch vpu_maple_clk = {
3003 .enable_reg = 0x142c,
3004 .enable_mask = BIT(0),
3005 .hw.init = &(struct clk_init_data){
3006 .name = "vpu_maple_clk",
3007 .parent_names = (const char *[]){
3011 .flags = CLK_SET_RATE_PARENT,
3012 .ops = &clk_branch2_ops,
3017 static struct clk_branch vpu_sleep_clk = {
3020 .enable_reg = 0x1438,
3021 .enable_mask = BIT(0),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "vpu_sleep_clk",
3024 .parent_names = (const char *[]){
3028 .flags = CLK_SET_RATE_PARENT,
3029 .ops = &clk_branch2_ops,
3034 static struct clk_branch vpu_vdp_clk = {
3037 .enable_reg = 0x1428,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "vpu_vdp_clk",
3041 .parent_names = (const char *[]){
3045 .flags = CLK_SET_RATE_PARENT,
3046 .ops = &clk_branch2_ops,
3051 static const struct pll_config mmpll1_config = {
3056 .vco_mask = 0x3 << 20,
3058 .pre_div_mask = 0x7 << 12,
3059 .post_div_val = 0x0,
3060 .post_div_mask = 0x3 << 8,
3061 .mn_ena_mask = BIT(24),
3062 .main_output_mask = BIT(0),
3065 static const struct pll_config mmpll3_config = {
3070 .vco_mask = 0x3 << 20,
3072 .pre_div_mask = 0x7 << 12,
3073 .post_div_val = 0x0,
3074 .post_div_mask = 0x3 << 8,
3075 .mn_ena_mask = BIT(24),
3076 .main_output_mask = BIT(0),
3077 .aux_output_mask = BIT(1),
3080 static struct clk_regmap *mmcc_apq8084_clocks[] = {
3081 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3082 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3083 [MMPLL0] = &mmpll0.clkr,
3084 [MMPLL0_VOTE] = &mmpll0_vote,
3085 [MMPLL1] = &mmpll1.clkr,
3086 [MMPLL1_VOTE] = &mmpll1_vote,
3087 [MMPLL2] = &mmpll2.clkr,
3088 [MMPLL3] = &mmpll3.clkr,
3089 [MMPLL4] = &mmpll4.clkr,
3090 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3091 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3092 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3093 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3094 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3095 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3096 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3097 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3098 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3099 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3100 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3101 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3102 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3103 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3104 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3105 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3106 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3107 [VP_CLK_SRC] = &vp_clk_src.clkr,
3108 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3109 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3110 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3111 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3112 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3113 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3114 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3115 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3116 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3117 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3118 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3119 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3120 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3121 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3122 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3123 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3124 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3125 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3126 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3127 [MMSS_RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3128 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3129 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3130 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3131 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3132 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3133 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3134 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3135 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3136 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3137 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3138 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3139 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3140 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3141 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3142 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3143 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3144 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3145 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3146 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3147 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3148 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3149 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3150 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3151 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3152 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3153 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3154 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3155 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3156 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3157 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3158 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3159 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3160 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3161 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3162 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3163 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3164 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3165 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3166 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3167 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3168 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3169 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3170 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3171 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3172 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3173 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3174 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3175 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3176 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3177 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3178 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3179 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3180 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3181 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3182 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3183 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3184 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3185 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3186 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3187 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3188 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3189 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3190 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3191 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3192 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3193 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3194 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3195 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3196 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3197 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3198 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3199 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3200 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3201 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3202 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3203 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3204 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3205 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3206 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3207 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3208 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3209 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3210 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3211 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3212 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3213 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3214 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3215 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3216 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3217 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3218 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3219 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3220 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3221 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3222 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3223 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3224 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3225 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3226 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3227 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3228 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3229 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3230 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3231 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3232 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3233 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3234 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3235 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3236 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3237 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3238 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3239 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3240 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3241 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3242 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3243 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3244 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3245 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3248 static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3249 [MMSS_SPDM_RESET] = { 0x0200 },
3250 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3251 [VENUS0_RESET] = { 0x1020 },
3252 [VPU_RESET] = { 0x1400 },
3253 [MDSS_RESET] = { 0x2300 },
3254 [AVSYNC_RESET] = { 0x2400 },
3255 [CAMSS_PHY0_RESET] = { 0x3020 },
3256 [CAMSS_PHY1_RESET] = { 0x3050 },
3257 [CAMSS_PHY2_RESET] = { 0x3080 },
3258 [CAMSS_CSI0_RESET] = { 0x30b0 },
3259 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3260 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3261 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3262 [CAMSS_CSI1_RESET] = { 0x3120 },
3263 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3264 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3265 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3266 [CAMSS_CSI2_RESET] = { 0x3180 },
3267 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3268 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3269 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3270 [CAMSS_CSI3_RESET] = { 0x31e0 },
3271 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3272 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3273 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3274 [CAMSS_ISPIF_RESET] = { 0x3220 },
3275 [CAMSS_CCI_RESET] = { 0x3340 },
3276 [CAMSS_MCLK0_RESET] = { 0x3380 },
3277 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3278 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3279 [CAMSS_MCLK3_RESET] = { 0x3410 },
3280 [CAMSS_GP0_RESET] = { 0x3440 },
3281 [CAMSS_GP1_RESET] = { 0x3470 },
3282 [CAMSS_TOP_RESET] = { 0x3480 },
3283 [CAMSS_AHB_RESET] = { 0x3488 },
3284 [CAMSS_MICRO_RESET] = { 0x3490 },
3285 [CAMSS_JPEG_RESET] = { 0x35a0 },
3286 [CAMSS_VFE_RESET] = { 0x36a0 },
3287 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3288 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3289 [OXILI_RESET] = { 0x4020 },
3290 [OXILICX_RESET] = { 0x4030 },
3291 [OCMEMCX_RESET] = { 0x4050 },
3292 [MMSS_RBCRP_RESET] = { 0x4080 },
3293 [MMSSNOCAHB_RESET] = { 0x5020 },
3294 [MMSSNOCAXI_RESET] = { 0x5060 },
3297 static const struct regmap_config mmcc_apq8084_regmap_config = {
3301 .max_register = 0x5104,
3305 static const struct qcom_cc_desc mmcc_apq8084_desc = {
3306 .config = &mmcc_apq8084_regmap_config,
3307 .clks = mmcc_apq8084_clocks,
3308 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3309 .resets = mmcc_apq8084_resets,
3310 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3313 static const struct of_device_id mmcc_apq8084_match_table[] = {
3314 { .compatible = "qcom,mmcc-apq8084" },
3317 MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3319 static int mmcc_apq8084_probe(struct platform_device *pdev)
3322 struct regmap *regmap;
3324 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3328 regmap = dev_get_regmap(&pdev->dev, NULL);
3329 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3330 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3335 static int mmcc_apq8084_remove(struct platform_device *pdev)
3337 qcom_cc_remove(pdev);
3341 static struct platform_driver mmcc_apq8084_driver = {
3342 .probe = mmcc_apq8084_probe,
3343 .remove = mmcc_apq8084_remove,
3345 .name = "mmcc-apq8084",
3346 .of_match_table = mmcc_apq8084_match_table,
3349 module_platform_driver(mmcc_apq8084_driver);
3351 MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3352 MODULE_LICENSE("GPL v2");
3353 MODULE_ALIAS("platform:mmcc-apq8084");