2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
24 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
27 #include "clk-regmap.h"
30 #include "clk-branch.h"
31 #include "clk-regmap-divider.h"
32 #include "clk-regmap-mux.h"
34 static struct clk_pll pll4 = {
42 .clkr.hw.init = &(struct clk_init_data){
44 .parent_names = (const char *[]){ "pxo" },
50 static const struct pll_config pll4_config = {
55 .vco_mask = BIT(17) | BIT(16),
57 .pre_div_mask = BIT(19),
59 .post_div_mask = BIT(21) | BIT(20),
60 .mn_ena_mask = BIT(22),
61 .main_output_mask = BIT(23),
67 static const u8 lcc_pxo_pll4_map[] = {
72 static const char *lcc_pxo_pll4[] = {
77 static struct freq_tbl clk_tbl_aif_mi2s[] = {
78 { 1024000, P_PLL4, 4, 1, 96 },
79 { 1411200, P_PLL4, 4, 2, 139 },
80 { 1536000, P_PLL4, 4, 1, 64 },
81 { 2048000, P_PLL4, 4, 1, 48 },
82 { 2116800, P_PLL4, 4, 2, 93 },
83 { 2304000, P_PLL4, 4, 2, 85 },
84 { 2822400, P_PLL4, 4, 6, 209 },
85 { 3072000, P_PLL4, 4, 1, 32 },
86 { 3175200, P_PLL4, 4, 1, 31 },
87 { 4096000, P_PLL4, 4, 1, 24 },
88 { 4233600, P_PLL4, 4, 9, 209 },
89 { 4608000, P_PLL4, 4, 3, 64 },
90 { 5644800, P_PLL4, 4, 12, 209 },
91 { 6144000, P_PLL4, 4, 1, 16 },
92 { 6350400, P_PLL4, 4, 2, 31 },
93 { 8192000, P_PLL4, 4, 1, 12 },
94 { 8467200, P_PLL4, 4, 18, 209 },
95 { 9216000, P_PLL4, 4, 3, 32 },
96 { 11289600, P_PLL4, 4, 24, 209 },
97 { 12288000, P_PLL4, 4, 1, 8 },
98 { 12700800, P_PLL4, 4, 27, 209 },
99 { 13824000, P_PLL4, 4, 9, 64 },
100 { 16384000, P_PLL4, 4, 1, 6 },
101 { 16934400, P_PLL4, 4, 41, 238 },
102 { 18432000, P_PLL4, 4, 3, 16 },
103 { 22579200, P_PLL4, 2, 24, 209 },
104 { 24576000, P_PLL4, 4, 1, 4 },
105 { 27648000, P_PLL4, 4, 9, 32 },
106 { 33868800, P_PLL4, 4, 41, 119 },
107 { 36864000, P_PLL4, 4, 3, 8 },
108 { 45158400, P_PLL4, 1, 24, 209 },
109 { 49152000, P_PLL4, 4, 1, 2 },
110 { 50803200, P_PLL4, 1, 27, 209 },
114 static struct clk_rcg mi2s_osr_src = {
119 .mnctr_reset_bit = 7,
120 .mnctr_mode_shift = 5,
131 .parent_map = lcc_pxo_pll4_map,
133 .freq_tbl = clk_tbl_aif_mi2s,
136 .enable_mask = BIT(9),
137 .hw.init = &(struct clk_init_data){
138 .name = "mi2s_osr_src",
139 .parent_names = lcc_pxo_pll4,
142 .flags = CLK_SET_RATE_GATE,
147 static const char *lcc_mi2s_parents[] = {
151 static struct clk_branch mi2s_osr_clk = {
154 .halt_check = BRANCH_HALT_ENABLE,
157 .enable_mask = BIT(17),
158 .hw.init = &(struct clk_init_data){
159 .name = "mi2s_osr_clk",
160 .parent_names = lcc_mi2s_parents,
162 .ops = &clk_branch_ops,
163 .flags = CLK_SET_RATE_PARENT,
168 static struct clk_regmap_div mi2s_div_clk = {
173 .hw.init = &(struct clk_init_data){
174 .name = "mi2s_div_clk",
175 .parent_names = lcc_mi2s_parents,
177 .ops = &clk_regmap_div_ops,
182 static struct clk_branch mi2s_bit_div_clk = {
185 .halt_check = BRANCH_HALT_ENABLE,
188 .enable_mask = BIT(15),
189 .hw.init = &(struct clk_init_data){
190 .name = "mi2s_bit_div_clk",
191 .parent_names = (const char *[]){ "mi2s_div_clk" },
193 .ops = &clk_branch_ops,
194 .flags = CLK_SET_RATE_PARENT,
200 static struct clk_regmap_mux mi2s_bit_clk = {
205 .hw.init = &(struct clk_init_data){
206 .name = "mi2s_bit_clk",
207 .parent_names = (const char *[]){
212 .ops = &clk_regmap_mux_closest_ops,
213 .flags = CLK_SET_RATE_PARENT,
218 static struct freq_tbl clk_tbl_pcm[] = {
219 { 64000, P_PLL4, 4, 1, 1536 },
220 { 128000, P_PLL4, 4, 1, 768 },
221 { 256000, P_PLL4, 4, 1, 384 },
222 { 512000, P_PLL4, 4, 1, 192 },
223 { 1024000, P_PLL4, 4, 1, 96 },
224 { 2048000, P_PLL4, 4, 1, 48 },
228 static struct clk_rcg pcm_src = {
233 .mnctr_reset_bit = 7,
234 .mnctr_mode_shift = 5,
245 .parent_map = lcc_pxo_pll4_map,
247 .freq_tbl = clk_tbl_pcm,
250 .enable_mask = BIT(9),
251 .hw.init = &(struct clk_init_data){
253 .parent_names = lcc_pxo_pll4,
256 .flags = CLK_SET_RATE_GATE,
261 static struct clk_branch pcm_clk_out = {
264 .halt_check = BRANCH_HALT_ENABLE,
267 .enable_mask = BIT(11),
268 .hw.init = &(struct clk_init_data){
269 .name = "pcm_clk_out",
270 .parent_names = (const char *[]){ "pcm_src" },
272 .ops = &clk_branch_ops,
273 .flags = CLK_SET_RATE_PARENT,
278 static struct clk_regmap_mux pcm_clk = {
283 .hw.init = &(struct clk_init_data){
285 .parent_names = (const char *[]){
290 .ops = &clk_regmap_mux_closest_ops,
291 .flags = CLK_SET_RATE_PARENT,
296 static struct freq_tbl clk_tbl_aif_osr[] = {
297 { 22050, P_PLL4, 1, 147, 20480 },
298 { 32000, P_PLL4, 1, 1, 96 },
299 { 44100, P_PLL4, 1, 147, 10240 },
300 { 48000, P_PLL4, 1, 1, 64 },
301 { 88200, P_PLL4, 1, 147, 5120 },
302 { 96000, P_PLL4, 1, 1, 32 },
303 { 176400, P_PLL4, 1, 147, 2560 },
304 { 192000, P_PLL4, 1, 1, 16 },
308 static struct clk_rcg spdif_src = {
313 .mnctr_reset_bit = 7,
314 .mnctr_mode_shift = 5,
325 .parent_map = lcc_pxo_pll4_map,
327 .freq_tbl = clk_tbl_aif_osr,
330 .enable_mask = BIT(9),
331 .hw.init = &(struct clk_init_data){
333 .parent_names = lcc_pxo_pll4,
336 .flags = CLK_SET_RATE_GATE,
341 static const char *lcc_spdif_parents[] = {
345 static struct clk_branch spdif_clk = {
348 .halt_check = BRANCH_HALT_ENABLE,
351 .enable_mask = BIT(12),
352 .hw.init = &(struct clk_init_data){
354 .parent_names = lcc_spdif_parents,
356 .ops = &clk_branch_ops,
357 .flags = CLK_SET_RATE_PARENT,
362 static struct freq_tbl clk_tbl_ahbix[] = {
363 { 131072, P_PLL4, 1, 1, 3 },
367 static struct clk_rcg ahbix_clk = {
372 .mnctr_reset_bit = 7,
373 .mnctr_mode_shift = 5,
384 .parent_map = lcc_pxo_pll4_map,
386 .freq_tbl = clk_tbl_ahbix,
389 .enable_mask = BIT(10), /* toggle the gfmux to select mn/pxo */
390 .hw.init = &(struct clk_init_data){
392 .parent_names = lcc_pxo_pll4,
395 .flags = CLK_SET_RATE_GATE,
400 static struct clk_regmap *lcc_ipq806x_clks[] = {
402 [MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
403 [MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
404 [MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
405 [MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
406 [MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
407 [PCM_SRC] = &pcm_src.clkr,
408 [PCM_CLK_OUT] = &pcm_clk_out.clkr,
409 [PCM_CLK] = &pcm_clk.clkr,
410 [SPDIF_SRC] = &spdif_src.clkr,
411 [SPDIF_CLK] = &spdif_clk.clkr,
412 [AHBIX_CLK] = &ahbix_clk.clkr,
415 static const struct regmap_config lcc_ipq806x_regmap_config = {
419 .max_register = 0xfc,
423 static const struct qcom_cc_desc lcc_ipq806x_desc = {
424 .config = &lcc_ipq806x_regmap_config,
425 .clks = lcc_ipq806x_clks,
426 .num_clks = ARRAY_SIZE(lcc_ipq806x_clks),
429 static const struct of_device_id lcc_ipq806x_match_table[] = {
430 { .compatible = "qcom,lcc-ipq8064" },
433 MODULE_DEVICE_TABLE(of, lcc_ipq806x_match_table);
435 static int lcc_ipq806x_probe(struct platform_device *pdev)
438 struct regmap *regmap;
440 regmap = qcom_cc_map(pdev, &lcc_ipq806x_desc);
442 return PTR_ERR(regmap);
444 /* Configure the rate of PLL4 if the bootloader hasn't already */
445 val = regmap_read(regmap, 0x0, &val);
447 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true);
448 /* Enable PLL4 source on the LPASS Primary PLL Mux */
449 regmap_write(regmap, 0xc4, 0x1);
451 return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
454 static int lcc_ipq806x_remove(struct platform_device *pdev)
456 qcom_cc_remove(pdev);
460 static struct platform_driver lcc_ipq806x_driver = {
461 .probe = lcc_ipq806x_probe,
462 .remove = lcc_ipq806x_remove,
464 .name = "lcc-ipq806x",
465 .of_match_table = lcc_ipq806x_match_table,
468 module_platform_driver(lcc_ipq806x_driver);
470 MODULE_DESCRIPTION("QCOM LCC IPQ806x Driver");
471 MODULE_LICENSE("GPL v2");
472 MODULE_ALIAS("platform:lcc-ipq806x");