2 * Copyright 2015 Linaro Limited
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
49 static const struct parent_map gcc_xo_gpll0_map[] = {
54 static const char * const gcc_xo_gpll0[] = {
59 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
65 static const char * const gcc_xo_gpll0_bimc[] = {
71 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {
78 static const char * const gcc_xo_gpll0a_gpll1_gpll2a[] = {
85 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
91 static const char * const gcc_xo_gpll0_gpll2[] = {
97 static const struct parent_map gcc_xo_gpll0a_map[] = {
102 static const char * const gcc_xo_gpll0a[] = {
107 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map[] = {
114 static const char * const gcc_xo_gpll0_gpll1a_sleep[] = {
121 static const struct parent_map gcc_xo_gpll0_gpll1a_map[] = {
127 static const char * const gcc_xo_gpll0_gpll1a[] = {
133 static const struct parent_map gcc_xo_dsibyte_map[] = {
135 { P_DSI0_PHYPLL_BYTE, 2 },
138 static const char * const gcc_xo_dsibyte[] = {
143 static const struct parent_map gcc_xo_gpll0a_dsibyte_map[] = {
146 { P_DSI0_PHYPLL_BYTE, 1 },
149 static const char * const gcc_xo_gpll0a_dsibyte[] = {
155 static const struct parent_map gcc_xo_gpll0_dsiphy_map[] = {
158 { P_DSI0_PHYPLL_DSI, 2 },
161 static const char * const gcc_xo_gpll0_dsiphy[] = {
167 static const struct parent_map gcc_xo_gpll0a_dsiphy_map[] = {
170 { P_DSI0_PHYPLL_DSI, 1 },
173 static const char * const gcc_xo_gpll0a_dsiphy[] = {
179 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map[] = {
186 static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
193 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
195 static struct clk_pll gpll0 = {
199 .config_reg = 0x21014,
201 .status_reg = 0x2101c,
203 .clkr.hw.init = &(struct clk_init_data){
205 .parent_names = (const char *[]){ "xo" },
211 static struct clk_regmap gpll0_vote = {
212 .enable_reg = 0x45000,
213 .enable_mask = BIT(0),
214 .hw.init = &(struct clk_init_data){
215 .name = "gpll0_vote",
216 .parent_names = (const char *[]){ "gpll0" },
218 .ops = &clk_pll_vote_ops,
222 static struct clk_pll gpll1 = {
226 .config_reg = 0x20014,
228 .status_reg = 0x2001c,
230 .clkr.hw.init = &(struct clk_init_data){
232 .parent_names = (const char *[]){ "xo" },
238 static struct clk_regmap gpll1_vote = {
239 .enable_reg = 0x45000,
240 .enable_mask = BIT(1),
241 .hw.init = &(struct clk_init_data){
242 .name = "gpll1_vote",
243 .parent_names = (const char *[]){ "gpll1" },
245 .ops = &clk_pll_vote_ops,
249 static struct clk_pll gpll2 = {
253 .config_reg = 0x4a014,
255 .status_reg = 0x4a01c,
257 .clkr.hw.init = &(struct clk_init_data){
259 .parent_names = (const char *[]){ "xo" },
265 static struct clk_regmap gpll2_vote = {
266 .enable_reg = 0x45000,
267 .enable_mask = BIT(2),
268 .hw.init = &(struct clk_init_data){
269 .name = "gpll2_vote",
270 .parent_names = (const char *[]){ "gpll2" },
272 .ops = &clk_pll_vote_ops,
276 static struct clk_pll bimc_pll = {
280 .config_reg = 0x23014,
282 .status_reg = 0x2301c,
284 .clkr.hw.init = &(struct clk_init_data){
286 .parent_names = (const char *[]){ "xo" },
292 static struct clk_regmap bimc_pll_vote = {
293 .enable_reg = 0x45000,
294 .enable_mask = BIT(3),
295 .hw.init = &(struct clk_init_data){
296 .name = "bimc_pll_vote",
297 .parent_names = (const char *[]){ "bimc_pll" },
299 .ops = &clk_pll_vote_ops,
303 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
306 .parent_map = gcc_xo_gpll0_bimc_map,
307 .clkr.hw.init = &(struct clk_init_data){
308 .name = "pcnoc_bfdcd_clk_src",
309 .parent_names = gcc_xo_gpll0_bimc,
311 .ops = &clk_rcg2_ops,
315 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
318 .parent_map = gcc_xo_gpll0_bimc_map,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "system_noc_bfdcd_clk_src",
321 .parent_names = gcc_xo_gpll0_bimc,
323 .ops = &clk_rcg2_ops,
327 static const struct freq_tbl ftbl_gcc_camss_ahb_clk[] = {
328 F(40000000, P_GPLL0, 10, 1, 2),
329 F(80000000, P_GPLL0, 10, 0, 0),
333 static struct clk_rcg2 camss_ahb_clk_src = {
337 .parent_map = gcc_xo_gpll0_map,
338 .freq_tbl = ftbl_gcc_camss_ahb_clk,
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "camss_ahb_clk_src",
341 .parent_names = gcc_xo_gpll0,
343 .ops = &clk_rcg2_ops,
347 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
348 F(19200000, P_XO, 1, 0, 0),
349 F(50000000, P_GPLL0, 16, 0, 0),
350 F(100000000, P_GPLL0, 8, 0, 0),
351 F(133330000, P_GPLL0, 6, 0, 0),
355 static struct clk_rcg2 apss_ahb_clk_src = {
358 .parent_map = gcc_xo_gpll0_map,
359 .freq_tbl = ftbl_apss_ahb_clk,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "apss_ahb_clk_src",
362 .parent_names = gcc_xo_gpll0,
364 .ops = &clk_rcg2_ops,
368 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk[] = {
369 F(100000000, P_GPLL0, 8, 0, 0),
370 F(200000000, P_GPLL0, 4, 0, 0),
374 static struct clk_rcg2 csi0_clk_src = {
377 .parent_map = gcc_xo_gpll0_map,
378 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
379 .clkr.hw.init = &(struct clk_init_data){
380 .name = "csi0_clk_src",
381 .parent_names = gcc_xo_gpll0,
383 .ops = &clk_rcg2_ops,
387 static struct clk_rcg2 csi1_clk_src = {
390 .parent_map = gcc_xo_gpll0_map,
391 .freq_tbl = ftbl_gcc_camss_csi0_1_clk,
392 .clkr.hw.init = &(struct clk_init_data){
393 .name = "csi1_clk_src",
394 .parent_names = gcc_xo_gpll0,
396 .ops = &clk_rcg2_ops,
400 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
401 F(19200000, P_XO, 1, 0, 0),
402 F(50000000, P_GPLL0_AUX, 16, 0, 0),
403 F(80000000, P_GPLL0_AUX, 10, 0, 0),
404 F(100000000, P_GPLL0_AUX, 8, 0, 0),
405 F(160000000, P_GPLL0_AUX, 5, 0, 0),
406 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
407 F(200000000, P_GPLL0_AUX, 4, 0, 0),
408 F(266670000, P_GPLL0_AUX, 3, 0, 0),
409 F(294912000, P_GPLL1, 3, 0, 0),
410 F(310000000, P_GPLL2, 3, 0, 0),
411 F(400000000, P_GPLL0_AUX, 2, 0, 0),
415 static struct clk_rcg2 gfx3d_clk_src = {
418 .parent_map = gcc_xo_gpll0a_gpll1_gpll2a_map,
419 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
420 .clkr.hw.init = &(struct clk_init_data){
421 .name = "gfx3d_clk_src",
422 .parent_names = gcc_xo_gpll0a_gpll1_gpll2a,
424 .ops = &clk_rcg2_ops,
428 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
429 F(50000000, P_GPLL0, 16, 0, 0),
430 F(80000000, P_GPLL0, 10, 0, 0),
431 F(100000000, P_GPLL0, 8, 0, 0),
432 F(160000000, P_GPLL0, 5, 0, 0),
433 F(177780000, P_GPLL0, 4.5, 0, 0),
434 F(200000000, P_GPLL0, 4, 0, 0),
435 F(266670000, P_GPLL0, 3, 0, 0),
436 F(320000000, P_GPLL0, 2.5, 0, 0),
437 F(400000000, P_GPLL0, 2, 0, 0),
438 F(465000000, P_GPLL2, 2, 0, 0),
442 static struct clk_rcg2 vfe0_clk_src = {
445 .parent_map = gcc_xo_gpll0_gpll2_map,
446 .freq_tbl = ftbl_gcc_camss_vfe0_clk,
447 .clkr.hw.init = &(struct clk_init_data){
448 .name = "vfe0_clk_src",
449 .parent_names = gcc_xo_gpll0_gpll2,
451 .ops = &clk_rcg2_ops,
455 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
456 F(19200000, P_XO, 1, 0, 0),
457 F(50000000, P_GPLL0, 16, 0, 0),
461 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
464 .parent_map = gcc_xo_gpll0_map,
465 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
466 .clkr.hw.init = &(struct clk_init_data){
467 .name = "blsp1_qup1_i2c_apps_clk_src",
468 .parent_names = gcc_xo_gpll0,
470 .ops = &clk_rcg2_ops,
474 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
475 F(960000, P_XO, 10, 1, 2),
476 F(4800000, P_XO, 4, 0, 0),
477 F(9600000, P_XO, 2, 0, 0),
478 F(16000000, P_GPLL0, 10, 1, 5),
479 F(19200000, P_XO, 1, 0, 0),
480 F(25000000, P_GPLL0, 16, 1, 2),
481 F(50000000, P_GPLL0, 16, 0, 0),
485 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
489 .parent_map = gcc_xo_gpll0_map,
490 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
491 .clkr.hw.init = &(struct clk_init_data){
492 .name = "blsp1_qup1_spi_apps_clk_src",
493 .parent_names = gcc_xo_gpll0,
495 .ops = &clk_rcg2_ops,
499 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
502 .parent_map = gcc_xo_gpll0_map,
503 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
504 .clkr.hw.init = &(struct clk_init_data){
505 .name = "blsp1_qup2_i2c_apps_clk_src",
506 .parent_names = gcc_xo_gpll0,
508 .ops = &clk_rcg2_ops,
512 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
516 .parent_map = gcc_xo_gpll0_map,
517 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
518 .clkr.hw.init = &(struct clk_init_data){
519 .name = "blsp1_qup2_spi_apps_clk_src",
520 .parent_names = gcc_xo_gpll0,
522 .ops = &clk_rcg2_ops,
526 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
529 .parent_map = gcc_xo_gpll0_map,
530 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
531 .clkr.hw.init = &(struct clk_init_data){
532 .name = "blsp1_qup3_i2c_apps_clk_src",
533 .parent_names = gcc_xo_gpll0,
535 .ops = &clk_rcg2_ops,
539 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
543 .parent_map = gcc_xo_gpll0_map,
544 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
545 .clkr.hw.init = &(struct clk_init_data){
546 .name = "blsp1_qup3_spi_apps_clk_src",
547 .parent_names = gcc_xo_gpll0,
549 .ops = &clk_rcg2_ops,
553 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
556 .parent_map = gcc_xo_gpll0_map,
557 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
558 .clkr.hw.init = &(struct clk_init_data){
559 .name = "blsp1_qup4_i2c_apps_clk_src",
560 .parent_names = gcc_xo_gpll0,
562 .ops = &clk_rcg2_ops,
566 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
570 .parent_map = gcc_xo_gpll0_map,
571 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
572 .clkr.hw.init = &(struct clk_init_data){
573 .name = "blsp1_qup4_spi_apps_clk_src",
574 .parent_names = gcc_xo_gpll0,
576 .ops = &clk_rcg2_ops,
580 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
583 .parent_map = gcc_xo_gpll0_map,
584 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
585 .clkr.hw.init = &(struct clk_init_data){
586 .name = "blsp1_qup5_i2c_apps_clk_src",
587 .parent_names = gcc_xo_gpll0,
589 .ops = &clk_rcg2_ops,
593 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
597 .parent_map = gcc_xo_gpll0_map,
598 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
599 .clkr.hw.init = &(struct clk_init_data){
600 .name = "blsp1_qup5_spi_apps_clk_src",
601 .parent_names = gcc_xo_gpll0,
603 .ops = &clk_rcg2_ops,
607 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
610 .parent_map = gcc_xo_gpll0_map,
611 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
612 .clkr.hw.init = &(struct clk_init_data){
613 .name = "blsp1_qup6_i2c_apps_clk_src",
614 .parent_names = gcc_xo_gpll0,
616 .ops = &clk_rcg2_ops,
620 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
624 .parent_map = gcc_xo_gpll0_map,
625 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
626 .clkr.hw.init = &(struct clk_init_data){
627 .name = "blsp1_qup6_spi_apps_clk_src",
628 .parent_names = gcc_xo_gpll0,
630 .ops = &clk_rcg2_ops,
634 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
635 F(3686400, P_GPLL0, 1, 72, 15625),
636 F(7372800, P_GPLL0, 1, 144, 15625),
637 F(14745600, P_GPLL0, 1, 288, 15625),
638 F(16000000, P_GPLL0, 10, 1, 5),
639 F(19200000, P_XO, 1, 0, 0),
640 F(24000000, P_GPLL0, 1, 3, 100),
641 F(25000000, P_GPLL0, 16, 1, 2),
642 F(32000000, P_GPLL0, 1, 1, 25),
643 F(40000000, P_GPLL0, 1, 1, 20),
644 F(46400000, P_GPLL0, 1, 29, 500),
645 F(48000000, P_GPLL0, 1, 3, 50),
646 F(51200000, P_GPLL0, 1, 8, 125),
647 F(56000000, P_GPLL0, 1, 7, 100),
648 F(58982400, P_GPLL0, 1, 1152, 15625),
649 F(60000000, P_GPLL0, 1, 3, 40),
653 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
657 .parent_map = gcc_xo_gpll0_map,
658 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "blsp1_uart1_apps_clk_src",
661 .parent_names = gcc_xo_gpll0,
663 .ops = &clk_rcg2_ops,
667 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
671 .parent_map = gcc_xo_gpll0_map,
672 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "blsp1_uart2_apps_clk_src",
675 .parent_names = gcc_xo_gpll0,
677 .ops = &clk_rcg2_ops,
681 static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
682 F(19200000, P_XO, 1, 0, 0),
686 static struct clk_rcg2 cci_clk_src = {
690 .parent_map = gcc_xo_gpll0a_map,
691 .freq_tbl = ftbl_gcc_camss_cci_clk,
692 .clkr.hw.init = &(struct clk_init_data){
693 .name = "cci_clk_src",
694 .parent_names = gcc_xo_gpll0a,
696 .ops = &clk_rcg2_ops,
700 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
701 F(100000000, P_GPLL0, 8, 0, 0),
702 F(200000000, P_GPLL0, 4, 0, 0),
706 static struct clk_rcg2 camss_gp0_clk_src = {
710 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
711 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "camss_gp0_clk_src",
714 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
716 .ops = &clk_rcg2_ops,
720 static struct clk_rcg2 camss_gp1_clk_src = {
724 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
725 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
726 .clkr.hw.init = &(struct clk_init_data){
727 .name = "camss_gp1_clk_src",
728 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
730 .ops = &clk_rcg2_ops,
734 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
735 F(133330000, P_GPLL0, 6, 0, 0),
736 F(266670000, P_GPLL0, 3, 0, 0),
737 F(320000000, P_GPLL0, 2.5, 0, 0),
741 static struct clk_rcg2 jpeg0_clk_src = {
744 .parent_map = gcc_xo_gpll0_map,
745 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
746 .clkr.hw.init = &(struct clk_init_data){
747 .name = "jpeg0_clk_src",
748 .parent_names = gcc_xo_gpll0,
750 .ops = &clk_rcg2_ops,
754 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
755 F(9600000, P_XO, 2, 0, 0),
756 F(23880000, P_GPLL0, 1, 2, 67),
757 F(66670000, P_GPLL0, 12, 0, 0),
761 static struct clk_rcg2 mclk0_clk_src = {
765 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
766 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
767 .clkr.hw.init = &(struct clk_init_data){
768 .name = "mclk0_clk_src",
769 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
771 .ops = &clk_rcg2_ops,
775 static struct clk_rcg2 mclk1_clk_src = {
779 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
780 .freq_tbl = ftbl_gcc_camss_mclk0_1_clk,
781 .clkr.hw.init = &(struct clk_init_data){
782 .name = "mclk1_clk_src",
783 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
785 .ops = &clk_rcg2_ops,
789 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
790 F(100000000, P_GPLL0, 8, 0, 0),
791 F(200000000, P_GPLL0, 4, 0, 0),
795 static struct clk_rcg2 csi0phytimer_clk_src = {
798 .parent_map = gcc_xo_gpll0_gpll1a_map,
799 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
800 .clkr.hw.init = &(struct clk_init_data){
801 .name = "csi0phytimer_clk_src",
802 .parent_names = gcc_xo_gpll0_gpll1a,
804 .ops = &clk_rcg2_ops,
808 static struct clk_rcg2 csi1phytimer_clk_src = {
811 .parent_map = gcc_xo_gpll0_gpll1a_map,
812 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
813 .clkr.hw.init = &(struct clk_init_data){
814 .name = "csi1phytimer_clk_src",
815 .parent_names = gcc_xo_gpll0_gpll1a,
817 .ops = &clk_rcg2_ops,
821 static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
822 F(160000000, P_GPLL0, 5, 0, 0),
823 F(320000000, P_GPLL0, 2.5, 0, 0),
824 F(465000000, P_GPLL2, 2, 0, 0),
828 static struct clk_rcg2 cpp_clk_src = {
831 .parent_map = gcc_xo_gpll0_gpll2_map,
832 .freq_tbl = ftbl_gcc_camss_cpp_clk,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "cpp_clk_src",
835 .parent_names = gcc_xo_gpll0_gpll2,
837 .ops = &clk_rcg2_ops,
841 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
842 F(50000000, P_GPLL0, 16, 0, 0),
843 F(80000000, P_GPLL0, 10, 0, 0),
844 F(100000000, P_GPLL0, 8, 0, 0),
845 F(160000000, P_GPLL0, 5, 0, 0),
849 static struct clk_rcg2 crypto_clk_src = {
852 .parent_map = gcc_xo_gpll0_map,
853 .freq_tbl = ftbl_gcc_crypto_clk,
854 .clkr.hw.init = &(struct clk_init_data){
855 .name = "crypto_clk_src",
856 .parent_names = gcc_xo_gpll0,
858 .ops = &clk_rcg2_ops,
862 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
863 F(19200000, P_XO, 1, 0, 0),
867 static struct clk_rcg2 gp1_clk_src = {
871 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
872 .freq_tbl = ftbl_gcc_gp1_3_clk,
873 .clkr.hw.init = &(struct clk_init_data){
874 .name = "gp1_clk_src",
875 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
877 .ops = &clk_rcg2_ops,
881 static struct clk_rcg2 gp2_clk_src = {
885 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
886 .freq_tbl = ftbl_gcc_gp1_3_clk,
887 .clkr.hw.init = &(struct clk_init_data){
888 .name = "gp2_clk_src",
889 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
891 .ops = &clk_rcg2_ops,
895 static struct clk_rcg2 gp3_clk_src = {
899 .parent_map = gcc_xo_gpll0_gpll1a_sleep_map,
900 .freq_tbl = ftbl_gcc_gp1_3_clk,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "gp3_clk_src",
903 .parent_names = gcc_xo_gpll0_gpll1a_sleep,
905 .ops = &clk_rcg2_ops,
909 static struct freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
910 { .src = P_DSI0_PHYPLL_BYTE },
914 static struct clk_rcg2 byte0_clk_src = {
917 .parent_map = gcc_xo_gpll0a_dsibyte_map,
918 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
919 .clkr.hw.init = &(struct clk_init_data){
920 .name = "byte0_clk_src",
921 .parent_names = gcc_xo_gpll0a_dsibyte,
923 .ops = &clk_byte_ops,
924 .flags = CLK_SET_RATE_PARENT,
928 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
929 F(19200000, P_XO, 1, 0, 0),
933 static struct clk_rcg2 esc0_clk_src = {
936 .parent_map = gcc_xo_dsibyte_map,
937 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "esc0_clk_src",
940 .parent_names = gcc_xo_dsibyte,
942 .ops = &clk_rcg2_ops,
946 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
947 F(50000000, P_GPLL0, 16, 0, 0),
948 F(80000000, P_GPLL0, 10, 0, 0),
949 F(100000000, P_GPLL0, 8, 0, 0),
950 F(160000000, P_GPLL0, 5, 0, 0),
951 F(177780000, P_GPLL0, 4.5, 0, 0),
952 F(200000000, P_GPLL0, 4, 0, 0),
953 F(266670000, P_GPLL0, 3, 0, 0),
954 F(320000000, P_GPLL0, 2.5, 0, 0),
958 static struct clk_rcg2 mdp_clk_src = {
961 .parent_map = gcc_xo_gpll0_dsiphy_map,
962 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
963 .clkr.hw.init = &(struct clk_init_data){
964 .name = "mdp_clk_src",
965 .parent_names = gcc_xo_gpll0_dsiphy,
967 .ops = &clk_rcg2_ops,
971 static struct freq_tbl ftbl_gcc_mdss_pclk[] = {
972 { .src = P_DSI0_PHYPLL_DSI },
976 static struct clk_rcg2 pclk0_clk_src = {
980 .parent_map = gcc_xo_gpll0a_dsiphy_map,
981 .freq_tbl = ftbl_gcc_mdss_pclk,
982 .clkr.hw.init = &(struct clk_init_data){
983 .name = "pclk0_clk_src",
984 .parent_names = gcc_xo_gpll0a_dsiphy,
986 .ops = &clk_pixel_ops,
987 .flags = CLK_SET_RATE_PARENT,
991 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
992 F(19200000, P_XO, 1, 0, 0),
996 static struct clk_rcg2 vsync_clk_src = {
999 .parent_map = gcc_xo_gpll0a_map,
1000 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1001 .clkr.hw.init = &(struct clk_init_data){
1002 .name = "vsync_clk_src",
1003 .parent_names = gcc_xo_gpll0a,
1005 .ops = &clk_rcg2_ops,
1009 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1010 F(64000000, P_GPLL0, 12.5, 0, 0),
1014 static struct clk_rcg2 pdm2_clk_src = {
1015 .cmd_rcgr = 0x44010,
1017 .parent_map = gcc_xo_gpll0_map,
1018 .freq_tbl = ftbl_gcc_pdm2_clk,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "pdm2_clk_src",
1021 .parent_names = gcc_xo_gpll0,
1023 .ops = &clk_rcg2_ops,
1027 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1028 F(144000, P_XO, 16, 3, 25),
1029 F(400000, P_XO, 12, 1, 4),
1030 F(20000000, P_GPLL0, 10, 1, 4),
1031 F(25000000, P_GPLL0, 16, 1, 2),
1032 F(50000000, P_GPLL0, 16, 0, 0),
1033 F(100000000, P_GPLL0, 8, 0, 0),
1034 F(177770000, P_GPLL0, 4.5, 0, 0),
1038 static struct clk_rcg2 sdcc1_apps_clk_src = {
1039 .cmd_rcgr = 0x42004,
1042 .parent_map = gcc_xo_gpll0_map,
1043 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1044 .clkr.hw.init = &(struct clk_init_data){
1045 .name = "sdcc1_apps_clk_src",
1046 .parent_names = gcc_xo_gpll0,
1048 .ops = &clk_rcg2_ops,
1052 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1053 F(144000, P_XO, 16, 3, 25),
1054 F(400000, P_XO, 12, 1, 4),
1055 F(20000000, P_GPLL0, 10, 1, 4),
1056 F(25000000, P_GPLL0, 16, 1, 2),
1057 F(50000000, P_GPLL0, 16, 0, 0),
1058 F(100000000, P_GPLL0, 8, 0, 0),
1059 F(200000000, P_GPLL0, 4, 0, 0),
1063 static struct clk_rcg2 sdcc2_apps_clk_src = {
1064 .cmd_rcgr = 0x43004,
1067 .parent_map = gcc_xo_gpll0_map,
1068 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1069 .clkr.hw.init = &(struct clk_init_data){
1070 .name = "sdcc2_apps_clk_src",
1071 .parent_names = gcc_xo_gpll0,
1073 .ops = &clk_rcg2_ops,
1077 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
1078 F(155000000, P_GPLL2, 6, 0, 0),
1079 F(310000000, P_GPLL2, 3, 0, 0),
1080 F(400000000, P_GPLL0, 2, 0, 0),
1084 static struct clk_rcg2 apss_tcu_clk_src = {
1085 .cmd_rcgr = 0x1207c,
1087 .parent_map = gcc_xo_gpll0a_gpll1_gpll2_map,
1088 .freq_tbl = ftbl_gcc_apss_tcu_clk,
1089 .clkr.hw.init = &(struct clk_init_data){
1090 .name = "apss_tcu_clk_src",
1091 .parent_names = gcc_xo_gpll0a_gpll1_gpll2,
1093 .ops = &clk_rcg2_ops,
1097 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1098 F(80000000, P_GPLL0, 10, 0, 0),
1102 static struct clk_rcg2 usb_hs_system_clk_src = {
1103 .cmd_rcgr = 0x41010,
1105 .parent_map = gcc_xo_gpll0_map,
1106 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1107 .clkr.hw.init = &(struct clk_init_data){
1108 .name = "usb_hs_system_clk_src",
1109 .parent_names = gcc_xo_gpll0,
1111 .ops = &clk_rcg2_ops,
1115 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1116 F(100000000, P_GPLL0, 8, 0, 0),
1117 F(160000000, P_GPLL0, 5, 0, 0),
1118 F(228570000, P_GPLL0, 3.5, 0, 0),
1122 static struct clk_rcg2 vcodec0_clk_src = {
1123 .cmd_rcgr = 0x4C000,
1126 .parent_map = gcc_xo_gpll0_map,
1127 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
1128 .clkr.hw.init = &(struct clk_init_data){
1129 .name = "vcodec0_clk_src",
1130 .parent_names = gcc_xo_gpll0,
1132 .ops = &clk_rcg2_ops,
1136 static struct clk_branch gcc_blsp1_ahb_clk = {
1137 .halt_reg = 0x01008,
1138 .halt_check = BRANCH_HALT_VOTED,
1140 .enable_reg = 0x45004,
1141 .enable_mask = BIT(10),
1142 .hw.init = &(struct clk_init_data){
1143 .name = "gcc_blsp1_ahb_clk",
1144 .parent_names = (const char *[]){
1145 "pcnoc_bfdcd_clk_src",
1148 .ops = &clk_branch2_ops,
1153 static struct clk_branch gcc_blsp1_sleep_clk = {
1154 .halt_reg = 0x01004,
1156 .enable_reg = 0x01004,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "gcc_blsp1_sleep_clk",
1160 .parent_names = (const char *[]){
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1170 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1171 .halt_reg = 0x02008,
1173 .enable_reg = 0x02008,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1177 .parent_names = (const char *[]){
1178 "blsp1_qup1_i2c_apps_clk_src",
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1187 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1188 .halt_reg = 0x02004,
1190 .enable_reg = 0x02004,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "gcc_blsp1_qup1_spi_apps_clk",
1194 .parent_names = (const char *[]){
1195 "blsp1_qup1_spi_apps_clk_src",
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1204 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1205 .halt_reg = 0x03010,
1207 .enable_reg = 0x03010,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1211 .parent_names = (const char *[]){
1212 "blsp1_qup2_i2c_apps_clk_src",
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1221 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1222 .halt_reg = 0x0300c,
1224 .enable_reg = 0x0300c,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "gcc_blsp1_qup2_spi_apps_clk",
1228 .parent_names = (const char *[]){
1229 "blsp1_qup2_spi_apps_clk_src",
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1238 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1239 .halt_reg = 0x04020,
1241 .enable_reg = 0x04020,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1245 .parent_names = (const char *[]){
1246 "blsp1_qup3_i2c_apps_clk_src",
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1255 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1256 .halt_reg = 0x0401c,
1258 .enable_reg = 0x0401c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "gcc_blsp1_qup3_spi_apps_clk",
1262 .parent_names = (const char *[]){
1263 "blsp1_qup3_spi_apps_clk_src",
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1272 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1273 .halt_reg = 0x05020,
1275 .enable_reg = 0x05020,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1279 .parent_names = (const char *[]){
1280 "blsp1_qup4_i2c_apps_clk_src",
1283 .flags = CLK_SET_RATE_PARENT,
1284 .ops = &clk_branch2_ops,
1289 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1290 .halt_reg = 0x0501c,
1292 .enable_reg = 0x0501c,
1293 .enable_mask = BIT(0),
1294 .hw.init = &(struct clk_init_data){
1295 .name = "gcc_blsp1_qup4_spi_apps_clk",
1296 .parent_names = (const char *[]){
1297 "blsp1_qup4_spi_apps_clk_src",
1300 .flags = CLK_SET_RATE_PARENT,
1301 .ops = &clk_branch2_ops,
1306 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1307 .halt_reg = 0x06020,
1309 .enable_reg = 0x06020,
1310 .enable_mask = BIT(0),
1311 .hw.init = &(struct clk_init_data){
1312 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1313 .parent_names = (const char *[]){
1314 "blsp1_qup5_i2c_apps_clk_src",
1317 .flags = CLK_SET_RATE_PARENT,
1318 .ops = &clk_branch2_ops,
1323 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1324 .halt_reg = 0x0601c,
1326 .enable_reg = 0x0601c,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "gcc_blsp1_qup5_spi_apps_clk",
1330 .parent_names = (const char *[]){
1331 "blsp1_qup5_spi_apps_clk_src",
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1340 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1341 .halt_reg = 0x07020,
1343 .enable_reg = 0x07020,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1347 .parent_names = (const char *[]){
1348 "blsp1_qup6_i2c_apps_clk_src",
1351 .flags = CLK_SET_RATE_PARENT,
1352 .ops = &clk_branch2_ops,
1357 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1358 .halt_reg = 0x0701c,
1360 .enable_reg = 0x0701c,
1361 .enable_mask = BIT(0),
1362 .hw.init = &(struct clk_init_data){
1363 .name = "gcc_blsp1_qup6_spi_apps_clk",
1364 .parent_names = (const char *[]){
1365 "blsp1_qup6_spi_apps_clk_src",
1368 .flags = CLK_SET_RATE_PARENT,
1369 .ops = &clk_branch2_ops,
1374 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1375 .halt_reg = 0x0203c,
1377 .enable_reg = 0x0203c,
1378 .enable_mask = BIT(0),
1379 .hw.init = &(struct clk_init_data){
1380 .name = "gcc_blsp1_uart1_apps_clk",
1381 .parent_names = (const char *[]){
1382 "blsp1_uart1_apps_clk_src",
1385 .flags = CLK_SET_RATE_PARENT,
1386 .ops = &clk_branch2_ops,
1391 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1392 .halt_reg = 0x0302c,
1394 .enable_reg = 0x0302c,
1395 .enable_mask = BIT(0),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "gcc_blsp1_uart2_apps_clk",
1398 .parent_names = (const char *[]){
1399 "blsp1_uart2_apps_clk_src",
1402 .flags = CLK_SET_RATE_PARENT,
1403 .ops = &clk_branch2_ops,
1408 static struct clk_branch gcc_boot_rom_ahb_clk = {
1409 .halt_reg = 0x1300c,
1410 .halt_check = BRANCH_HALT_VOTED,
1412 .enable_reg = 0x45004,
1413 .enable_mask = BIT(7),
1414 .hw.init = &(struct clk_init_data){
1415 .name = "gcc_boot_rom_ahb_clk",
1416 .parent_names = (const char *[]){
1417 "pcnoc_bfdcd_clk_src",
1420 .ops = &clk_branch2_ops,
1425 static struct clk_branch gcc_camss_cci_ahb_clk = {
1426 .halt_reg = 0x5101c,
1428 .enable_reg = 0x5101c,
1429 .enable_mask = BIT(0),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "gcc_camss_cci_ahb_clk",
1432 .parent_names = (const char *[]){
1433 "camss_ahb_clk_src",
1436 .flags = CLK_SET_RATE_PARENT,
1437 .ops = &clk_branch2_ops,
1442 static struct clk_branch gcc_camss_cci_clk = {
1443 .halt_reg = 0x51018,
1445 .enable_reg = 0x51018,
1446 .enable_mask = BIT(0),
1447 .hw.init = &(struct clk_init_data){
1448 .name = "gcc_camss_cci_clk",
1449 .parent_names = (const char *[]){
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1459 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1460 .halt_reg = 0x4e040,
1462 .enable_reg = 0x4e040,
1463 .enable_mask = BIT(0),
1464 .hw.init = &(struct clk_init_data){
1465 .name = "gcc_camss_csi0_ahb_clk",
1466 .parent_names = (const char *[]){
1467 "camss_ahb_clk_src",
1470 .flags = CLK_SET_RATE_PARENT,
1471 .ops = &clk_branch2_ops,
1476 static struct clk_branch gcc_camss_csi0_clk = {
1477 .halt_reg = 0x4e03c,
1479 .enable_reg = 0x4e03c,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "gcc_camss_csi0_clk",
1483 .parent_names = (const char *[]){
1487 .flags = CLK_SET_RATE_PARENT,
1488 .ops = &clk_branch2_ops,
1493 static struct clk_branch gcc_camss_csi0phy_clk = {
1494 .halt_reg = 0x4e048,
1496 .enable_reg = 0x4e048,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "gcc_camss_csi0phy_clk",
1500 .parent_names = (const char *[]){
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_camss_csi0pix_clk = {
1511 .halt_reg = 0x4e058,
1513 .enable_reg = 0x4e058,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "gcc_camss_csi0pix_clk",
1517 .parent_names = (const char *[]){
1521 .flags = CLK_SET_RATE_PARENT,
1522 .ops = &clk_branch2_ops,
1527 static struct clk_branch gcc_camss_csi0rdi_clk = {
1528 .halt_reg = 0x4e050,
1530 .enable_reg = 0x4e050,
1531 .enable_mask = BIT(0),
1532 .hw.init = &(struct clk_init_data){
1533 .name = "gcc_camss_csi0rdi_clk",
1534 .parent_names = (const char *[]){
1538 .flags = CLK_SET_RATE_PARENT,
1539 .ops = &clk_branch2_ops,
1544 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1545 .halt_reg = 0x4f040,
1547 .enable_reg = 0x4f040,
1548 .enable_mask = BIT(0),
1549 .hw.init = &(struct clk_init_data){
1550 .name = "gcc_camss_csi1_ahb_clk",
1551 .parent_names = (const char *[]){
1552 "camss_ahb_clk_src",
1555 .flags = CLK_SET_RATE_PARENT,
1556 .ops = &clk_branch2_ops,
1561 static struct clk_branch gcc_camss_csi1_clk = {
1562 .halt_reg = 0x4f03c,
1564 .enable_reg = 0x4f03c,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "gcc_camss_csi1_clk",
1568 .parent_names = (const char *[]){
1572 .flags = CLK_SET_RATE_PARENT,
1573 .ops = &clk_branch2_ops,
1578 static struct clk_branch gcc_camss_csi1phy_clk = {
1579 .halt_reg = 0x4f048,
1581 .enable_reg = 0x4f048,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "gcc_camss_csi1phy_clk",
1585 .parent_names = (const char *[]){
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch gcc_camss_csi1pix_clk = {
1596 .halt_reg = 0x4f058,
1598 .enable_reg = 0x4f058,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "gcc_camss_csi1pix_clk",
1602 .parent_names = (const char *[]){
1606 .flags = CLK_SET_RATE_PARENT,
1607 .ops = &clk_branch2_ops,
1612 static struct clk_branch gcc_camss_csi1rdi_clk = {
1613 .halt_reg = 0x4f050,
1615 .enable_reg = 0x4f050,
1616 .enable_mask = BIT(0),
1617 .hw.init = &(struct clk_init_data){
1618 .name = "gcc_camss_csi1rdi_clk",
1619 .parent_names = (const char *[]){
1623 .flags = CLK_SET_RATE_PARENT,
1624 .ops = &clk_branch2_ops,
1629 static struct clk_branch gcc_camss_csi_vfe0_clk = {
1630 .halt_reg = 0x58050,
1632 .enable_reg = 0x58050,
1633 .enable_mask = BIT(0),
1634 .hw.init = &(struct clk_init_data){
1635 .name = "gcc_camss_csi_vfe0_clk",
1636 .parent_names = (const char *[]){
1640 .flags = CLK_SET_RATE_PARENT,
1641 .ops = &clk_branch2_ops,
1646 static struct clk_branch gcc_camss_gp0_clk = {
1647 .halt_reg = 0x54018,
1649 .enable_reg = 0x54018,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_camss_gp0_clk",
1653 .parent_names = (const char *[]){
1654 "camss_gp0_clk_src",
1657 .flags = CLK_SET_RATE_PARENT,
1658 .ops = &clk_branch2_ops,
1663 static struct clk_branch gcc_camss_gp1_clk = {
1664 .halt_reg = 0x55018,
1666 .enable_reg = 0x55018,
1667 .enable_mask = BIT(0),
1668 .hw.init = &(struct clk_init_data){
1669 .name = "gcc_camss_gp1_clk",
1670 .parent_names = (const char *[]){
1671 "camss_gp1_clk_src",
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch gcc_camss_ispif_ahb_clk = {
1681 .halt_reg = 0x50004,
1683 .enable_reg = 0x50004,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "gcc_camss_ispif_ahb_clk",
1687 .parent_names = (const char *[]){
1688 "camss_ahb_clk_src",
1691 .flags = CLK_SET_RATE_PARENT,
1692 .ops = &clk_branch2_ops,
1697 static struct clk_branch gcc_camss_jpeg0_clk = {
1698 .halt_reg = 0x57020,
1700 .enable_reg = 0x57020,
1701 .enable_mask = BIT(0),
1702 .hw.init = &(struct clk_init_data){
1703 .name = "gcc_camss_jpeg0_clk",
1704 .parent_names = (const char *[]){
1708 .flags = CLK_SET_RATE_PARENT,
1709 .ops = &clk_branch2_ops,
1714 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
1715 .halt_reg = 0x57024,
1717 .enable_reg = 0x57024,
1718 .enable_mask = BIT(0),
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gcc_camss_jpeg_ahb_clk",
1721 .parent_names = (const char *[]){
1722 "camss_ahb_clk_src",
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1731 static struct clk_branch gcc_camss_jpeg_axi_clk = {
1732 .halt_reg = 0x57028,
1734 .enable_reg = 0x57028,
1735 .enable_mask = BIT(0),
1736 .hw.init = &(struct clk_init_data){
1737 .name = "gcc_camss_jpeg_axi_clk",
1738 .parent_names = (const char *[]){
1739 "system_noc_bfdcd_clk_src",
1742 .flags = CLK_SET_RATE_PARENT,
1743 .ops = &clk_branch2_ops,
1748 static struct clk_branch gcc_camss_mclk0_clk = {
1749 .halt_reg = 0x52018,
1751 .enable_reg = 0x52018,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(struct clk_init_data){
1754 .name = "gcc_camss_mclk0_clk",
1755 .parent_names = (const char *[]){
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1765 static struct clk_branch gcc_camss_mclk1_clk = {
1766 .halt_reg = 0x53018,
1768 .enable_reg = 0x53018,
1769 .enable_mask = BIT(0),
1770 .hw.init = &(struct clk_init_data){
1771 .name = "gcc_camss_mclk1_clk",
1772 .parent_names = (const char *[]){
1776 .flags = CLK_SET_RATE_PARENT,
1777 .ops = &clk_branch2_ops,
1782 static struct clk_branch gcc_camss_micro_ahb_clk = {
1783 .halt_reg = 0x5600c,
1785 .enable_reg = 0x5600c,
1786 .enable_mask = BIT(0),
1787 .hw.init = &(struct clk_init_data){
1788 .name = "gcc_camss_micro_ahb_clk",
1789 .parent_names = (const char *[]){
1790 "camss_ahb_clk_src",
1793 .flags = CLK_SET_RATE_PARENT,
1794 .ops = &clk_branch2_ops,
1799 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1800 .halt_reg = 0x4e01c,
1802 .enable_reg = 0x4e01c,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "gcc_camss_csi0phytimer_clk",
1806 .parent_names = (const char *[]){
1807 "csi0phytimer_clk_src",
1810 .flags = CLK_SET_RATE_PARENT,
1811 .ops = &clk_branch2_ops,
1816 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1817 .halt_reg = 0x4f01c,
1819 .enable_reg = 0x4f01c,
1820 .enable_mask = BIT(0),
1821 .hw.init = &(struct clk_init_data){
1822 .name = "gcc_camss_csi1phytimer_clk",
1823 .parent_names = (const char *[]){
1824 "csi1phytimer_clk_src",
1827 .flags = CLK_SET_RATE_PARENT,
1828 .ops = &clk_branch2_ops,
1833 static struct clk_branch gcc_camss_ahb_clk = {
1834 .halt_reg = 0x5a014,
1836 .enable_reg = 0x5a014,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "gcc_camss_ahb_clk",
1840 .parent_names = (const char *[]){
1841 "camss_ahb_clk_src",
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1850 static struct clk_branch gcc_camss_top_ahb_clk = {
1851 .halt_reg = 0x56004,
1853 .enable_reg = 0x56004,
1854 .enable_mask = BIT(0),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "gcc_camss_top_ahb_clk",
1857 .parent_names = (const char *[]){
1858 "pcnoc_bfdcd_clk_src",
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1867 static struct clk_branch gcc_camss_cpp_ahb_clk = {
1868 .halt_reg = 0x58040,
1870 .enable_reg = 0x58040,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_camss_cpp_ahb_clk",
1874 .parent_names = (const char *[]){
1875 "camss_ahb_clk_src",
1878 .flags = CLK_SET_RATE_PARENT,
1879 .ops = &clk_branch2_ops,
1884 static struct clk_branch gcc_camss_cpp_clk = {
1885 .halt_reg = 0x5803c,
1887 .enable_reg = 0x5803c,
1888 .enable_mask = BIT(0),
1889 .hw.init = &(struct clk_init_data){
1890 .name = "gcc_camss_cpp_clk",
1891 .parent_names = (const char *[]){
1895 .flags = CLK_SET_RATE_PARENT,
1896 .ops = &clk_branch2_ops,
1901 static struct clk_branch gcc_camss_vfe0_clk = {
1902 .halt_reg = 0x58038,
1904 .enable_reg = 0x58038,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_camss_vfe0_clk",
1908 .parent_names = (const char *[]){
1912 .flags = CLK_SET_RATE_PARENT,
1913 .ops = &clk_branch2_ops,
1918 static struct clk_branch gcc_camss_vfe_ahb_clk = {
1919 .halt_reg = 0x58044,
1921 .enable_reg = 0x58044,
1922 .enable_mask = BIT(0),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "gcc_camss_vfe_ahb_clk",
1925 .parent_names = (const char *[]){
1926 "camss_ahb_clk_src",
1929 .flags = CLK_SET_RATE_PARENT,
1930 .ops = &clk_branch2_ops,
1935 static struct clk_branch gcc_camss_vfe_axi_clk = {
1936 .halt_reg = 0x58048,
1938 .enable_reg = 0x58048,
1939 .enable_mask = BIT(0),
1940 .hw.init = &(struct clk_init_data){
1941 .name = "gcc_camss_vfe_axi_clk",
1942 .parent_names = (const char *[]){
1943 "system_noc_bfdcd_clk_src",
1946 .flags = CLK_SET_RATE_PARENT,
1947 .ops = &clk_branch2_ops,
1952 static struct clk_branch gcc_crypto_ahb_clk = {
1953 .halt_reg = 0x16024,
1954 .halt_check = BRANCH_HALT_VOTED,
1956 .enable_reg = 0x45004,
1957 .enable_mask = BIT(0),
1958 .hw.init = &(struct clk_init_data){
1959 .name = "gcc_crypto_ahb_clk",
1960 .parent_names = (const char *[]){
1961 "pcnoc_bfdcd_clk_src",
1964 .ops = &clk_branch2_ops,
1969 static struct clk_branch gcc_crypto_axi_clk = {
1970 .halt_reg = 0x16020,
1971 .halt_check = BRANCH_HALT_VOTED,
1973 .enable_reg = 0x45004,
1974 .enable_mask = BIT(1),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "gcc_crypto_axi_clk",
1977 .parent_names = (const char *[]){
1978 "pcnoc_bfdcd_clk_src",
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_branch2_ops,
1987 static struct clk_branch gcc_crypto_clk = {
1988 .halt_reg = 0x1601c,
1989 .halt_check = BRANCH_HALT_VOTED,
1991 .enable_reg = 0x45004,
1992 .enable_mask = BIT(2),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "gcc_crypto_clk",
1995 .parent_names = (const char *[]){
1999 .ops = &clk_branch2_ops,
2004 static struct clk_branch gcc_oxili_gmem_clk = {
2005 .halt_reg = 0x59024,
2007 .enable_reg = 0x59024,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "gcc_oxili_gmem_clk",
2011 .parent_names = (const char *[]){
2015 .flags = CLK_SET_RATE_PARENT,
2016 .ops = &clk_branch2_ops,
2021 static struct clk_branch gcc_gp1_clk = {
2022 .halt_reg = 0x08000,
2024 .enable_reg = 0x08000,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gcc_gp1_clk",
2028 .parent_names = (const char *[]){
2032 .flags = CLK_SET_RATE_PARENT,
2033 .ops = &clk_branch2_ops,
2038 static struct clk_branch gcc_gp2_clk = {
2039 .halt_reg = 0x09000,
2041 .enable_reg = 0x09000,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(struct clk_init_data){
2044 .name = "gcc_gp2_clk",
2045 .parent_names = (const char *[]){
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_branch2_ops,
2055 static struct clk_branch gcc_gp3_clk = {
2056 .halt_reg = 0x0a000,
2058 .enable_reg = 0x0a000,
2059 .enable_mask = BIT(0),
2060 .hw.init = &(struct clk_init_data){
2061 .name = "gcc_gp3_clk",
2062 .parent_names = (const char *[]){
2066 .flags = CLK_SET_RATE_PARENT,
2067 .ops = &clk_branch2_ops,
2072 static struct clk_branch gcc_mdss_ahb_clk = {
2073 .halt_reg = 0x4d07c,
2075 .enable_reg = 0x4d07c,
2076 .enable_mask = BIT(0),
2077 .hw.init = &(struct clk_init_data){
2078 .name = "gcc_mdss_ahb_clk",
2079 .parent_names = (const char *[]){
2080 "pcnoc_bfdcd_clk_src",
2083 .flags = CLK_SET_RATE_PARENT,
2084 .ops = &clk_branch2_ops,
2089 static struct clk_branch gcc_mdss_axi_clk = {
2090 .halt_reg = 0x4d080,
2092 .enable_reg = 0x4d080,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_mdss_axi_clk",
2096 .parent_names = (const char *[]){
2097 "system_noc_bfdcd_clk_src",
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2106 static struct clk_branch gcc_mdss_byte0_clk = {
2107 .halt_reg = 0x4d094,
2109 .enable_reg = 0x4d094,
2110 .enable_mask = BIT(0),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "gcc_mdss_byte0_clk",
2113 .parent_names = (const char *[]){
2117 .flags = CLK_SET_RATE_PARENT,
2118 .ops = &clk_branch2_ops,
2123 static struct clk_branch gcc_mdss_esc0_clk = {
2124 .halt_reg = 0x4d098,
2126 .enable_reg = 0x4d098,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "gcc_mdss_esc0_clk",
2130 .parent_names = (const char *[]){
2134 .flags = CLK_SET_RATE_PARENT,
2135 .ops = &clk_branch2_ops,
2140 static struct clk_branch gcc_mdss_mdp_clk = {
2141 .halt_reg = 0x4D088,
2143 .enable_reg = 0x4D088,
2144 .enable_mask = BIT(0),
2145 .hw.init = &(struct clk_init_data){
2146 .name = "gcc_mdss_mdp_clk",
2147 .parent_names = (const char *[]){
2151 .flags = CLK_SET_RATE_PARENT,
2152 .ops = &clk_branch2_ops,
2157 static struct clk_branch gcc_mdss_pclk0_clk = {
2158 .halt_reg = 0x4d084,
2160 .enable_reg = 0x4d084,
2161 .enable_mask = BIT(0),
2162 .hw.init = &(struct clk_init_data){
2163 .name = "gcc_mdss_pclk0_clk",
2164 .parent_names = (const char *[]){
2168 .flags = CLK_SET_RATE_PARENT,
2169 .ops = &clk_branch2_ops,
2174 static struct clk_branch gcc_mdss_vsync_clk = {
2175 .halt_reg = 0x4d090,
2177 .enable_reg = 0x4d090,
2178 .enable_mask = BIT(0),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_mdss_vsync_clk",
2181 .parent_names = (const char *[]){
2185 .flags = CLK_SET_RATE_PARENT,
2186 .ops = &clk_branch2_ops,
2191 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2192 .halt_reg = 0x49000,
2194 .enable_reg = 0x49000,
2195 .enable_mask = BIT(0),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "gcc_mss_cfg_ahb_clk",
2198 .parent_names = (const char *[]){
2199 "pcnoc_bfdcd_clk_src",
2202 .flags = CLK_SET_RATE_PARENT,
2203 .ops = &clk_branch2_ops,
2208 static struct clk_branch gcc_oxili_ahb_clk = {
2209 .halt_reg = 0x59028,
2211 .enable_reg = 0x59028,
2212 .enable_mask = BIT(0),
2213 .hw.init = &(struct clk_init_data){
2214 .name = "gcc_oxili_ahb_clk",
2215 .parent_names = (const char *[]){
2216 "pcnoc_bfdcd_clk_src",
2219 .flags = CLK_SET_RATE_PARENT,
2220 .ops = &clk_branch2_ops,
2225 static struct clk_branch gcc_oxili_gfx3d_clk = {
2226 .halt_reg = 0x59020,
2228 .enable_reg = 0x59020,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "gcc_oxili_gfx3d_clk",
2232 .parent_names = (const char *[]){
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2242 static struct clk_branch gcc_pdm2_clk = {
2243 .halt_reg = 0x4400c,
2245 .enable_reg = 0x4400c,
2246 .enable_mask = BIT(0),
2247 .hw.init = &(struct clk_init_data){
2248 .name = "gcc_pdm2_clk",
2249 .parent_names = (const char *[]){
2253 .flags = CLK_SET_RATE_PARENT,
2254 .ops = &clk_branch2_ops,
2259 static struct clk_branch gcc_pdm_ahb_clk = {
2260 .halt_reg = 0x44004,
2262 .enable_reg = 0x44004,
2263 .enable_mask = BIT(0),
2264 .hw.init = &(struct clk_init_data){
2265 .name = "gcc_pdm_ahb_clk",
2266 .parent_names = (const char *[]){
2267 "pcnoc_bfdcd_clk_src",
2270 .flags = CLK_SET_RATE_PARENT,
2271 .ops = &clk_branch2_ops,
2276 static struct clk_branch gcc_prng_ahb_clk = {
2277 .halt_reg = 0x13004,
2278 .halt_check = BRANCH_HALT_VOTED,
2280 .enable_reg = 0x45004,
2281 .enable_mask = BIT(8),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gcc_prng_ahb_clk",
2284 .parent_names = (const char *[]){
2285 "pcnoc_bfdcd_clk_src",
2288 .ops = &clk_branch2_ops,
2293 static struct clk_branch gcc_sdcc1_ahb_clk = {
2294 .halt_reg = 0x4201c,
2296 .enable_reg = 0x4201c,
2297 .enable_mask = BIT(0),
2298 .hw.init = &(struct clk_init_data){
2299 .name = "gcc_sdcc1_ahb_clk",
2300 .parent_names = (const char *[]){
2301 "pcnoc_bfdcd_clk_src",
2304 .flags = CLK_SET_RATE_PARENT,
2305 .ops = &clk_branch2_ops,
2310 static struct clk_branch gcc_sdcc1_apps_clk = {
2311 .halt_reg = 0x42018,
2313 .enable_reg = 0x42018,
2314 .enable_mask = BIT(0),
2315 .hw.init = &(struct clk_init_data){
2316 .name = "gcc_sdcc1_apps_clk",
2317 .parent_names = (const char *[]){
2318 "sdcc1_apps_clk_src",
2321 .flags = CLK_SET_RATE_PARENT,
2322 .ops = &clk_branch2_ops,
2327 static struct clk_branch gcc_sdcc2_ahb_clk = {
2328 .halt_reg = 0x4301c,
2330 .enable_reg = 0x4301c,
2331 .enable_mask = BIT(0),
2332 .hw.init = &(struct clk_init_data){
2333 .name = "gcc_sdcc2_ahb_clk",
2334 .parent_names = (const char *[]){
2335 "pcnoc_bfdcd_clk_src",
2338 .flags = CLK_SET_RATE_PARENT,
2339 .ops = &clk_branch2_ops,
2344 static struct clk_branch gcc_sdcc2_apps_clk = {
2345 .halt_reg = 0x43018,
2347 .enable_reg = 0x43018,
2348 .enable_mask = BIT(0),
2349 .hw.init = &(struct clk_init_data){
2350 .name = "gcc_sdcc2_apps_clk",
2351 .parent_names = (const char *[]){
2352 "sdcc2_apps_clk_src",
2355 .flags = CLK_SET_RATE_PARENT,
2356 .ops = &clk_branch2_ops,
2361 static struct clk_branch gcc_gtcu_ahb_clk = {
2362 .halt_reg = 0x12044,
2364 .enable_reg = 0x4500c,
2365 .enable_mask = BIT(13),
2366 .hw.init = &(struct clk_init_data){
2367 .name = "gcc_gtcu_ahb_clk",
2368 .parent_names = (const char *[]){
2369 "pcnoc_bfdcd_clk_src",
2372 .flags = CLK_SET_RATE_PARENT,
2373 .ops = &clk_branch2_ops,
2378 static struct clk_branch gcc_jpeg_tbu_clk = {
2379 .halt_reg = 0x12034,
2381 .enable_reg = 0x4500c,
2382 .enable_mask = BIT(10),
2383 .hw.init = &(struct clk_init_data){
2384 .name = "gcc_jpeg_tbu_clk",
2385 .parent_names = (const char *[]){
2386 "system_noc_bfdcd_clk_src",
2389 .flags = CLK_SET_RATE_PARENT,
2390 .ops = &clk_branch2_ops,
2395 static struct clk_branch gcc_mdp_tbu_clk = {
2396 .halt_reg = 0x1201c,
2398 .enable_reg = 0x4500c,
2399 .enable_mask = BIT(4),
2400 .hw.init = &(struct clk_init_data){
2401 .name = "gcc_mdp_tbu_clk",
2402 .parent_names = (const char *[]){
2403 "system_noc_bfdcd_clk_src",
2406 .flags = CLK_SET_RATE_PARENT,
2407 .ops = &clk_branch2_ops,
2412 static struct clk_branch gcc_smmu_cfg_clk = {
2413 .halt_reg = 0x12038,
2415 .enable_reg = 0x4500c,
2416 .enable_mask = BIT(12),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_smmu_cfg_clk",
2419 .parent_names = (const char *[]){
2420 "pcnoc_bfdcd_clk_src",
2423 .flags = CLK_SET_RATE_PARENT,
2424 .ops = &clk_branch2_ops,
2429 static struct clk_branch gcc_venus_tbu_clk = {
2430 .halt_reg = 0x12014,
2432 .enable_reg = 0x4500c,
2433 .enable_mask = BIT(5),
2434 .hw.init = &(struct clk_init_data){
2435 .name = "gcc_venus_tbu_clk",
2436 .parent_names = (const char *[]){
2437 "system_noc_bfdcd_clk_src",
2440 .flags = CLK_SET_RATE_PARENT,
2441 .ops = &clk_branch2_ops,
2446 static struct clk_branch gcc_vfe_tbu_clk = {
2447 .halt_reg = 0x1203c,
2449 .enable_reg = 0x4500c,
2450 .enable_mask = BIT(9),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "gcc_vfe_tbu_clk",
2453 .parent_names = (const char *[]){
2454 "system_noc_bfdcd_clk_src",
2457 .flags = CLK_SET_RATE_PARENT,
2458 .ops = &clk_branch2_ops,
2463 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2464 .halt_reg = 0x4102c,
2466 .enable_reg = 0x4102c,
2467 .enable_mask = BIT(0),
2468 .hw.init = &(struct clk_init_data){
2469 .name = "gcc_usb2a_phy_sleep_clk",
2470 .parent_names = (const char *[]){
2474 .flags = CLK_SET_RATE_PARENT,
2475 .ops = &clk_branch2_ops,
2480 static struct clk_branch gcc_usb_hs_ahb_clk = {
2481 .halt_reg = 0x41008,
2483 .enable_reg = 0x41008,
2484 .enable_mask = BIT(0),
2485 .hw.init = &(struct clk_init_data){
2486 .name = "gcc_usb_hs_ahb_clk",
2487 .parent_names = (const char *[]){
2488 "pcnoc_bfdcd_clk_src",
2491 .flags = CLK_SET_RATE_PARENT,
2492 .ops = &clk_branch2_ops,
2497 static struct clk_branch gcc_usb_hs_system_clk = {
2498 .halt_reg = 0x41004,
2500 .enable_reg = 0x41004,
2501 .enable_mask = BIT(0),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gcc_usb_hs_system_clk",
2504 .parent_names = (const char *[]){
2505 "usb_hs_system_clk_src",
2508 .flags = CLK_SET_RATE_PARENT,
2509 .ops = &clk_branch2_ops,
2514 static struct clk_branch gcc_venus0_ahb_clk = {
2515 .halt_reg = 0x4c020,
2517 .enable_reg = 0x4c020,
2518 .enable_mask = BIT(0),
2519 .hw.init = &(struct clk_init_data){
2520 .name = "gcc_venus0_ahb_clk",
2521 .parent_names = (const char *[]){
2522 "pcnoc_bfdcd_clk_src",
2525 .flags = CLK_SET_RATE_PARENT,
2526 .ops = &clk_branch2_ops,
2531 static struct clk_branch gcc_venus0_axi_clk = {
2532 .halt_reg = 0x4c024,
2534 .enable_reg = 0x4c024,
2535 .enable_mask = BIT(0),
2536 .hw.init = &(struct clk_init_data){
2537 .name = "gcc_venus0_axi_clk",
2538 .parent_names = (const char *[]){
2539 "system_noc_bfdcd_clk_src",
2542 .flags = CLK_SET_RATE_PARENT,
2543 .ops = &clk_branch2_ops,
2548 static struct clk_branch gcc_venus0_vcodec0_clk = {
2549 .halt_reg = 0x4c01c,
2551 .enable_reg = 0x4c01c,
2552 .enable_mask = BIT(0),
2553 .hw.init = &(struct clk_init_data){
2554 .name = "gcc_venus0_vcodec0_clk",
2555 .parent_names = (const char *[]){
2559 .flags = CLK_SET_RATE_PARENT,
2560 .ops = &clk_branch2_ops,
2565 static struct clk_regmap *gcc_msm8916_clocks[] = {
2566 [GPLL0] = &gpll0.clkr,
2567 [GPLL0_VOTE] = &gpll0_vote,
2568 [BIMC_PLL] = &bimc_pll.clkr,
2569 [BIMC_PLL_VOTE] = &bimc_pll_vote,
2570 [GPLL1] = &gpll1.clkr,
2571 [GPLL1_VOTE] = &gpll1_vote,
2572 [GPLL2] = &gpll2.clkr,
2573 [GPLL2_VOTE] = &gpll2_vote,
2574 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
2575 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
2576 [CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
2577 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2578 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2579 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2580 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2581 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2582 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2583 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2584 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2585 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2586 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2587 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2588 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2589 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2590 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2591 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2592 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2593 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2594 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2595 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2596 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2597 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2598 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2599 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2600 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2601 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2602 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2603 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2604 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2605 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
2606 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2607 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2608 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2609 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2610 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2611 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2612 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2613 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2614 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2615 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2616 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2617 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
2618 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2619 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2620 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2621 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2622 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2623 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2624 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2625 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2626 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2627 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2628 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2629 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2630 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2631 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2632 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2633 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2634 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2635 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2636 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2637 [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
2638 [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
2639 [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
2640 [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
2641 [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr,
2642 [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
2643 [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
2644 [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
2645 [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
2646 [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr,
2647 [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
2648 [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
2649 [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
2650 [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
2651 [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
2652 [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
2653 [GCC_CAMSS_JPEG0_CLK] = &gcc_camss_jpeg0_clk.clkr,
2654 [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
2655 [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
2656 [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
2657 [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
2658 [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
2659 [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
2660 [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
2661 [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr,
2662 [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
2663 [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
2664 [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
2665 [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
2666 [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr,
2667 [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr,
2668 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2669 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2670 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2671 [GCC_OXILI_GMEM_CLK] = &gcc_oxili_gmem_clk.clkr,
2672 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2673 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2674 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2675 [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2676 [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2677 [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2678 [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2679 [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2680 [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2681 [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2682 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2683 [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2684 [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2685 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2686 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2687 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2688 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2689 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2690 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2691 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2692 [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2693 [GCC_JPEG_TBU_CLK] = &gcc_jpeg_tbu_clk.clkr,
2694 [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2695 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2696 [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr,
2697 [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr,
2698 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2699 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2700 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2701 [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
2702 [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
2703 [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
2706 static const struct qcom_reset_map gcc_msm8916_resets[] = {
2707 [GCC_BLSP1_BCR] = { 0x01000 },
2708 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
2709 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
2710 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
2711 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
2712 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
2713 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
2714 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
2715 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
2716 [GCC_IMEM_BCR] = { 0x0e000 },
2717 [GCC_SMMU_BCR] = { 0x12000 },
2718 [GCC_APSS_TCU_BCR] = { 0x12050 },
2719 [GCC_SMMU_XPU_BCR] = { 0x12054 },
2720 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
2721 [GCC_PRNG_BCR] = { 0x13000 },
2722 [GCC_BOOT_ROM_BCR] = { 0x13008 },
2723 [GCC_CRYPTO_BCR] = { 0x16000 },
2724 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
2725 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
2726 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
2727 [GCC_DEHR_BCR] = { 0x1f000 },
2728 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
2729 [GCC_PCNOC_BCR] = { 0x27018 },
2730 [GCC_TCSR_BCR] = { 0x28000 },
2731 [GCC_QDSS_BCR] = { 0x29000 },
2732 [GCC_DCD_BCR] = { 0x2a000 },
2733 [GCC_MSG_RAM_BCR] = { 0x2b000 },
2734 [GCC_MPM_BCR] = { 0x2c000 },
2735 [GCC_SPMI_BCR] = { 0x2e000 },
2736 [GCC_SPDM_BCR] = { 0x2f000 },
2737 [GCC_MM_SPDM_BCR] = { 0x2f024 },
2738 [GCC_BIMC_BCR] = { 0x31000 },
2739 [GCC_RBCPR_BCR] = { 0x33000 },
2740 [GCC_TLMM_BCR] = { 0x34000 },
2741 [GCC_USB_HS_BCR] = { 0x41000 },
2742 [GCC_USB2A_PHY_BCR] = { 0x41028 },
2743 [GCC_SDCC1_BCR] = { 0x42000 },
2744 [GCC_SDCC2_BCR] = { 0x43000 },
2745 [GCC_PDM_BCR] = { 0x44000 },
2746 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
2747 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
2748 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
2749 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
2750 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
2751 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
2752 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
2753 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
2754 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
2755 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
2756 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
2757 [GCC_MMSS_BCR] = { 0x4b000 },
2758 [GCC_VENUS0_BCR] = { 0x4c014 },
2759 [GCC_MDSS_BCR] = { 0x4d074 },
2760 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
2761 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
2762 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
2763 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
2764 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
2765 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
2766 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
2767 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
2768 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
2769 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
2770 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
2771 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
2772 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
2773 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
2774 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
2775 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
2776 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
2777 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
2778 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
2779 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
2780 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
2781 [GCC_OXILI_BCR] = { 0x59018 },
2782 [GCC_GMEM_BCR] = { 0x5902c },
2783 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
2784 [GCC_MDP_TBU_BCR] = { 0x62000 },
2785 [GCC_GFX_TBU_BCR] = { 0x63000 },
2786 [GCC_GFX_TCU_BCR] = { 0x64000 },
2787 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
2788 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
2789 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
2790 [GCC_GTCU_AHB_BCR] = { 0x68000 },
2791 [GCC_SMMU_CFG_BCR] = { 0x69000 },
2792 [GCC_VFE_TBU_BCR] = { 0x6a000 },
2793 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
2794 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
2795 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
2796 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
2799 static const struct regmap_config gcc_msm8916_regmap_config = {
2803 .max_register = 0x80000,
2807 static const struct qcom_cc_desc gcc_msm8916_desc = {
2808 .config = &gcc_msm8916_regmap_config,
2809 .clks = gcc_msm8916_clocks,
2810 .num_clks = ARRAY_SIZE(gcc_msm8916_clocks),
2811 .resets = gcc_msm8916_resets,
2812 .num_resets = ARRAY_SIZE(gcc_msm8916_resets),
2815 static const struct of_device_id gcc_msm8916_match_table[] = {
2816 { .compatible = "qcom,gcc-msm8916" },
2819 MODULE_DEVICE_TABLE(of, gcc_msm8916_match_table);
2821 static int gcc_msm8916_probe(struct platform_device *pdev)
2824 struct device *dev = &pdev->dev;
2826 /* Temporary until RPM clocks supported */
2827 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
2829 return PTR_ERR(clk);
2831 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
2832 CLK_IS_ROOT, 32768);
2834 return PTR_ERR(clk);
2836 return qcom_cc_probe(pdev, &gcc_msm8916_desc);
2839 static int gcc_msm8916_remove(struct platform_device *pdev)
2841 qcom_cc_remove(pdev);
2845 static struct platform_driver gcc_msm8916_driver = {
2846 .probe = gcc_msm8916_probe,
2847 .remove = gcc_msm8916_remove,
2849 .name = "gcc-msm8916",
2850 .of_match_table = gcc_msm8916_match_table,
2854 static int __init gcc_msm8916_init(void)
2856 return platform_driver_register(&gcc_msm8916_driver);
2858 core_initcall(gcc_msm8916_init);
2860 static void __exit gcc_msm8916_exit(void)
2862 platform_driver_unregister(&gcc_msm8916_driver);
2864 module_exit(gcc_msm8916_exit);
2866 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
2867 MODULE_LICENSE("GPL v2");
2868 MODULE_ALIAS("platform:gcc-msm8916");