2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/export.h>
18 #include <linux/clk-provider.h>
19 #include <linux/regmap.h>
21 #include <asm/div64.h>
26 static u32 ns_to_src(struct src_sel *s, u32 ns)
28 ns >>= s->src_sel_shift;
33 static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
38 mask <<= s->src_sel_shift;
41 ns |= src << s->src_sel_shift;
45 static u8 clk_rcg_get_parent(struct clk_hw *hw)
47 struct clk_rcg *rcg = to_clk_rcg(hw);
48 int num_parents = __clk_get_num_parents(hw->clk);
52 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
55 ns = ns_to_src(&rcg->s, ns);
56 for (i = 0; i < num_parents; i++)
57 if (ns == rcg->s.parent_map[i].cfg)
61 pr_debug("%s: Clock %s has invalid parent, using default.\n",
62 __func__, __clk_get_name(hw->clk));
66 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
68 bank &= BIT(rcg->mux_sel_bit);
72 static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
74 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
75 int num_parents = __clk_get_num_parents(hw->clk);
81 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
84 bank = reg_to_bank(rcg, reg);
87 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
90 ns = ns_to_src(s, ns);
92 for (i = 0; i < num_parents; i++)
93 if (ns == s->parent_map[i].cfg)
97 pr_debug("%s: Clock %s has invalid parent, using default.\n",
98 __func__, __clk_get_name(hw->clk));
102 static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
104 struct clk_rcg *rcg = to_clk_rcg(hw);
107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
108 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
114 static u32 md_to_m(struct mn *mn, u32 md)
116 md >>= mn->m_val_shift;
117 md &= BIT(mn->width) - 1;
121 static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
123 ns >>= p->pre_div_shift;
124 ns &= BIT(p->pre_div_width) - 1;
128 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
132 mask = BIT(p->pre_div_width) - 1;
133 mask <<= p->pre_div_shift;
136 ns |= pre_div << p->pre_div_shift;
140 static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
144 mask_w = BIT(mn->width) - 1;
145 mask = (mask_w << mn->m_val_shift) | mask_w;
149 m <<= mn->m_val_shift;
157 static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
159 ns = ~ns >> mn->n_val_shift;
160 ns &= BIT(mn->width) - 1;
164 static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
166 val >>= mn->mnctr_mode_shift;
167 val &= MNCTR_MODE_MASK;
171 static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
175 mask = BIT(mn->width) - 1;
176 mask <<= mn->n_val_shift;
182 n &= BIT(mn->width) - 1;
183 n <<= mn->n_val_shift;
190 static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
194 mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
195 mask |= BIT(mn->mnctr_en_bit);
199 val |= BIT(mn->mnctr_en_bit);
200 val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
206 static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
209 int bank, new_bank, ret, index;
215 bool banked_mn = !!rcg->mn[1].width;
216 bool banked_p = !!rcg->p[1].pre_div_width;
217 struct clk_hw *hw = &rcg->clkr.hw;
219 enabled = __clk_is_enabled(hw->clk);
221 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
224 bank = reg_to_bank(rcg, reg);
225 new_bank = enabled ? !bank : bank;
227 ns_reg = rcg->ns_reg[new_bank];
228 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
233 mn = &rcg->mn[new_bank];
234 md_reg = rcg->md_reg[new_bank];
236 ns |= BIT(mn->mnctr_reset_bit);
237 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
241 ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
244 md = mn_to_md(mn, f->m, f->n, md);
245 ret = regmap_write(rcg->clkr.regmap, md_reg, md);
248 ns = mn_to_ns(mn, f->m, f->n, ns);
249 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
253 /* Two NS registers means mode control is in NS register */
254 if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
255 ns = mn_to_reg(mn, f->m, f->n, ns);
256 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
260 reg = mn_to_reg(mn, f->m, f->n, reg);
261 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
267 ns &= ~BIT(mn->mnctr_reset_bit);
268 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
274 p = &rcg->p[new_bank];
275 ns = pre_div_to_ns(p, f->pre_div - 1, ns);
278 s = &rcg->s[new_bank];
279 index = qcom_find_src_index(hw, s->parent_map, f->src);
282 ns = src_to_ns(s, s->parent_map[index].cfg, ns);
283 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
288 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
291 reg ^= BIT(rcg->mux_sel_bit);
292 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
299 static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
301 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
304 struct freq_tbl f = { 0 };
305 bool banked_mn = !!rcg->mn[1].width;
306 bool banked_p = !!rcg->p[1].pre_div_width;
308 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
309 bank = reg_to_bank(rcg, reg);
311 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
314 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
315 f.m = md_to_m(&rcg->mn[bank], md);
316 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
320 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
322 f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
323 return configure_bank(rcg, &f);
327 * Calculate m/n:d rate
330 * rate = ----------- x ---
334 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
350 clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
352 struct clk_rcg *rcg = to_clk_rcg(hw);
353 u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
354 struct mn *mn = &rcg->mn;
356 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
357 pre_div = ns_to_pre_div(&rcg->p, ns);
360 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
362 n = ns_m_to_n(mn, ns, m);
363 /* MN counter mode is in hw.enable_reg sometimes */
364 if (rcg->clkr.enable_reg != rcg->ns_reg)
365 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
368 mode = reg_to_mnctr_mode(mn, mode);
371 return calc_rate(parent_rate, m, n, mode, pre_div);
375 clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
377 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
378 u32 m, n, pre_div, ns, md, mode, reg;
381 bool banked_p = !!rcg->p[1].pre_div_width;
382 bool banked_mn = !!rcg->mn[1].width;
384 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
385 bank = reg_to_bank(rcg, reg);
387 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
388 m = n = pre_div = mode = 0;
392 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
394 n = ns_m_to_n(mn, ns, m);
395 /* Two NS registers means mode control is in NS register */
396 if (rcg->ns_reg[0] != rcg->ns_reg[1])
398 mode = reg_to_mnctr_mode(mn, reg);
402 pre_div = ns_to_pre_div(&rcg->p[bank], ns);
404 return calc_rate(parent_rate, m, n, mode, pre_div);
407 static long _freq_tbl_determine_rate(struct clk_hw *hw,
408 const struct freq_tbl *f, unsigned long rate,
409 unsigned long min_rate, unsigned long max_rate,
410 unsigned long *p_rate, struct clk_hw **p_hw,
411 const struct parent_map *parent_map)
413 unsigned long clk_flags;
417 f = qcom_find_freq(f, rate);
421 index = qcom_find_src_index(hw, parent_map, f->src);
425 clk_flags = __clk_get_flags(hw->clk);
426 p = clk_get_parent_by_index(hw->clk, index);
427 if (clk_flags & CLK_SET_RATE_PARENT) {
428 rate = rate * f->pre_div;
436 rate = __clk_get_rate(p);
438 *p_hw = __clk_get_hw(p);
444 static long clk_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
445 unsigned long min_rate, unsigned long max_rate,
446 unsigned long *p_rate, struct clk_hw **p)
448 struct clk_rcg *rcg = to_clk_rcg(hw);
450 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
451 max_rate, p_rate, p, rcg->s.parent_map);
454 static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
455 unsigned long min_rate, unsigned long max_rate,
456 unsigned long *p_rate, struct clk_hw **p)
458 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
463 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
464 bank = reg_to_bank(rcg, reg);
467 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, min_rate,
468 max_rate, p_rate, p, s->parent_map);
471 static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
472 unsigned long min_rate, unsigned long max_rate,
473 unsigned long *p_rate, struct clk_hw **p_hw)
475 struct clk_rcg *rcg = to_clk_rcg(hw);
476 const struct freq_tbl *f = rcg->freq_tbl;
478 int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
480 p = clk_get_parent_by_index(hw->clk, index);
481 *p_hw = __clk_get_hw(p);
482 *p_rate = __clk_round_rate(p, rate);
487 static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
490 struct mn *mn = &rcg->mn;
492 unsigned int reset_reg;
494 if (rcg->mn.reset_in_cc)
495 reset_reg = rcg->clkr.enable_reg;
497 reset_reg = rcg->ns_reg;
500 mask = BIT(mn->mnctr_reset_bit);
501 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
503 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
504 md = mn_to_md(mn, f->m, f->n, md);
505 regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
507 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
508 /* MN counter mode is in hw.enable_reg sometimes */
509 if (rcg->clkr.enable_reg != rcg->ns_reg) {
510 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
511 ctl = mn_to_reg(mn, f->m, f->n, ctl);
512 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
514 ns = mn_to_reg(mn, f->m, f->n, ns);
516 ns = mn_to_ns(mn, f->m, f->n, ns);
518 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
521 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
522 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
524 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
529 static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
530 unsigned long parent_rate)
532 struct clk_rcg *rcg = to_clk_rcg(hw);
533 const struct freq_tbl *f;
535 f = qcom_find_freq(rcg->freq_tbl, rate);
539 return __clk_rcg_set_rate(rcg, f);
542 static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
543 unsigned long parent_rate)
545 struct clk_rcg *rcg = to_clk_rcg(hw);
547 return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
551 * This type of clock has a glitch-free mux that switches between the output of
552 * the M/N counter and an always on clock source (XO). When clk_set_rate() is
553 * called we need to make sure that we don't switch to the M/N counter if it
554 * isn't clocking because the mux will get stuck and the clock will stop
555 * outputting a clock. This can happen if the framework isn't aware that this
556 * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
557 * this we switch the mux in the enable/disable ops and reprogram the M/N
558 * counter in the set_rate op. We also make sure to switch away from the M/N
559 * counter in set_rate if software thinks the clock is off.
561 static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
562 unsigned long parent_rate)
564 struct clk_rcg *rcg = to_clk_rcg(hw);
565 const struct freq_tbl *f;
569 f = qcom_find_freq(rcg->freq_tbl, rate);
573 /* Switch to XO to avoid glitches */
574 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
575 ret = __clk_rcg_set_rate(rcg, f);
576 /* Switch back to M/N if it's clocking */
577 if (__clk_is_enabled(hw->clk))
578 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
583 static int clk_rcg_lcc_enable(struct clk_hw *hw)
585 struct clk_rcg *rcg = to_clk_rcg(hw);
589 return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
592 static void clk_rcg_lcc_disable(struct clk_hw *hw)
594 struct clk_rcg *rcg = to_clk_rcg(hw);
598 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
601 static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
603 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
604 const struct freq_tbl *f;
606 f = qcom_find_freq(rcg->freq_tbl, rate);
610 return configure_bank(rcg, f);
613 static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
614 unsigned long parent_rate)
616 return __clk_dyn_rcg_set_rate(hw, rate);
619 static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
620 unsigned long rate, unsigned long parent_rate, u8 index)
622 return __clk_dyn_rcg_set_rate(hw, rate);
625 const struct clk_ops clk_rcg_ops = {
626 .enable = clk_enable_regmap,
627 .disable = clk_disable_regmap,
628 .get_parent = clk_rcg_get_parent,
629 .set_parent = clk_rcg_set_parent,
630 .recalc_rate = clk_rcg_recalc_rate,
631 .determine_rate = clk_rcg_determine_rate,
632 .set_rate = clk_rcg_set_rate,
634 EXPORT_SYMBOL_GPL(clk_rcg_ops);
636 const struct clk_ops clk_rcg_bypass_ops = {
637 .enable = clk_enable_regmap,
638 .disable = clk_disable_regmap,
639 .get_parent = clk_rcg_get_parent,
640 .set_parent = clk_rcg_set_parent,
641 .recalc_rate = clk_rcg_recalc_rate,
642 .determine_rate = clk_rcg_bypass_determine_rate,
643 .set_rate = clk_rcg_bypass_set_rate,
645 EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
647 const struct clk_ops clk_rcg_lcc_ops = {
648 .enable = clk_rcg_lcc_enable,
649 .disable = clk_rcg_lcc_disable,
650 .get_parent = clk_rcg_get_parent,
651 .set_parent = clk_rcg_set_parent,
652 .recalc_rate = clk_rcg_recalc_rate,
653 .determine_rate = clk_rcg_determine_rate,
654 .set_rate = clk_rcg_lcc_set_rate,
656 EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
658 const struct clk_ops clk_dyn_rcg_ops = {
659 .enable = clk_enable_regmap,
660 .is_enabled = clk_is_enabled_regmap,
661 .disable = clk_disable_regmap,
662 .get_parent = clk_dyn_rcg_get_parent,
663 .set_parent = clk_dyn_rcg_set_parent,
664 .recalc_rate = clk_dyn_rcg_recalc_rate,
665 .determine_rate = clk_dyn_rcg_determine_rate,
666 .set_rate = clk_dyn_rcg_set_rate,
667 .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
669 EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);