2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/export.h>
18 #include <linux/clk-provider.h>
19 #include <linux/regmap.h>
21 #include <asm/div64.h>
26 static u32 ns_to_src(struct src_sel *s, u32 ns)
28 ns >>= s->src_sel_shift;
33 static u32 src_to_ns(struct src_sel *s, u8 src, u32 ns)
38 mask <<= s->src_sel_shift;
41 ns |= src << s->src_sel_shift;
45 static u8 clk_rcg_get_parent(struct clk_hw *hw)
47 struct clk_rcg *rcg = to_clk_rcg(hw);
48 int num_parents = __clk_get_num_parents(hw->clk);
52 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
55 ns = ns_to_src(&rcg->s, ns);
56 for (i = 0; i < num_parents; i++)
57 if (ns == rcg->s.parent_map[i].cfg)
61 pr_debug("%s: Clock %s has invalid parent, using default.\n",
62 __func__, __clk_get_name(hw->clk));
66 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
68 bank &= BIT(rcg->mux_sel_bit);
72 static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
74 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
75 int num_parents = __clk_get_num_parents(hw->clk);
81 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
84 bank = reg_to_bank(rcg, reg);
87 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
90 ns = ns_to_src(s, ns);
92 for (i = 0; i < num_parents; i++)
93 if (ns == s->parent_map[i].cfg)
97 pr_debug("%s: Clock %s has invalid parent, using default.\n",
98 __func__, __clk_get_name(hw->clk));
102 static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
104 struct clk_rcg *rcg = to_clk_rcg(hw);
107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
108 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
114 static u32 md_to_m(struct mn *mn, u32 md)
116 md >>= mn->m_val_shift;
117 md &= BIT(mn->width) - 1;
121 static u32 ns_to_pre_div(struct pre_div *p, u32 ns)
123 ns >>= p->pre_div_shift;
124 ns &= BIT(p->pre_div_width) - 1;
128 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns)
132 mask = BIT(p->pre_div_width) - 1;
133 mask <<= p->pre_div_shift;
136 ns |= pre_div << p->pre_div_shift;
140 static u32 mn_to_md(struct mn *mn, u32 m, u32 n, u32 md)
144 mask_w = BIT(mn->width) - 1;
145 mask = (mask_w << mn->m_val_shift) | mask_w;
149 m <<= mn->m_val_shift;
157 static u32 ns_m_to_n(struct mn *mn, u32 ns, u32 m)
159 ns = ~ns >> mn->n_val_shift;
160 ns &= BIT(mn->width) - 1;
164 static u32 reg_to_mnctr_mode(struct mn *mn, u32 val)
166 val >>= mn->mnctr_mode_shift;
167 val &= MNCTR_MODE_MASK;
171 static u32 mn_to_ns(struct mn *mn, u32 m, u32 n, u32 ns)
175 mask = BIT(mn->width) - 1;
176 mask <<= mn->n_val_shift;
182 n &= BIT(mn->width) - 1;
183 n <<= mn->n_val_shift;
190 static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
194 mask = MNCTR_MODE_MASK << mn->mnctr_mode_shift;
195 mask |= BIT(mn->mnctr_en_bit);
199 val |= BIT(mn->mnctr_en_bit);
200 val |= MNCTR_MODE_DUAL << mn->mnctr_mode_shift;
206 static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
209 int bank, new_bank, ret, index;
215 bool banked_mn = !!rcg->mn[1].width;
216 bool banked_p = !!rcg->p[1].pre_div_width;
217 struct clk_hw *hw = &rcg->clkr.hw;
219 enabled = __clk_is_enabled(hw->clk);
221 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
224 bank = reg_to_bank(rcg, reg);
225 new_bank = enabled ? !bank : bank;
227 ns_reg = rcg->ns_reg[new_bank];
228 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
233 mn = &rcg->mn[new_bank];
234 md_reg = rcg->md_reg[new_bank];
236 ns |= BIT(mn->mnctr_reset_bit);
237 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
241 ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
244 md = mn_to_md(mn, f->m, f->n, md);
245 ret = regmap_write(rcg->clkr.regmap, md_reg, md);
248 ns = mn_to_ns(mn, f->m, f->n, ns);
249 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
253 /* Two NS registers means mode control is in NS register */
254 if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
255 ns = mn_to_reg(mn, f->m, f->n, ns);
256 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
260 reg = mn_to_reg(mn, f->m, f->n, reg);
261 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
267 ns &= ~BIT(mn->mnctr_reset_bit);
268 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
274 p = &rcg->p[new_bank];
275 ns = pre_div_to_ns(p, f->pre_div - 1, ns);
278 s = &rcg->s[new_bank];
279 index = qcom_find_src_index(hw, s->parent_map, f->src);
282 ns = src_to_ns(s, s->parent_map[index].cfg, ns);
283 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
288 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
291 reg ^= BIT(rcg->mux_sel_bit);
292 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
299 static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
301 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
304 struct freq_tbl f = { 0 };
305 bool banked_mn = !!rcg->mn[1].width;
306 bool banked_p = !!rcg->p[1].pre_div_width;
308 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
309 bank = reg_to_bank(rcg, reg);
311 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
314 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
315 f.m = md_to_m(&rcg->mn[bank], md);
316 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
320 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
322 f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
323 return configure_bank(rcg, &f);
327 * Calculate m/n:d rate
330 * rate = ----------- x ---
334 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
350 clk_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
352 struct clk_rcg *rcg = to_clk_rcg(hw);
353 u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
354 struct mn *mn = &rcg->mn;
356 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
357 pre_div = ns_to_pre_div(&rcg->p, ns);
360 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
362 n = ns_m_to_n(mn, ns, m);
363 /* MN counter mode is in hw.enable_reg sometimes */
364 if (rcg->clkr.enable_reg != rcg->ns_reg)
365 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
368 mode = reg_to_mnctr_mode(mn, mode);
371 return calc_rate(parent_rate, m, n, mode, pre_div);
375 clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
377 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
378 u32 m, n, pre_div, ns, md, mode, reg;
381 bool banked_p = !!rcg->p[1].pre_div_width;
382 bool banked_mn = !!rcg->mn[1].width;
384 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
385 bank = reg_to_bank(rcg, reg);
387 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
388 m = n = pre_div = mode = 0;
392 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
394 n = ns_m_to_n(mn, ns, m);
395 /* Two NS registers means mode control is in NS register */
396 if (rcg->ns_reg[0] != rcg->ns_reg[1])
398 mode = reg_to_mnctr_mode(mn, reg);
402 pre_div = ns_to_pre_div(&rcg->p[bank], ns);
404 return calc_rate(parent_rate, m, n, mode, pre_div);
407 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
408 struct clk_rate_request *req,
409 const struct parent_map *parent_map)
411 unsigned long clk_flags, rate = req->rate;
415 f = qcom_find_freq(f, rate);
419 index = qcom_find_src_index(hw, parent_map, f->src);
423 clk_flags = __clk_get_flags(hw->clk);
424 p = clk_get_parent_by_index(hw->clk, index);
425 if (clk_flags & CLK_SET_RATE_PARENT) {
426 rate = rate * f->pre_div;
434 rate = __clk_get_rate(p);
436 req->best_parent_hw = __clk_get_hw(p);
437 req->best_parent_rate = rate;
443 static int clk_rcg_determine_rate(struct clk_hw *hw,
444 struct clk_rate_request *req)
446 struct clk_rcg *rcg = to_clk_rcg(hw);
448 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,
452 static int clk_dyn_rcg_determine_rate(struct clk_hw *hw,
453 struct clk_rate_request *req)
455 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
460 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
461 bank = reg_to_bank(rcg, reg);
464 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);
467 static int clk_rcg_bypass_determine_rate(struct clk_hw *hw,
468 struct clk_rate_request *req)
470 struct clk_rcg *rcg = to_clk_rcg(hw);
471 const struct freq_tbl *f = rcg->freq_tbl;
473 int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
475 p = clk_get_parent_by_index(hw->clk, index);
476 req->best_parent_hw = __clk_get_hw(p);
477 req->best_parent_rate = __clk_round_rate(p, req->rate);
478 req->rate = req->best_parent_rate;
483 static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
486 struct mn *mn = &rcg->mn;
488 unsigned int reset_reg;
490 if (rcg->mn.reset_in_cc)
491 reset_reg = rcg->clkr.enable_reg;
493 reset_reg = rcg->ns_reg;
496 mask = BIT(mn->mnctr_reset_bit);
497 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
499 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
500 md = mn_to_md(mn, f->m, f->n, md);
501 regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
503 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
504 /* MN counter mode is in hw.enable_reg sometimes */
505 if (rcg->clkr.enable_reg != rcg->ns_reg) {
506 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
507 ctl = mn_to_reg(mn, f->m, f->n, ctl);
508 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
510 ns = mn_to_reg(mn, f->m, f->n, ns);
512 ns = mn_to_ns(mn, f->m, f->n, ns);
514 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
517 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
518 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
520 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
525 static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
526 unsigned long parent_rate)
528 struct clk_rcg *rcg = to_clk_rcg(hw);
529 const struct freq_tbl *f;
531 f = qcom_find_freq(rcg->freq_tbl, rate);
535 return __clk_rcg_set_rate(rcg, f);
538 static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
539 unsigned long parent_rate)
541 struct clk_rcg *rcg = to_clk_rcg(hw);
543 return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
547 * This type of clock has a glitch-free mux that switches between the output of
548 * the M/N counter and an always on clock source (XO). When clk_set_rate() is
549 * called we need to make sure that we don't switch to the M/N counter if it
550 * isn't clocking because the mux will get stuck and the clock will stop
551 * outputting a clock. This can happen if the framework isn't aware that this
552 * clock is on and so clk_set_rate() doesn't turn on the new parent. To fix
553 * this we switch the mux in the enable/disable ops and reprogram the M/N
554 * counter in the set_rate op. We also make sure to switch away from the M/N
555 * counter in set_rate if software thinks the clock is off.
557 static int clk_rcg_lcc_set_rate(struct clk_hw *hw, unsigned long rate,
558 unsigned long parent_rate)
560 struct clk_rcg *rcg = to_clk_rcg(hw);
561 const struct freq_tbl *f;
565 f = qcom_find_freq(rcg->freq_tbl, rate);
569 /* Switch to XO to avoid glitches */
570 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
571 ret = __clk_rcg_set_rate(rcg, f);
572 /* Switch back to M/N if it's clocking */
573 if (__clk_is_enabled(hw->clk))
574 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
579 static int clk_rcg_lcc_enable(struct clk_hw *hw)
581 struct clk_rcg *rcg = to_clk_rcg(hw);
585 return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
588 static void clk_rcg_lcc_disable(struct clk_hw *hw)
590 struct clk_rcg *rcg = to_clk_rcg(hw);
594 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
597 static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
599 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
600 const struct freq_tbl *f;
602 f = qcom_find_freq(rcg->freq_tbl, rate);
606 return configure_bank(rcg, f);
609 static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
610 unsigned long parent_rate)
612 return __clk_dyn_rcg_set_rate(hw, rate);
615 static int clk_dyn_rcg_set_rate_and_parent(struct clk_hw *hw,
616 unsigned long rate, unsigned long parent_rate, u8 index)
618 return __clk_dyn_rcg_set_rate(hw, rate);
621 const struct clk_ops clk_rcg_ops = {
622 .enable = clk_enable_regmap,
623 .disable = clk_disable_regmap,
624 .get_parent = clk_rcg_get_parent,
625 .set_parent = clk_rcg_set_parent,
626 .recalc_rate = clk_rcg_recalc_rate,
627 .determine_rate = clk_rcg_determine_rate,
628 .set_rate = clk_rcg_set_rate,
630 EXPORT_SYMBOL_GPL(clk_rcg_ops);
632 const struct clk_ops clk_rcg_bypass_ops = {
633 .enable = clk_enable_regmap,
634 .disable = clk_disable_regmap,
635 .get_parent = clk_rcg_get_parent,
636 .set_parent = clk_rcg_set_parent,
637 .recalc_rate = clk_rcg_recalc_rate,
638 .determine_rate = clk_rcg_bypass_determine_rate,
639 .set_rate = clk_rcg_bypass_set_rate,
641 EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
643 const struct clk_ops clk_rcg_lcc_ops = {
644 .enable = clk_rcg_lcc_enable,
645 .disable = clk_rcg_lcc_disable,
646 .get_parent = clk_rcg_get_parent,
647 .set_parent = clk_rcg_set_parent,
648 .recalc_rate = clk_rcg_recalc_rate,
649 .determine_rate = clk_rcg_determine_rate,
650 .set_rate = clk_rcg_lcc_set_rate,
652 EXPORT_SYMBOL_GPL(clk_rcg_lcc_ops);
654 const struct clk_ops clk_dyn_rcg_ops = {
655 .enable = clk_enable_regmap,
656 .is_enabled = clk_is_enabled_regmap,
657 .disable = clk_disable_regmap,
658 .get_parent = clk_dyn_rcg_get_parent,
659 .set_parent = clk_dyn_rcg_set_parent,
660 .recalc_rate = clk_dyn_rcg_recalc_rate,
661 .determine_rate = clk_dyn_rcg_determine_rate,
662 .set_rate = clk_dyn_rcg_set_rate,
663 .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent,
665 EXPORT_SYMBOL_GPL(clk_dyn_rcg_ops);