2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/bug.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/clk-provider.h>
21 #include <linux/regmap.h>
23 #include <asm/div64.h>
27 #define PLL_OUTCTRL BIT(0)
28 #define PLL_BYPASSNL BIT(1)
29 #define PLL_RESET_N BIT(2)
30 #define PLL_LOCK_COUNT_SHIFT 8
31 #define PLL_LOCK_COUNT_MASK 0x3f
32 #define PLL_BIAS_COUNT_SHIFT 14
33 #define PLL_BIAS_COUNT_MASK 0x3f
34 #define PLL_VOTE_FSM_ENA BIT(20)
35 #define PLL_VOTE_FSM_RESET BIT(21)
37 static int clk_pll_enable(struct clk_hw *hw)
39 struct clk_pll *pll = to_clk_pll(hw);
43 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
44 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
48 /* Skip if already enabled or in FSM mode */
49 if ((val & mask) == mask || val & PLL_VOTE_FSM_ENA)
52 /* Disable PLL bypass mode. */
53 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
59 * H/W requires a 5us delay between disabling the bypass and
60 * de-asserting the reset. Delay 10us just to be safe.
64 /* De-assert active-low PLL reset. */
65 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
70 /* Wait until PLL is locked. */
73 /* Enable PLL output. */
74 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
78 static void clk_pll_disable(struct clk_hw *hw)
80 struct clk_pll *pll = to_clk_pll(hw);
84 regmap_read(pll->clkr.regmap, pll->mode_reg, &val);
85 /* Skip if in FSM mode */
86 if (val & PLL_VOTE_FSM_ENA)
88 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
89 regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);
93 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
95 struct clk_pll *pll = to_clk_pll(hw);
100 regmap_read(pll->clkr.regmap, pll->l_reg, &l);
101 regmap_read(pll->clkr.regmap, pll->m_reg, &m);
102 regmap_read(pll->clkr.regmap, pll->n_reg, &n);
108 rate = parent_rate * l;
115 if (pll->post_div_width) {
116 regmap_read(pll->clkr.regmap, pll->config_reg, &config);
117 config >>= pll->post_div_shift;
118 config &= BIT(pll->post_div_width) - 1;
126 struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
139 clk_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
141 struct clk *parent = __clk_get_parent(hw->clk);
142 struct clk_pll *pll = to_clk_pll(hw);
143 const struct pll_freq_tbl *f;
145 req->best_parent_hw = __clk_get_hw(parent);
146 req->best_parent_rate = __clk_get_rate(parent);
148 f = find_freq(pll->freq_tbl, req->rate);
150 req->rate = clk_pll_recalc_rate(hw, req->best_parent_rate);
158 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
160 struct clk_pll *pll = to_clk_pll(hw);
161 const struct pll_freq_tbl *f;
164 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
166 f = find_freq(pll->freq_tbl, rate);
170 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
171 enabled = (mode & enable_mask) == enable_mask;
176 regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
177 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
178 regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
179 regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
187 const struct clk_ops clk_pll_ops = {
188 .enable = clk_pll_enable,
189 .disable = clk_pll_disable,
190 .recalc_rate = clk_pll_recalc_rate,
191 .determine_rate = clk_pll_determine_rate,
192 .set_rate = clk_pll_set_rate,
194 EXPORT_SYMBOL_GPL(clk_pll_ops);
196 static int wait_for_pll(struct clk_pll *pll)
201 const char *name = __clk_get_name(pll->clkr.hw.clk);
203 /* Wait for pll to enable. */
204 for (count = 200; count > 0; count--) {
205 ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);
208 if (val & BIT(pll->status_bit))
213 WARN(1, "%s didn't enable after voting for it!\n", name);
217 static int clk_pll_vote_enable(struct clk_hw *hw)
220 struct clk_pll *p = to_clk_pll(__clk_get_hw(__clk_get_parent(hw->clk)));
222 ret = clk_enable_regmap(hw);
226 return wait_for_pll(p);
229 const struct clk_ops clk_pll_vote_ops = {
230 .enable = clk_pll_vote_enable,
231 .disable = clk_disable_regmap,
233 EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
236 clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
241 /* De-assert reset to FSM */
242 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
244 /* Program bias count and lock count */
245 val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
246 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
247 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
248 regmap_update_bits(regmap, pll->mode_reg, mask, val);
250 /* Enable PLL FSM voting */
251 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,
255 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
256 const struct pll_config *config)
261 regmap_write(regmap, pll->l_reg, config->l);
262 regmap_write(regmap, pll->m_reg, config->m);
263 regmap_write(regmap, pll->n_reg, config->n);
265 val = config->vco_val;
266 val |= config->pre_div_val;
267 val |= config->post_div_val;
268 val |= config->mn_ena_mask;
269 val |= config->main_output_mask;
270 val |= config->aux_output_mask;
272 mask = config->vco_mask;
273 mask |= config->pre_div_mask;
274 mask |= config->post_div_mask;
275 mask |= config->mn_ena_mask;
276 mask |= config->main_output_mask;
277 mask |= config->aux_output_mask;
279 regmap_update_bits(regmap, pll->config_reg, mask, val);
282 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
283 const struct pll_config *config, bool fsm_mode)
285 clk_pll_configure(pll, regmap, config);
287 clk_pll_set_fsm_mode(pll, regmap, 8);
289 EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
291 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
292 const struct pll_config *config, bool fsm_mode)
294 clk_pll_configure(pll, regmap, config);
296 clk_pll_set_fsm_mode(pll, regmap, 0);
298 EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
300 static int clk_pll_sr2_enable(struct clk_hw *hw)
302 struct clk_pll *pll = to_clk_pll(hw);
306 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
310 /* Disable PLL bypass mode. */
311 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,
317 * H/W requires a 5us delay between disabling the bypass and
318 * de-asserting the reset. Delay 10us just to be safe.
322 /* De-assert active-low PLL reset. */
323 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,
328 ret = wait_for_pll(pll);
332 /* Enable PLL output. */
333 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,
338 clk_pll_sr2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
340 struct clk_pll *pll = to_clk_pll(hw);
341 const struct pll_freq_tbl *f;
344 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
346 f = find_freq(pll->freq_tbl, rate);
350 regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
351 enabled = (mode & enable_mask) == enable_mask;
356 regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
357 regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
358 regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
361 clk_pll_sr2_enable(hw);
366 const struct clk_ops clk_pll_sr2_ops = {
367 .enable = clk_pll_sr2_enable,
368 .disable = clk_pll_disable,
369 .set_rate = clk_pll_sr2_set_rate,
370 .recalc_rate = clk_pll_recalc_rate,
371 .determine_rate = clk_pll_determine_rate,
373 EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);