drivers/clk/meson/clk-cpu.c

   1 /*
   2  * Copyright (c) 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /*
  19  * CPU clock path:
  20  *
  21  *                           +-[/N]-----|3|
  22  *             MUX2  +--[/3]-+----------|2| MUX1
  23  * [sys_pll]---|1|   |--[/2]------------|1|-|1|
  24  *             | |---+------------------|0| | |----- [a5_clk]
  25  *          +--|0|                          | |
  26  * [xtal]---+-------------------------------|0|
  27  *
  28  *
  29  *
  30  */
  31
  32 #include <linux/delay.h>
  33 #include <linux/err.h>
  34 #include <linux/io.h>
  35 #include <linux/module.h>
  36 #include <linux/of_address.h>
  37 #include <linux/slab.h>
  38 #include <linux/clk-provider.h>
  39
  40 #define MESON_CPU_CLK_CNTL1             0x00
  41 #define MESON_CPU_CLK_CNTL              0x40
  42
  43 #define MESON_CPU_CLK_MUX1              BIT(7)
  44 #define MESON_CPU_CLK_MUX2              BIT(0)
  45
  46 #define MESON_N_WIDTH                   9
  47 #define MESON_N_SHIFT                   20
  48 #define MESON_SEL_WIDTH                 2
  49 #define MESON_SEL_SHIFT                 2
  50
  51 #include "clkc.h"
  52
  53 struct meson_clk_cpu {
  54         struct notifier_block           clk_nb;
  55         const struct clk_div_table      *div_table;
  56         struct clk_hw                   hw;
  57         void __iomem                    *base;
  58         u16                             reg_off;
  59 };
  60 #define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw)
  61 #define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb)
  62
  63 static long meson_clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
  64                                      unsigned long *prate)
  65 {
  66         struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
  67
  68         return divider_round_rate(hw, rate, prate, clk_cpu->div_table,
  69                                   MESON_N_WIDTH, CLK_DIVIDER_ROUND_CLOSEST);
  70 }
  71
  72 static int meson_clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
  73                                   unsigned long parent_rate)
  74 {
  75         struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
  76         unsigned int div, sel, N = 0;
  77         u32 reg;
  78
  79         div = DIV_ROUND_UP(parent_rate, rate);
  80
  81         if (div <= 3) {
  82                 sel = div - 1;
  83         } else {
  84                 sel = 3;
  85                 N = div / 2;
  86         }
  87
  88         reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1);
  89         reg = PARM_SET(MESON_N_WIDTH, MESON_N_SHIFT, reg, N);
  90         writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1);
  91
  92         reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL);
  93         reg = PARM_SET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg, sel);
  94         writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL);
  95
  96         return 0;
  97 }
  98
  99 static unsigned long meson_clk_cpu_recalc_rate(struct clk_hw *hw,
 100                                                unsigned long parent_rate)
 101 {
 102         struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
 103         unsigned int N, sel;
 104         unsigned int div = 1;
 105         u32 reg;
 106
 107         reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1);
 108         N = PARM_GET(MESON_N_WIDTH, MESON_N_SHIFT, reg);
 109
 110         reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL);
 111         sel = PARM_GET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg);
 112
 113         if (sel < 3)
 114                 div = sel + 1;
 115         else
 116                 div = 2 * N;
 117
 118         return parent_rate / div;
 119 }
 120
 121 static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu,
 122                                          struct clk_notifier_data *ndata)
 123 {
 124         u32 cpu_clk_cntl;
 125
 126         /* switch MUX1 to xtal */
 127         cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off
 128                                 + MESON_CPU_CLK_CNTL);
 129         cpu_clk_cntl &= ~MESON_CPU_CLK_MUX1;
 130         writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off
 131                                 + MESON_CPU_CLK_CNTL);
 132         udelay(100);
 133
 134         /* switch MUX2 to sys-pll */
 135         cpu_clk_cntl |= MESON_CPU_CLK_MUX2;
 136         writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off
 137                                 + MESON_CPU_CLK_CNTL);
 138
 139         return 0;
 140 }
 141
 142 static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu,
 143                                           struct clk_notifier_data *ndata)
 144 {
 145         u32 cpu_clk_cntl;
 146
 147         /* switch MUX1 to divisors' output */
 148         cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off
 149                                 + MESON_CPU_CLK_CNTL);
 150         cpu_clk_cntl |= MESON_CPU_CLK_MUX1;
 151         writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off
 152                                 + MESON_CPU_CLK_CNTL);
 153         udelay(100);
 154
 155         return 0;
 156 }
 157
 158 /*
 159  * This clock notifier is called when the frequency of the of the parent
 160  * PLL clock is to be changed. We use the xtal input as temporary parent
 161  * while the PLL frequency is stabilized.
 162  */
 163 static int meson_clk_cpu_notifier_cb(struct notifier_block *nb,
 164                                      unsigned long event, void *data)
 165 {
 166         struct clk_notifier_data *ndata = data;
 167         struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_nb(nb);
 168         int ret = 0;
 169
 170         if (event == PRE_RATE_CHANGE)
 171                 ret = meson_clk_cpu_pre_rate_change(clk_cpu, ndata);
 172         else if (event == POST_RATE_CHANGE)
 173                 ret = meson_clk_cpu_post_rate_change(clk_cpu, ndata);
 174
 175         return notifier_from_errno(ret);
 176 }
 177
 178 static const struct clk_ops meson_clk_cpu_ops = {
 179         .recalc_rate    = meson_clk_cpu_recalc_rate,
 180         .round_rate     = meson_clk_cpu_round_rate,
 181         .set_rate       = meson_clk_cpu_set_rate,
 182 };
 183
 184 struct clk *meson_clk_register_cpu(const struct clk_conf *clk_conf,
 185                                    void __iomem *reg_base,
 186                                    spinlock_t *lock)
 187 {
 188         struct clk *clk;
 189         struct clk *pclk;
 190         struct meson_clk_cpu *clk_cpu;
 191         struct clk_init_data init;
 192         int ret;
 193
 194         clk_cpu = kzalloc(sizeof(*clk_cpu), GFP_KERNEL);
 195         if (!clk_cpu)
 196                 return ERR_PTR(-ENOMEM);
 197
 198         clk_cpu->base = reg_base;
 199         clk_cpu->reg_off = clk_conf->reg_off;
 200         clk_cpu->div_table = clk_conf->conf.div_table;
 201         clk_cpu->clk_nb.notifier_call = meson_clk_cpu_notifier_cb;
 202
 203         init.name = clk_conf->clk_name;
 204         init.ops = &meson_clk_cpu_ops;
 205         init.flags = clk_conf->flags | CLK_GET_RATE_NOCACHE;
 206         init.flags |= CLK_SET_RATE_PARENT;
 207         init.parent_names = clk_conf->clks_parent;
 208         init.num_parents = 1;
 209
 210         clk_cpu->hw.init = &init;
 211
 212         pclk = __clk_lookup(clk_conf->clks_parent[0]);
 213         if (!pclk) {
 214                 pr_err("%s: could not lookup parent clock %s\n",
 215                                 __func__, clk_conf->clks_parent[0]);
 216                 ret = -EINVAL;
 217                 goto free_clk;
 218         }
 219
 220         ret = clk_notifier_register(pclk, &clk_cpu->clk_nb);
 221         if (ret) {
 222                 pr_err("%s: failed to register clock notifier for %s\n",
 223                                 __func__, clk_conf->clk_name);
 224                 goto free_clk;
 225         }
 226
 227         clk = clk_register(NULL, &clk_cpu->hw);
 228         if (IS_ERR(clk)) {
 229                 ret = PTR_ERR(clk);
 230                 goto unregister_clk_nb;
 231         }
 232
 233         return clk;
 234
 235 unregister_clk_nb:
 236         clk_notifier_unregister(pclk, &clk_cpu->clk_nb);
 237 free_clk:
 238         kfree(clk_cpu);
 239
 240         return ERR_PTR(ret);
 241 }
 242