2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __DRV_CLK_MTK_H
16 #define __DRV_CLK_MTK_H
18 #include <linux/regmap.h>
19 #include <linux/bitops.h>
20 #include <linux/clk-provider.h>
24 #define MAX_MUX_GATE_BIT 31
25 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
27 #define MHZ (1000 * 1000)
29 struct mtk_fixed_factor {
32 const char *parent_name;
37 #define FACTOR(_id, _name, _parent, _mult, _div) { \
40 .parent_name = _parent, \
45 extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
46 int num, struct clk_onecell_data *clk_data);
48 struct mtk_composite {
51 const char * const *parent_names;
59 signed char mux_shift;
60 signed char mux_width;
61 signed char gate_shift;
63 signed char divider_shift;
64 signed char divider_width;
66 signed char num_parents;
69 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
73 .mux_shift = _shift, \
74 .mux_width = _width, \
76 .gate_shift = _gate, \
77 .divider_shift = -1, \
78 .parent_names = _parents, \
79 .num_parents = ARRAY_SIZE(_parents), \
80 .flags = CLK_SET_RATE_PARENT, \
83 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \
87 .mux_shift = _shift, \
88 .mux_width = _width, \
90 .divider_shift = -1, \
91 .parent_names = _parents, \
92 .num_parents = ARRAY_SIZE(_parents), \
93 .flags = CLK_SET_RATE_PARENT, \
96 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
100 .divider_reg = _div_reg, \
101 .divider_shift = _div_shift, \
102 .divider_width = _div_width, \
103 .gate_reg = _gate_reg, \
104 .gate_shift = _gate_shift, \
109 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
110 void __iomem *base, spinlock_t *lock);
112 void mtk_clk_register_composites(const struct mtk_composite *mcs,
113 int num, void __iomem *base, spinlock_t *lock,
114 struct clk_onecell_data *clk_data);
116 struct mtk_gate_regs {
125 const char *parent_name;
126 const struct mtk_gate_regs *regs;
128 const struct clk_ops *ops;
131 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
132 int num, struct clk_onecell_data *clk_data);
134 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
136 #define HAVE_RST_BAR BIT(0)
138 struct mtk_pll_div_table {
143 struct mtk_pll_data {
153 const struct clk_ops *ops;
159 const struct mtk_pll_div_table *div_table;
162 void __init mtk_clk_register_plls(struct device_node *node,
163 const struct mtk_pll_data *plls, int num_plls,
164 struct clk_onecell_data *clk_data);
166 #ifdef CONFIG_RESET_CONTROLLER
167 void mtk_register_reset_controller(struct device_node *np,
168 unsigned int num_regs, int regofs);
170 static inline void mtk_register_reset_controller(struct device_node *np,
171 unsigned int num_regs, int regofs)
176 #endif /* __DRV_CLK_MTK_H */