drivers/clk/mediatek/clk-mtk.h

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: James Liao <jamesjj.liao@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __DRV_CLK_MTK_H
  16 #define __DRV_CLK_MTK_H
  17
  18 #include <linux/regmap.h>
  19 #include <linux/bitops.h>
  20 #include <linux/clk-provider.h>
  21
  22 struct clk;
  23
  24 #define MAX_MUX_GATE_BIT        31
  25 #define INVALID_MUX_GATE_BIT    (MAX_MUX_GATE_BIT + 1)
  26
  27 #define MHZ (1000 * 1000)
  28
  29 struct mtk_fixed_factor {
  30         int id;
  31         const char *name;
  32         const char *parent_name;
  33         int mult;
  34         int div;
  35 };
  36
  37 #define FACTOR(_id, _name, _parent, _mult, _div) {      \
  38                 .id = _id,                              \
  39                 .name = _name,                          \
  40                 .parent_name = _parent,                 \
  41                 .mult = _mult,                          \
  42                 .div = _div,                            \
  43         }
  44
  45 extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
  46                 int num, struct clk_onecell_data *clk_data);
  47
  48 struct mtk_composite {
  49         int id;
  50         const char *name;
  51         const char * const *parent_names;
  52         const char *parent;
  53         unsigned flags;
  54
  55         uint32_t mux_reg;
  56         uint32_t divider_reg;
  57         uint32_t gate_reg;
  58
  59         signed char mux_shift;
  60         signed char mux_width;
  61         signed char gate_shift;
  62
  63         signed char divider_shift;
  64         signed char divider_width;
  65
  66         signed char num_parents;
  67 };
  68
  69 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) {   \
  70                 .id = _id,                                              \
  71                 .name = _name,                                          \
  72                 .mux_reg = _reg,                                        \
  73                 .mux_shift = _shift,                                    \
  74                 .mux_width = _width,                                    \
  75                 .gate_reg = _reg,                                       \
  76                 .gate_shift = _gate,                                    \
  77                 .divider_shift = -1,                                    \
  78                 .parent_names = _parents,                               \
  79                 .num_parents = ARRAY_SIZE(_parents),                    \
  80                 .flags = CLK_SET_RATE_PARENT,                           \
  81         }
  82
  83 #define MUX(_id, _name, _parents, _reg, _shift, _width) {               \
  84                 .id = _id,                                              \
  85                 .name = _name,                                          \
  86                 .mux_reg = _reg,                                        \
  87                 .mux_shift = _shift,                                    \
  88                 .mux_width = _width,                                    \
  89                 .gate_shift = -1,                                       \
  90                 .divider_shift = -1,                                    \
  91                 .parent_names = _parents,                               \
  92                 .num_parents = ARRAY_SIZE(_parents),                    \
  93                 .flags = CLK_SET_RATE_PARENT,                           \
  94         }
  95
  96 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) {       \
  97                 .id = _id,                                              \
  98                 .parent = _parent,                                      \
  99                 .name = _name,                                          \
 100                 .divider_reg = _div_reg,                                \
 101                 .divider_shift = _div_shift,                            \
 102                 .divider_width = _div_width,                            \
 103                 .gate_reg = _gate_reg,                                  \
 104                 .gate_shift = _gate_shift,                              \
 105                 .mux_shift = -1,                                        \
 106                 .flags = 0,                                             \
 107         }
 108
 109 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
 110                 void __iomem *base, spinlock_t *lock);
 111
 112 void mtk_clk_register_composites(const struct mtk_composite *mcs,
 113                 int num, void __iomem *base, spinlock_t *lock,
 114                 struct clk_onecell_data *clk_data);
 115
 116 struct mtk_gate_regs {
 117         u32 sta_ofs;
 118         u32 clr_ofs;
 119         u32 set_ofs;
 120 };
 121
 122 struct mtk_gate {
 123         int id;
 124         const char *name;
 125         const char *parent_name;
 126         const struct mtk_gate_regs *regs;
 127         int shift;
 128         const struct clk_ops *ops;
 129 };
 130
 131 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
 132                 int num, struct clk_onecell_data *clk_data);
 133
 134 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 135
 136 #define HAVE_RST_BAR    BIT(0)
 137
 138 struct mtk_pll_div_table {
 139         u32 div;
 140         unsigned long freq;
 141 };
 142
 143 struct mtk_pll_data {
 144         int id;
 145         const char *name;
 146         uint32_t reg;
 147         uint32_t pwr_reg;
 148         uint32_t en_mask;
 149         uint32_t pd_reg;
 150         uint32_t tuner_reg;
 151         int pd_shift;
 152         unsigned int flags;
 153         const struct clk_ops *ops;
 154         u32 rst_bar_mask;
 155         unsigned long fmax;
 156         int pcwbits;
 157         uint32_t pcw_reg;
 158         int pcw_shift;
 159         const struct mtk_pll_div_table *div_table;
 160 };
 161
 162 void __init mtk_clk_register_plls(struct device_node *node,
 163                 const struct mtk_pll_data *plls, int num_plls,
 164                 struct clk_onecell_data *clk_data);
 165
 166 #ifdef CONFIG_RESET_CONTROLLER
 167 void mtk_register_reset_controller(struct device_node *np,
 168                         unsigned int num_regs, int regofs);
 169 #else
 170 static inline void mtk_register_reset_controller(struct device_node *np,
 171                         unsigned int num_regs, int regofs)
 172 {
 173 }
 174 #endif
 175
 176 #endif /* __DRV_CLK_MTK_H */