1 #include <linux/kernel.h>
4 #include <linux/errno.h>
5 #include <linux/delay.h>
6 #include <linux/slab.h>
13 #define to_clk_pllv2(clk) (container_of(clk, struct clk_pllv2, clk))
15 /* PLL Register Offsets */
16 #define MXC_PLL_DP_CTL 0x00
17 #define MXC_PLL_DP_CONFIG 0x04
18 #define MXC_PLL_DP_OP 0x08
19 #define MXC_PLL_DP_MFD 0x0C
20 #define MXC_PLL_DP_MFN 0x10
21 #define MXC_PLL_DP_MFNMINUS 0x14
22 #define MXC_PLL_DP_MFNPLUS 0x18
23 #define MXC_PLL_DP_HFS_OP 0x1C
24 #define MXC_PLL_DP_HFS_MFD 0x20
25 #define MXC_PLL_DP_HFS_MFN 0x24
26 #define MXC_PLL_DP_MFN_TOGC 0x28
27 #define MXC_PLL_DP_DESTAT 0x2c
29 /* PLL Register Bit definitions */
30 #define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
31 #define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
32 #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
33 #define MXC_PLL_DP_CTL_ADE 0x800
34 #define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
35 #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
36 #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
37 #define MXC_PLL_DP_CTL_HFSM 0x80
38 #define MXC_PLL_DP_CTL_PRE 0x40
39 #define MXC_PLL_DP_CTL_UPEN 0x20
40 #define MXC_PLL_DP_CTL_RST 0x10
41 #define MXC_PLL_DP_CTL_RCP 0x8
42 #define MXC_PLL_DP_CTL_PLM 0x4
43 #define MXC_PLL_DP_CTL_BRM0 0x2
44 #define MXC_PLL_DP_CTL_LRF 0x1
46 #define MXC_PLL_DP_CONFIG_BIST 0x8
47 #define MXC_PLL_DP_CONFIG_SJC_CE 0x4
48 #define MXC_PLL_DP_CONFIG_AREN 0x2
49 #define MXC_PLL_DP_CONFIG_LDREQ 0x1
51 #define MXC_PLL_DP_OP_MFI_OFFSET 4
52 #define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
53 #define MXC_PLL_DP_OP_PDF_OFFSET 0
54 #define MXC_PLL_DP_OP_PDF_MASK 0xF
56 #define MXC_PLL_DP_MFD_OFFSET 0
57 #define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
59 #define MXC_PLL_DP_MFN_OFFSET 0x0
60 #define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
62 #define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
63 #define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
64 #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
65 #define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
67 #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
68 #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
70 #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
77 static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
78 u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn)
80 long mfi, mfn, mfd, pdf, ref_clk;
84 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
86 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
87 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
88 mfi = (mfi <= 5) ? 5 : mfi;
89 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
90 mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
91 mfn = sign_extend32(mfn, 26);
93 ref_clk = 2 * parent_rate;
98 temp = (u64) ref_clk * abs(mfn);
99 do_div(temp, mfd + 1);
102 temp = (ref_clk * mfi) + temp;
107 static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw,
108 unsigned long parent_rate)
110 u32 dp_op, dp_mfd, dp_mfn, dp_ctl;
111 void __iomem *pllbase;
112 struct clk_pllv2 *pll = to_clk_pllv2(hw);
116 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
117 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
118 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
119 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
121 return __clk_pllv2_recalc_rate(parent_rate, dp_ctl, dp_op, dp_mfd, dp_mfn);
124 static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
125 u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn)
128 long mfi, pdf, mfn, mfd = 999999;
130 unsigned long quad_parent_rate;
132 quad_parent_rate = 4 * parent_rate;
134 while (++pdf < 16 && mfi < 5)
135 mfi = rate * (pdf+1) / quad_parent_rate;
140 temp64 = rate * (pdf + 1) - quad_parent_rate * mfi;
141 do_div(temp64, quad_parent_rate / 1000000);
144 reg = mfi << 4 | pdf;
153 static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
154 unsigned long parent_rate)
156 struct clk_pllv2 *pll = to_clk_pllv2(hw);
157 void __iomem *pllbase;
158 u32 dp_ctl, dp_op, dp_mfd, dp_mfn;
164 ret = __clk_pllv2_set_rate(rate, parent_rate, &dp_op, &dp_mfd, &dp_mfn);
168 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
170 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
172 __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP);
173 __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD);
174 __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN);
179 static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
180 unsigned long *prate)
182 u32 dp_op, dp_mfd, dp_mfn;
184 __clk_pllv2_set_rate(rate, *prate, &dp_op, &dp_mfd, &dp_mfn);
185 return __clk_pllv2_recalc_rate(*prate, MXC_PLL_DP_CTL_DPDCK0_2_EN,
186 dp_op, dp_mfd, dp_mfn);
189 static int clk_pllv2_prepare(struct clk_hw *hw)
191 struct clk_pllv2 *pll = to_clk_pllv2(hw);
193 void __iomem *pllbase;
197 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
198 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
202 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
203 if (reg & MXC_PLL_DP_CTL_LRF)
207 } while (++i < MAX_DPLL_WAIT_TRIES);
209 if (i == MAX_DPLL_WAIT_TRIES) {
210 pr_err("MX5: pll locking failed\n");
217 static void clk_pllv2_unprepare(struct clk_hw *hw)
219 struct clk_pllv2 *pll = to_clk_pllv2(hw);
221 void __iomem *pllbase;
224 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
225 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
228 static struct clk_ops clk_pllv2_ops = {
229 .prepare = clk_pllv2_prepare,
230 .unprepare = clk_pllv2_unprepare,
231 .recalc_rate = clk_pllv2_recalc_rate,
232 .round_rate = clk_pllv2_round_rate,
233 .set_rate = clk_pllv2_set_rate,
236 struct clk *imx_clk_pllv2(const char *name, const char *parent,
239 struct clk_pllv2 *pll;
241 struct clk_init_data init;
243 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
245 return ERR_PTR(-ENOMEM);
250 init.ops = &clk_pllv2_ops;
252 init.parent_names = &parent;
253 init.num_parents = 1;
255 pll->hw.init = &init;
257 clk = clk_register(NULL, &pll->hw);