2 * drivers/clk/at91/clk-slow.c
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
13 #include <linux/clk-provider.h>
14 #include <linux/clkdev.h>
15 #include <linux/clk/at91_pmc.h>
16 #include <linux/delay.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/sched.h>
24 #include <linux/wait.h>
29 #define SLOW_CLOCK_FREQ 32768
30 #define SLOWCK_SW_CYCLES 5
31 #define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
34 #define AT91_SCKC_CR 0x00
35 #define AT91_SCKC_RCEN (1 << 0)
36 #define AT91_SCKC_OSC32EN (1 << 1)
37 #define AT91_SCKC_OSC32BYP (1 << 2)
38 #define AT91_SCKC_OSCSEL (1 << 3)
43 unsigned long startup_usec;
46 #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
48 struct clk_slow_rc_osc {
51 unsigned long frequency;
52 unsigned long accuracy;
53 unsigned long startup_usec;
56 #define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
58 struct clk_sam9260_slow {
63 #define to_clk_sam9260_slow(hw) container_of(hw, struct clk_sam9260_slow, hw)
65 struct clk_sam9x5_slow {
71 #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
73 static struct clk *slow_clk;
75 static int clk_slow_osc_prepare(struct clk_hw *hw)
77 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
78 void __iomem *sckcr = osc->sckcr;
79 u32 tmp = readl(sckcr);
81 if (tmp & AT91_SCKC_OSC32BYP)
84 writel(tmp | AT91_SCKC_OSC32EN, sckcr);
86 usleep_range(osc->startup_usec, osc->startup_usec + 1);
91 static void clk_slow_osc_unprepare(struct clk_hw *hw)
93 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
94 void __iomem *sckcr = osc->sckcr;
95 u32 tmp = readl(sckcr);
97 if (tmp & AT91_SCKC_OSC32BYP)
100 writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
103 static int clk_slow_osc_is_prepared(struct clk_hw *hw)
105 struct clk_slow_osc *osc = to_clk_slow_osc(hw);
106 void __iomem *sckcr = osc->sckcr;
107 u32 tmp = readl(sckcr);
109 if (tmp & AT91_SCKC_OSC32BYP)
112 return !!(tmp & AT91_SCKC_OSC32EN);
115 static const struct clk_ops slow_osc_ops = {
116 .prepare = clk_slow_osc_prepare,
117 .unprepare = clk_slow_osc_unprepare,
118 .is_prepared = clk_slow_osc_is_prepared,
121 static struct clk * __init
122 at91_clk_register_slow_osc(void __iomem *sckcr,
124 const char *parent_name,
125 unsigned long startup,
128 struct clk_slow_osc *osc;
129 struct clk *clk = NULL;
130 struct clk_init_data init;
132 if (!sckcr || !name || !parent_name)
133 return ERR_PTR(-EINVAL);
135 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
137 return ERR_PTR(-ENOMEM);
140 init.ops = &slow_osc_ops;
141 init.parent_names = &parent_name;
142 init.num_parents = 1;
143 init.flags = CLK_IGNORE_UNUSED;
145 osc->hw.init = &init;
147 osc->startup_usec = startup;
150 writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
153 clk = clk_register(NULL, &osc->hw);
160 void __init of_at91sam9x5_clk_slow_osc_setup(struct device_node *np,
164 const char *parent_name;
165 const char *name = np->name;
169 parent_name = of_clk_get_parent_name(np, 0);
170 of_property_read_string(np, "clock-output-names", &name);
171 of_property_read_u32(np, "atmel,startup-time-usec", &startup);
172 bypass = of_property_read_bool(np, "atmel,osc-bypass");
174 clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup,
179 of_clk_add_provider(np, of_clk_src_simple_get, clk);
182 static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
183 unsigned long parent_rate)
185 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
187 return osc->frequency;
190 static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
191 unsigned long parent_acc)
193 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
195 return osc->accuracy;
198 static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
200 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
201 void __iomem *sckcr = osc->sckcr;
203 writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
205 usleep_range(osc->startup_usec, osc->startup_usec + 1);
210 static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
212 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
213 void __iomem *sckcr = osc->sckcr;
215 writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
218 static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
220 struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
222 return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
225 static const struct clk_ops slow_rc_osc_ops = {
226 .prepare = clk_slow_rc_osc_prepare,
227 .unprepare = clk_slow_rc_osc_unprepare,
228 .is_prepared = clk_slow_rc_osc_is_prepared,
229 .recalc_rate = clk_slow_rc_osc_recalc_rate,
230 .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
233 static struct clk * __init
234 at91_clk_register_slow_rc_osc(void __iomem *sckcr,
236 unsigned long frequency,
237 unsigned long accuracy,
238 unsigned long startup)
240 struct clk_slow_rc_osc *osc;
241 struct clk *clk = NULL;
242 struct clk_init_data init;
245 return ERR_PTR(-EINVAL);
247 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
249 return ERR_PTR(-ENOMEM);
252 init.ops = &slow_rc_osc_ops;
253 init.parent_names = NULL;
254 init.num_parents = 0;
255 init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
257 osc->hw.init = &init;
259 osc->frequency = frequency;
260 osc->accuracy = accuracy;
261 osc->startup_usec = startup;
263 clk = clk_register(NULL, &osc->hw);
270 void __init of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np,
277 const char *name = np->name;
279 of_property_read_string(np, "clock-output-names", &name);
280 of_property_read_u32(np, "clock-frequency", &frequency);
281 of_property_read_u32(np, "clock-accuracy", &accuracy);
282 of_property_read_u32(np, "atmel,startup-time-usec", &startup);
284 clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy,
289 of_clk_add_provider(np, of_clk_src_simple_get, clk);
292 static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
294 struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
295 void __iomem *sckcr = slowck->sckcr;
303 if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
304 (index && (tmp & AT91_SCKC_OSCSEL)))
308 tmp |= AT91_SCKC_OSCSEL;
310 tmp &= ~AT91_SCKC_OSCSEL;
314 usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
319 static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
321 struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
323 return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
326 static const struct clk_ops sam9x5_slow_ops = {
327 .set_parent = clk_sam9x5_slow_set_parent,
328 .get_parent = clk_sam9x5_slow_get_parent,
331 static struct clk * __init
332 at91_clk_register_sam9x5_slow(void __iomem *sckcr,
334 const char **parent_names,
337 struct clk_sam9x5_slow *slowck;
338 struct clk *clk = NULL;
339 struct clk_init_data init;
341 if (!sckcr || !name || !parent_names || !num_parents)
342 return ERR_PTR(-EINVAL);
344 slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
346 return ERR_PTR(-ENOMEM);
349 init.ops = &sam9x5_slow_ops;
350 init.parent_names = parent_names;
351 init.num_parents = num_parents;
354 slowck->hw.init = &init;
355 slowck->sckcr = sckcr;
356 slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
358 clk = clk_register(NULL, &slowck->hw);
367 void __init of_at91sam9x5_clk_slow_setup(struct device_node *np,
371 const char *parent_names[2];
373 const char *name = np->name;
376 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
377 if (num_parents <= 0 || num_parents > 2)
380 for (i = 0; i < num_parents; ++i) {
381 parent_names[i] = of_clk_get_parent_name(np, i);
382 if (!parent_names[i])
386 of_property_read_string(np, "clock-output-names", &name);
388 clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names,
393 of_clk_add_provider(np, of_clk_src_simple_get, clk);
396 static u8 clk_sam9260_slow_get_parent(struct clk_hw *hw)
398 struct clk_sam9260_slow *slowck = to_clk_sam9260_slow(hw);
400 return !!(pmc_read(slowck->pmc, AT91_PMC_SR) & AT91_PMC_OSCSEL);
403 static const struct clk_ops sam9260_slow_ops = {
404 .get_parent = clk_sam9260_slow_get_parent,
407 static struct clk * __init
408 at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
410 const char **parent_names,
413 struct clk_sam9260_slow *slowck;
414 struct clk *clk = NULL;
415 struct clk_init_data init;
418 return ERR_PTR(-EINVAL);
420 if (!parent_names || !num_parents)
421 return ERR_PTR(-EINVAL);
423 slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
425 return ERR_PTR(-ENOMEM);
428 init.ops = &sam9260_slow_ops;
429 init.parent_names = parent_names;
430 init.num_parents = num_parents;
433 slowck->hw.init = &init;
436 clk = clk_register(NULL, &slowck->hw);
445 void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
446 struct at91_pmc *pmc)
449 const char *parent_names[2];
451 const char *name = np->name;
454 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
455 if (num_parents != 2)
458 for (i = 0; i < num_parents; ++i) {
459 parent_names[i] = of_clk_get_parent_name(np, i);
460 if (!parent_names[i])
464 of_property_read_string(np, "clock-output-names", &name);
466 clk = at91_clk_register_sam9260_slow(pmc, name, parent_names,
471 of_clk_add_provider(np, of_clk_src_simple_get, clk);
475 * FIXME: All slow clk users are not properly claiming it (get + prepare +
476 * enable) before using it.
477 * If all users properly claiming this clock decide that they don't need it
478 * anymore (or are removed), it is disabled while faulty users are still
479 * requiring it, and the system hangs.
480 * Prevent this clock from being disabled until all users are properly
482 * Once this is done we should remove this function and the slow_clk variable.
484 static int __init of_at91_clk_slow_retain(void)
490 clk_prepare_enable(slow_clk);
494 arch_initcall(of_at91_clk_slow_retain);