2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk/at91_pmc.h>
14 #include <linux/delay.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/sched.h>
22 #include <linux/wait.h>
26 #define SLOW_CLOCK_FREQ 32768
28 #define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
30 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
31 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
33 #define MOR_KEY_MASK (0xff << 16)
39 wait_queue_head_t wait;
42 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
44 struct clk_main_rc_osc {
48 wait_queue_head_t wait;
49 unsigned long frequency;
50 unsigned long accuracy;
53 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
55 struct clk_rm9200_main {
60 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
62 struct clk_sam9x5_main {
66 wait_queue_head_t wait;
70 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
72 static irqreturn_t clk_main_osc_irq_handler(int irq, void *dev_id)
74 struct clk_main_osc *osc = dev_id;
77 disable_irq_nosync(osc->irq);
82 static int clk_main_osc_prepare(struct clk_hw *hw)
84 struct clk_main_osc *osc = to_clk_main_osc(hw);
85 struct at91_pmc *pmc = osc->pmc;
88 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
89 if (tmp & AT91_PMC_OSCBYPASS)
92 if (!(tmp & AT91_PMC_MOSCEN)) {
93 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
94 pmc_write(pmc, AT91_CKGR_MOR, tmp);
97 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
100 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
106 static void clk_main_osc_unprepare(struct clk_hw *hw)
108 struct clk_main_osc *osc = to_clk_main_osc(hw);
109 struct at91_pmc *pmc = osc->pmc;
110 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
112 if (tmp & AT91_PMC_OSCBYPASS)
115 if (!(tmp & AT91_PMC_MOSCEN))
118 tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
119 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
122 static int clk_main_osc_is_prepared(struct clk_hw *hw)
124 struct clk_main_osc *osc = to_clk_main_osc(hw);
125 struct at91_pmc *pmc = osc->pmc;
126 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
128 if (tmp & AT91_PMC_OSCBYPASS)
131 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS) &&
132 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN));
135 static const struct clk_ops main_osc_ops = {
136 .prepare = clk_main_osc_prepare,
137 .unprepare = clk_main_osc_unprepare,
138 .is_prepared = clk_main_osc_is_prepared,
141 static struct clk * __init
142 at91_clk_register_main_osc(struct at91_pmc *pmc,
145 const char *parent_name,
149 struct clk_main_osc *osc;
150 struct clk *clk = NULL;
151 struct clk_init_data init;
153 if (!pmc || !irq || !name || !parent_name)
154 return ERR_PTR(-EINVAL);
156 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
158 return ERR_PTR(-ENOMEM);
161 init.ops = &main_osc_ops;
162 init.parent_names = &parent_name;
163 init.num_parents = 1;
164 init.flags = CLK_IGNORE_UNUSED;
166 osc->hw.init = &init;
170 init_waitqueue_head(&osc->wait);
171 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
172 ret = request_irq(osc->irq, clk_main_osc_irq_handler,
173 IRQF_TRIGGER_HIGH, name, osc);
178 pmc_write(pmc, AT91_CKGR_MOR,
179 (pmc_read(pmc, AT91_CKGR_MOR) &
180 ~(MOR_KEY_MASK | AT91_PMC_MOSCEN)) |
181 AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
183 clk = clk_register(NULL, &osc->hw);
192 void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np,
193 struct at91_pmc *pmc)
197 const char *name = np->name;
198 const char *parent_name;
201 of_property_read_string(np, "clock-output-names", &name);
202 bypass = of_property_read_bool(np, "atmel,osc-bypass");
203 parent_name = of_clk_get_parent_name(np, 0);
205 irq = irq_of_parse_and_map(np, 0);
209 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass);
213 of_clk_add_provider(np, of_clk_src_simple_get, clk);
216 static irqreturn_t clk_main_rc_osc_irq_handler(int irq, void *dev_id)
218 struct clk_main_rc_osc *osc = dev_id;
221 disable_irq_nosync(osc->irq);
226 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
228 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
229 struct at91_pmc *pmc = osc->pmc;
232 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
234 if (!(tmp & AT91_PMC_MOSCRCEN)) {
235 tmp |= AT91_PMC_MOSCRCEN | AT91_PMC_KEY;
236 pmc_write(pmc, AT91_CKGR_MOR, tmp);
239 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS)) {
240 enable_irq(osc->irq);
241 wait_event(osc->wait,
242 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS);
248 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
250 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
251 struct at91_pmc *pmc = osc->pmc;
252 u32 tmp = pmc_read(pmc, AT91_CKGR_MOR);
254 if (!(tmp & AT91_PMC_MOSCRCEN))
257 tmp &= ~(MOR_KEY_MASK | AT91_PMC_MOSCRCEN);
258 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
261 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
263 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
264 struct at91_pmc *pmc = osc->pmc;
266 return !!((pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCRCS) &&
267 (pmc_read(pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCRCEN));
270 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
271 unsigned long parent_rate)
273 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
275 return osc->frequency;
278 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
279 unsigned long parent_acc)
281 struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
283 return osc->accuracy;
286 static const struct clk_ops main_rc_osc_ops = {
287 .prepare = clk_main_rc_osc_prepare,
288 .unprepare = clk_main_rc_osc_unprepare,
289 .is_prepared = clk_main_rc_osc_is_prepared,
290 .recalc_rate = clk_main_rc_osc_recalc_rate,
291 .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
294 static struct clk * __init
295 at91_clk_register_main_rc_osc(struct at91_pmc *pmc,
298 u32 frequency, u32 accuracy)
301 struct clk_main_rc_osc *osc;
302 struct clk *clk = NULL;
303 struct clk_init_data init;
305 if (!pmc || !irq || !name || !frequency)
306 return ERR_PTR(-EINVAL);
308 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
310 return ERR_PTR(-ENOMEM);
313 init.ops = &main_rc_osc_ops;
314 init.parent_names = NULL;
315 init.num_parents = 0;
316 init.flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED;
318 osc->hw.init = &init;
321 osc->frequency = frequency;
322 osc->accuracy = accuracy;
324 init_waitqueue_head(&osc->wait);
325 irq_set_status_flags(osc->irq, IRQ_NOAUTOEN);
326 ret = request_irq(osc->irq, clk_main_rc_osc_irq_handler,
327 IRQF_TRIGGER_HIGH, name, osc);
331 clk = clk_register(NULL, &osc->hw);
340 void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np,
341 struct at91_pmc *pmc)
347 const char *name = np->name;
349 of_property_read_string(np, "clock-output-names", &name);
350 of_property_read_u32(np, "clock-frequency", &frequency);
351 of_property_read_u32(np, "clock-accuracy", &accuracy);
353 irq = irq_of_parse_and_map(np, 0);
357 clk = at91_clk_register_main_rc_osc(pmc, irq, name, frequency,
362 of_clk_add_provider(np, of_clk_src_simple_get, clk);
366 static int clk_main_probe_frequency(struct at91_pmc *pmc)
368 unsigned long prep_time, timeout;
371 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
374 tmp = pmc_read(pmc, AT91_CKGR_MCFR);
375 if (tmp & AT91_PMC_MAINRDY)
377 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
378 } while (time_before(prep_time, timeout));
383 static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
384 unsigned long parent_rate)
391 pr_warn("Main crystal frequency not set, using approximate value\n");
392 tmp = pmc_read(pmc, AT91_CKGR_MCFR);
393 if (!(tmp & AT91_PMC_MAINRDY))
396 return ((tmp & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
399 static int clk_rm9200_main_prepare(struct clk_hw *hw)
401 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
403 return clk_main_probe_frequency(clkmain->pmc);
406 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
408 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
410 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINRDY);
413 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
414 unsigned long parent_rate)
416 struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
418 return clk_main_recalc_rate(clkmain->pmc, parent_rate);
421 static const struct clk_ops rm9200_main_ops = {
422 .prepare = clk_rm9200_main_prepare,
423 .is_prepared = clk_rm9200_main_is_prepared,
424 .recalc_rate = clk_rm9200_main_recalc_rate,
427 static struct clk * __init
428 at91_clk_register_rm9200_main(struct at91_pmc *pmc,
430 const char *parent_name)
432 struct clk_rm9200_main *clkmain;
433 struct clk *clk = NULL;
434 struct clk_init_data init;
437 return ERR_PTR(-EINVAL);
440 return ERR_PTR(-EINVAL);
442 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
444 return ERR_PTR(-ENOMEM);
447 init.ops = &rm9200_main_ops;
448 init.parent_names = &parent_name;
449 init.num_parents = 1;
452 clkmain->hw.init = &init;
455 clk = clk_register(NULL, &clkmain->hw);
462 void __init of_at91rm9200_clk_main_setup(struct device_node *np,
463 struct at91_pmc *pmc)
466 const char *parent_name;
467 const char *name = np->name;
469 parent_name = of_clk_get_parent_name(np, 0);
470 of_property_read_string(np, "clock-output-names", &name);
472 clk = at91_clk_register_rm9200_main(pmc, name, parent_name);
476 of_clk_add_provider(np, of_clk_src_simple_get, clk);
479 static irqreturn_t clk_sam9x5_main_irq_handler(int irq, void *dev_id)
481 struct clk_sam9x5_main *clkmain = dev_id;
483 wake_up(&clkmain->wait);
484 disable_irq_nosync(clkmain->irq);
489 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
491 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
492 struct at91_pmc *pmc = clkmain->pmc;
494 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
495 enable_irq(clkmain->irq);
496 wait_event(clkmain->wait,
497 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
500 return clk_main_probe_frequency(pmc);
503 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
505 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
507 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
510 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
511 unsigned long parent_rate)
513 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
515 return clk_main_recalc_rate(clkmain->pmc, parent_rate);
518 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
520 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
521 struct at91_pmc *pmc = clkmain->pmc;
527 tmp = pmc_read(pmc, AT91_CKGR_MOR) & ~MOR_KEY_MASK;
529 if (index && !(tmp & AT91_PMC_MOSCSEL))
530 pmc_write(pmc, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
531 else if (!index && (tmp & AT91_PMC_MOSCSEL))
532 pmc_write(pmc, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
534 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS)) {
535 enable_irq(clkmain->irq);
536 wait_event(clkmain->wait,
537 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCSELS);
543 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
545 struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
547 return !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) & AT91_PMC_MOSCEN);
550 static const struct clk_ops sam9x5_main_ops = {
551 .prepare = clk_sam9x5_main_prepare,
552 .is_prepared = clk_sam9x5_main_is_prepared,
553 .recalc_rate = clk_sam9x5_main_recalc_rate,
554 .set_parent = clk_sam9x5_main_set_parent,
555 .get_parent = clk_sam9x5_main_get_parent,
558 static struct clk * __init
559 at91_clk_register_sam9x5_main(struct at91_pmc *pmc,
562 const char **parent_names,
566 struct clk_sam9x5_main *clkmain;
567 struct clk *clk = NULL;
568 struct clk_init_data init;
570 if (!pmc || !irq || !name)
571 return ERR_PTR(-EINVAL);
573 if (!parent_names || !num_parents)
574 return ERR_PTR(-EINVAL);
576 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
578 return ERR_PTR(-ENOMEM);
581 init.ops = &sam9x5_main_ops;
582 init.parent_names = parent_names;
583 init.num_parents = num_parents;
584 init.flags = CLK_SET_PARENT_GATE;
586 clkmain->hw.init = &init;
589 clkmain->parent = !!(pmc_read(clkmain->pmc, AT91_CKGR_MOR) &
591 init_waitqueue_head(&clkmain->wait);
592 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
593 ret = request_irq(clkmain->irq, clk_sam9x5_main_irq_handler,
594 IRQF_TRIGGER_HIGH, name, clkmain);
598 clk = clk_register(NULL, &clkmain->hw);
600 free_irq(clkmain->irq, clkmain);
607 void __init of_at91sam9x5_clk_main_setup(struct device_node *np,
608 struct at91_pmc *pmc)
611 const char *parent_names[2];
614 const char *name = np->name;
617 num_parents = of_clk_get_parent_count(np);
618 if (num_parents <= 0 || num_parents > 2)
621 for (i = 0; i < num_parents; ++i) {
622 parent_names[i] = of_clk_get_parent_name(np, i);
623 if (!parent_names[i])
627 of_property_read_string(np, "clock-output-names", &name);
629 irq = irq_of_parse_and_map(np, 0);
633 clk = at91_clk_register_sam9x5_main(pmc, irq, name, parent_names,
638 of_clk_add_provider(np, of_clk_src_simple_get, clk);